| Martin Roth | 5856240 | 2015-10-11 10:36:26 +0200 | [diff] [blame] | 1 | ## |
| 2 | ## This file is part of the coreboot project. |
| 3 | ## |
| 4 | ## Copyright (C) 2011 Google Inc. |
| 5 | ## Copyright (C) 2013-2014 Sage Electronic Engineering, LLC. |
| 6 | ## |
| 7 | ## This program is free software; you can redistribute it and/or modify |
| 8 | ## it under the terms of the GNU General Public License as published by |
| 9 | ## the Free Software Foundation; version 2 of the License. |
| 10 | ## |
| 11 | ## This program is distributed in the hope that it will be useful, |
| 12 | ## but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 13 | ## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 14 | ## GNU General Public License for more details. |
| 15 | ## |
| Martin Roth | 5856240 | 2015-10-11 10:36:26 +0200 | [diff] [blame] | 16 | |
| 17 | config SOUTHBRIDGE_INTEL_FSP_RANGELEY |
| 18 | bool |
| 19 | |
| 20 | if SOUTHBRIDGE_INTEL_FSP_RANGELEY |
| 21 | |
| 22 | config SOUTH_BRIDGE_OPTIONS # dummy |
| 23 | def_bool y |
| 24 | select IOAPIC |
| 25 | select HAVE_HARD_RESET |
| 26 | select HAVE_USBDEBUG |
| 27 | select USE_WATCHDOG_ON_BOOT |
| 28 | select PCIEXP_ASPM |
| 29 | select PCIEXP_COMMON_CLOCK |
| 30 | select SPI_FLASH |
| 31 | select HAVE_INTEL_FIRMWARE |
| 32 | |
| 33 | config EHCI_BAR |
| 34 | hex |
| 35 | default 0xfef00000 |
| 36 | |
| 37 | config EHCI_DEBUG_OFFSET |
| 38 | hex |
| 39 | default 0xa0 |
| 40 | |
| 41 | config SERIRQ_CONTINUOUS_MODE |
| 42 | bool |
| 43 | default n |
| 44 | help |
| 45 | If you set this option to y, the serial IRQ machine will be |
| 46 | operated in continuous mode. |
| 47 | |
| 48 | config HPET_MIN_TICKS |
| 49 | hex |
| 50 | default 0x80 |
| 51 | |
| 52 | config IFD_BIN_PATH |
| 53 | string |
| 54 | depends on HAVE_IFD_BIN |
| 55 | default "../intel/mainboard/intel/rangeley" |
| 56 | help |
| 57 | The path and filename to the descriptor.bin file. |
| 58 | |
| 59 | endif |