Marc Jones | 5a4554a | 2015-09-15 12:44:37 -0600 | [diff] [blame] | 1 | /* |
| 2 | * This file is part of the coreboot project. |
| 3 | * |
| 4 | * Copyright (C) 2008-2009 coresystems GmbH |
| 5 | * |
| 6 | * This program is free software; you can redistribute it and/or |
| 7 | * modify it under the terms of the GNU General Public License as |
| 8 | * published by the Free Software Foundation; version 2 of |
| 9 | * the License. |
| 10 | * |
| 11 | * This program is distributed in the hope that it will be useful, |
| 12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 14 | * GNU General Public License for more details. |
| 15 | * |
| 16 | * You should have received a copy of the GNU General Public License |
| 17 | * along with this program; if not, write to the Free Software |
| 18 | * Foundation, Inc. |
| 19 | */ |
| 20 | |
| 21 | |
| 22 | #include <device/device.h> |
| 23 | #include <device/pci.h> |
| 24 | #include <console/console.h> |
| 25 | #include <arch/io.h> |
| 26 | #include <cpu/cpu.h> |
| 27 | #include <cpu/x86/cache.h> |
| 28 | #include <cpu/x86/smm.h> |
| 29 | #include <string.h> |
| 30 | #include <cpu/intel/smm/gen1/smi.h> |
| 31 | #include "pch.h" |
| 32 | |
| 33 | /* While we read PMBASE dynamically in case it changed, let's |
| 34 | * initialize it with a sane value |
| 35 | */ |
| 36 | static u16 pmbase = DEFAULT_PMBASE; |
| 37 | |
| 38 | /** |
| 39 | * @brief read and clear PM1_STS |
| 40 | * @return PM1_STS register |
| 41 | */ |
| 42 | static u16 reset_pm1_status(void) |
| 43 | { |
| 44 | u16 reg16; |
| 45 | |
| 46 | reg16 = inw(pmbase + PM1_STS); |
| 47 | /* set status bits are cleared by writing 1 to them */ |
| 48 | outw(reg16, pmbase + PM1_STS); |
| 49 | |
| 50 | return reg16; |
| 51 | } |
| 52 | |
| 53 | static void dump_pm1_status(u16 pm1_sts) |
| 54 | { |
| 55 | printk(BIOS_DEBUG, "PM1_STS: "); |
| 56 | if (pm1_sts & (1 << 15)) printk(BIOS_DEBUG, "WAK "); |
| 57 | if (pm1_sts & (1 << 14)) printk(BIOS_DEBUG, "PCIEXPWAK "); |
| 58 | if (pm1_sts & (1 << 11)) printk(BIOS_DEBUG, "PRBTNOR "); |
| 59 | if (pm1_sts & (1 << 10)) printk(BIOS_DEBUG, "RTC "); |
| 60 | if (pm1_sts & (1 << 8)) printk(BIOS_DEBUG, "PWRBTN "); |
| 61 | if (pm1_sts & (1 << 5)) printk(BIOS_DEBUG, "GBL "); |
| 62 | if (pm1_sts & (1 << 4)) printk(BIOS_DEBUG, "BM "); |
| 63 | if (pm1_sts & (1 << 0)) printk(BIOS_DEBUG, "TMROF "); |
| 64 | printk(BIOS_DEBUG, "\n"); |
| 65 | } |
| 66 | |
| 67 | /** |
| 68 | * @brief read and clear SMI_STS |
| 69 | * @return SMI_STS register |
| 70 | */ |
| 71 | static u32 reset_smi_status(void) |
| 72 | { |
| 73 | u32 reg32; |
| 74 | |
| 75 | reg32 = inl(pmbase + SMI_STS); |
| 76 | /* set status bits are cleared by writing 1 to them */ |
| 77 | outl(reg32, pmbase + SMI_STS); |
| 78 | |
| 79 | return reg32; |
| 80 | } |
| 81 | |
| 82 | static void dump_smi_status(u32 smi_sts) |
| 83 | { |
| 84 | printk(BIOS_DEBUG, "SMI_STS: "); |
| 85 | if (smi_sts & (1 << 26)) printk(BIOS_DEBUG, "SPI "); |
| 86 | if (smi_sts & (1 << 25)) printk(BIOS_DEBUG, "EL_SMI "); |
| 87 | if (smi_sts & (1 << 21)) printk(BIOS_DEBUG, "MONITOR "); |
| 88 | if (smi_sts & (1 << 20)) printk(BIOS_DEBUG, "PCI_EXP_SMI "); |
| 89 | if (smi_sts & (1 << 18)) printk(BIOS_DEBUG, "INTEL_USB2 "); |
| 90 | if (smi_sts & (1 << 17)) printk(BIOS_DEBUG, "LEGACY_USB2 "); |
| 91 | if (smi_sts & (1 << 16)) printk(BIOS_DEBUG, "SMBUS_SMI "); |
| 92 | if (smi_sts & (1 << 15)) printk(BIOS_DEBUG, "SERIRQ_SMI "); |
| 93 | if (smi_sts & (1 << 14)) printk(BIOS_DEBUG, "PERIODIC "); |
| 94 | if (smi_sts & (1 << 13)) printk(BIOS_DEBUG, "TCO "); |
| 95 | if (smi_sts & (1 << 12)) printk(BIOS_DEBUG, "DEVMON "); |
| 96 | if (smi_sts & (1 << 11)) printk(BIOS_DEBUG, "MCSMI "); |
| 97 | if (smi_sts & (1 << 10)) printk(BIOS_DEBUG, "GPI "); |
| 98 | if (smi_sts & (1 << 9)) printk(BIOS_DEBUG, "GPE0 "); |
| 99 | if (smi_sts & (1 << 8)) printk(BIOS_DEBUG, "PM1 "); |
| 100 | if (smi_sts & (1 << 6)) printk(BIOS_DEBUG, "SWSMI_TMR "); |
| 101 | if (smi_sts & (1 << 5)) printk(BIOS_DEBUG, "APM "); |
| 102 | if (smi_sts & (1 << 4)) printk(BIOS_DEBUG, "SLP_SMI "); |
| 103 | if (smi_sts & (1 << 3)) printk(BIOS_DEBUG, "LEGACY_USB "); |
| 104 | if (smi_sts & (1 << 2)) printk(BIOS_DEBUG, "BIOS "); |
| 105 | printk(BIOS_DEBUG, "\n"); |
| 106 | } |
| 107 | |
| 108 | |
| 109 | /** |
| 110 | * @brief read and clear GPE0_STS |
| 111 | * @return GPE0_STS register |
| 112 | */ |
| 113 | static u32 reset_gpe0_status(void) |
| 114 | { |
| 115 | u32 reg32; |
| 116 | |
| 117 | reg32 = inl(pmbase + GPE0_STS); |
| 118 | /* set status bits are cleared by writing 1 to them */ |
| 119 | outl(reg32, pmbase + GPE0_STS); |
| 120 | |
| 121 | return reg32; |
| 122 | } |
| 123 | |
| 124 | static void dump_gpe0_status(u32 gpe0_sts) |
| 125 | { |
| 126 | int i; |
| 127 | printk(BIOS_DEBUG, "GPE0_STS: "); |
| 128 | for (i = 31; i >= 16; i--) { |
| 129 | if (gpe0_sts & (1 << i)) printk(BIOS_DEBUG, "GPIO%d ", (i-16)); |
| 130 | } |
| 131 | if (gpe0_sts & (1 << 14)) printk(BIOS_DEBUG, "USB4 "); |
| 132 | if (gpe0_sts & (1 << 13)) printk(BIOS_DEBUG, "PME_B0 "); |
| 133 | if (gpe0_sts & (1 << 12)) printk(BIOS_DEBUG, "USB3 "); |
| 134 | if (gpe0_sts & (1 << 11)) printk(BIOS_DEBUG, "PME "); |
| 135 | if (gpe0_sts & (1 << 10)) printk(BIOS_DEBUG, "EL_SCI/BATLOW "); |
| 136 | if (gpe0_sts & (1 << 9)) printk(BIOS_DEBUG, "PCI_EXP "); |
| 137 | if (gpe0_sts & (1 << 8)) printk(BIOS_DEBUG, "RI "); |
| 138 | if (gpe0_sts & (1 << 7)) printk(BIOS_DEBUG, "SMB_WAK "); |
| 139 | if (gpe0_sts & (1 << 6)) printk(BIOS_DEBUG, "TCO_SCI "); |
| 140 | if (gpe0_sts & (1 << 5)) printk(BIOS_DEBUG, "AC97 "); |
| 141 | if (gpe0_sts & (1 << 4)) printk(BIOS_DEBUG, "USB2 "); |
| 142 | if (gpe0_sts & (1 << 3)) printk(BIOS_DEBUG, "USB1 "); |
| 143 | if (gpe0_sts & (1 << 2)) printk(BIOS_DEBUG, "HOT_PLUG "); |
| 144 | if (gpe0_sts & (1 << 0)) printk(BIOS_DEBUG, "THRM "); |
| 145 | printk(BIOS_DEBUG, "\n"); |
| 146 | } |
| 147 | |
| 148 | |
| 149 | /** |
| 150 | * @brief read and clear ALT_GP_SMI_STS |
| 151 | * @return ALT_GP_SMI_STS register |
| 152 | */ |
| 153 | static u16 reset_alt_gp_smi_status(void) |
| 154 | { |
| 155 | u16 reg16; |
| 156 | |
| 157 | reg16 = inl(pmbase + ALT_GP_SMI_STS); |
| 158 | /* set status bits are cleared by writing 1 to them */ |
| 159 | outl(reg16, pmbase + ALT_GP_SMI_STS); |
| 160 | |
| 161 | return reg16; |
| 162 | } |
| 163 | |
| 164 | static void dump_alt_gp_smi_status(u16 alt_gp_smi_sts) |
| 165 | { |
| 166 | int i; |
| 167 | printk(BIOS_DEBUG, "ALT_GP_SMI_STS: "); |
| 168 | for (i = 15; i >= 0; i--) { |
| 169 | if (alt_gp_smi_sts & (1 << i)) printk(BIOS_DEBUG, "GPI%d ", i); |
| 170 | } |
| 171 | printk(BIOS_DEBUG, "\n"); |
| 172 | } |
| 173 | |
| 174 | |
| 175 | |
| 176 | /** |
| 177 | * @brief read and clear TCOx_STS |
| 178 | * @return TCOx_STS registers |
| 179 | */ |
| 180 | static u32 reset_tco_status(void) |
| 181 | { |
| 182 | u32 tcobase = pmbase + 0x60; |
| 183 | u32 reg32; |
| 184 | |
| 185 | reg32 = inl(tcobase + 0x04); |
| 186 | /* set status bits are cleared by writing 1 to them */ |
| 187 | outl(reg32 & ~(1<<18), tcobase + 0x04); // Don't clear BOOT_STS before SECOND_TO_STS |
| 188 | if (reg32 & (1 << 18)) |
| 189 | outl(reg32 & (1<<18), tcobase + 0x04); // clear BOOT_STS |
| 190 | |
| 191 | return reg32; |
| 192 | } |
| 193 | |
| 194 | |
| 195 | static void dump_tco_status(u32 tco_sts) |
| 196 | { |
| 197 | printk(BIOS_DEBUG, "TCO_STS: "); |
| 198 | if (tco_sts & (1 << 20)) printk(BIOS_DEBUG, "SMLINK_SLV "); |
| 199 | if (tco_sts & (1 << 18)) printk(BIOS_DEBUG, "BOOT "); |
| 200 | if (tco_sts & (1 << 17)) printk(BIOS_DEBUG, "SECOND_TO "); |
| 201 | if (tco_sts & (1 << 16)) printk(BIOS_DEBUG, "INTRD_DET "); |
| 202 | if (tco_sts & (1 << 12)) printk(BIOS_DEBUG, "DMISERR "); |
| 203 | if (tco_sts & (1 << 10)) printk(BIOS_DEBUG, "DMISMI "); |
| 204 | if (tco_sts & (1 << 9)) printk(BIOS_DEBUG, "DMISCI "); |
| 205 | if (tco_sts & (1 << 8)) printk(BIOS_DEBUG, "BIOSWR "); |
| 206 | if (tco_sts & (1 << 7)) printk(BIOS_DEBUG, "NEWCENTURY "); |
| 207 | if (tco_sts & (1 << 3)) printk(BIOS_DEBUG, "TIMEOUT "); |
| 208 | if (tco_sts & (1 << 2)) printk(BIOS_DEBUG, "TCO_INT "); |
| 209 | if (tco_sts & (1 << 1)) printk(BIOS_DEBUG, "SW_TCO "); |
| 210 | if (tco_sts & (1 << 0)) printk(BIOS_DEBUG, "NMI2SMI "); |
| 211 | printk(BIOS_DEBUG, "\n"); |
| 212 | } |
| 213 | |
| 214 | |
| 215 | |
| 216 | /** |
| 217 | * @brief Set the EOS bit |
| 218 | */ |
| 219 | static void smi_set_eos(void) |
| 220 | { |
| 221 | u8 reg8; |
| 222 | |
| 223 | reg8 = inb(pmbase + SMI_EN); |
| 224 | reg8 |= EOS; |
| 225 | outb(reg8, pmbase + SMI_EN); |
| 226 | } |
| 227 | |
| 228 | void southbridge_smm_init(void) |
| 229 | { |
| 230 | u32 smi_en; |
| 231 | u16 pm1_en; |
| 232 | u32 gpe0_en; |
| 233 | |
| 234 | #if CONFIG_ELOG |
| 235 | /* Log events from chipset before clearing */ |
| 236 | pch_log_state(); |
| 237 | #endif |
| 238 | |
| 239 | printk(BIOS_DEBUG, "Initializing southbridge SMI..."); |
| 240 | |
| 241 | pmbase = pci_read_config32(dev_find_slot(0, PCI_DEVFN(0x1f, 0)), |
| 242 | PMBASE) & 0xff80; |
| 243 | |
| 244 | printk(BIOS_SPEW, " ... pmbase = 0x%04x\n", pmbase); |
| 245 | |
| 246 | smi_en = inl(pmbase + SMI_EN); |
| 247 | if (smi_en & APMC_EN) { |
| 248 | printk(BIOS_INFO, "SMI# handler already enabled?\n"); |
| 249 | return; |
| 250 | } |
| 251 | |
| 252 | printk(BIOS_DEBUG, "\n"); |
| 253 | dump_smi_status(reset_smi_status()); |
| 254 | dump_pm1_status(reset_pm1_status()); |
| 255 | dump_gpe0_status(reset_gpe0_status()); |
| 256 | dump_alt_gp_smi_status(reset_alt_gp_smi_status()); |
| 257 | dump_tco_status(reset_tco_status()); |
| 258 | |
| 259 | /* Disable GPE0 PME_B0 */ |
| 260 | gpe0_en = inl(pmbase + GPE0_EN); |
| 261 | gpe0_en &= ~PME_B0_EN; |
| 262 | outl(gpe0_en, pmbase + GPE0_EN); |
| 263 | |
| 264 | pm1_en = 0; |
| 265 | pm1_en |= PWRBTN_EN; |
| 266 | pm1_en |= GBL_EN; |
| 267 | outw(pm1_en, pmbase + PM1_EN); |
| 268 | |
| 269 | /* Enable SMI generation: |
| 270 | * - on TCO events |
| 271 | * - on APMC writes (io 0xb2) |
| 272 | * - on writes to SLP_EN (sleep states) |
| 273 | * - on writes to GBL_RLS (bios commands) |
| 274 | * No SMIs: |
| 275 | * - on microcontroller writes (io 0x62/0x66) |
| 276 | */ |
| 277 | |
| 278 | smi_en = 0; /* reset SMI enables */ |
| 279 | |
| 280 | #if 0 |
| 281 | smi_en |= LEGACY_USB2_EN | LEGACY_USB_EN; |
| 282 | #endif |
| 283 | smi_en |= TCO_EN; |
| 284 | smi_en |= APMC_EN; |
| 285 | #if DEBUG_PERIODIC_SMIS |
| 286 | /* Set DEBUG_PERIODIC_SMIS in pch.h to debug using |
| 287 | * periodic SMIs. |
| 288 | */ |
| 289 | smi_en |= PERIODIC_EN; |
| 290 | #endif |
| 291 | smi_en |= SLP_SMI_EN; |
| 292 | #if 0 |
| 293 | smi_en |= BIOS_EN; |
| 294 | #endif |
| 295 | |
| 296 | /* The following need to be on for SMIs to happen */ |
| 297 | smi_en |= EOS | GBL_SMI_EN; |
| 298 | |
| 299 | outl(smi_en, pmbase + SMI_EN); |
| 300 | } |
| 301 | |
| 302 | void southbridge_trigger_smi(void) |
| 303 | { |
| 304 | /** |
| 305 | * There are several methods of raising a controlled SMI# via |
| 306 | * software, among them: |
| 307 | * - Writes to io 0xb2 (APMC) |
| 308 | * - Writes to the Local Apic ICR with Delivery mode SMI. |
| 309 | * |
| 310 | * Using the local apic is a bit more tricky. According to |
| 311 | * AMD Family 11 Processor BKDG no destination shorthand must be |
| 312 | * used. |
| 313 | * The whole SMM initialization is quite a bit hardware specific, so |
| 314 | * I'm not too worried about the better of the methods at the moment |
| 315 | */ |
| 316 | |
| 317 | /* raise an SMI interrupt */ |
| 318 | printk(BIOS_SPEW, " ... raise SMI#\n"); |
| 319 | outb(0x00, 0xb2); |
| 320 | } |
| 321 | |
| 322 | void southbridge_clear_smi_status(void) |
| 323 | { |
| 324 | /* Clear SMI status */ |
| 325 | reset_smi_status(); |
| 326 | |
| 327 | /* Clear PM1 status */ |
| 328 | reset_pm1_status(); |
| 329 | |
| 330 | /* Set EOS bit so other SMIs can occur. */ |
| 331 | smi_set_eos(); |
| 332 | } |
| 333 | |
| 334 | void smm_setup_structures(void *gnvs, void *tcg, void *smi1) |
| 335 | { |
| 336 | /* |
| 337 | * Issue SMI to set the gnvs pointer in SMM. |
| 338 | * tcg and smi1 are unused. |
| 339 | * |
| 340 | * EAX = APM_CNT_GNVS_UPDATE |
| 341 | * EBX = gnvs pointer |
| 342 | * EDX = APM_CNT |
| 343 | */ |
| 344 | asm volatile ( |
| 345 | "outb %%al, %%dx\n\t" |
| 346 | : /* ignore result */ |
| 347 | : "a" (APM_CNT_GNVS_UPDATE), |
| 348 | "b" ((u32)gnvs), |
| 349 | "d" (APM_CNT) |
| 350 | ); |
| 351 | } |