Marc Jones | 5a4554a | 2015-09-15 12:44:37 -0600 | [diff] [blame] | 1 | /* |
| 2 | * This file is part of the coreboot project. |
| 3 | * |
| 4 | * Copyright (C) 2011 The Chromium OS Authors. All rights reserved. |
| 5 | * Copyright (C) 2013 Sage Electronic Engineering, LLC. |
| 6 | * |
| 7 | * This program is free software; you can redistribute it and/or modify |
| 8 | * it under the terms of the GNU General Public License as published by |
| 9 | * the Free Software Foundation; version 2 of the License. |
| 10 | * |
| 11 | * This program is distributed in the hope that it will be useful, |
| 12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 14 | * GNU General Public License for more details. |
| 15 | * |
| 16 | * You should have received a copy of the GNU General Public License |
| 17 | * along with this program; if not, write to the Free Software |
| 18 | * Foundation, Inc. |
| 19 | */ |
| 20 | |
| 21 | #ifndef INTEL_I89XX_GPIO_H |
| 22 | #define INTEL_I89XX_GPIO_H |
| 23 | |
| 24 | #define GPIO_MODE_NATIVE 0 |
| 25 | #define GPIO_MODE_GPIO 1 |
| 26 | #define GPIO_MODE_NONE 1 |
| 27 | |
| 28 | #define GPIO_DIR_OUTPUT 0 |
| 29 | #define GPIO_DIR_INPUT 1 |
| 30 | |
| 31 | #define GPIO_NO_INVERT 0 |
| 32 | #define GPIO_INVERT 1 |
| 33 | |
| 34 | #define GPIO_LEVEL_LOW 0 |
| 35 | #define GPIO_LEVEL_HIGH 1 |
| 36 | |
| 37 | #define GPIO_NO_BLINK 0 |
| 38 | #define GPIO_BLINK 1 |
| 39 | |
| 40 | #define GPIO_RESET_PWROK 0 |
| 41 | #define GPIO_RESET_RSMRST 1 |
| 42 | |
| 43 | struct pch_gpio_set1 { |
| 44 | u32 gpio0 : 1; |
| 45 | u32 gpio1 : 1; |
| 46 | u32 gpio2 : 1; |
| 47 | u32 gpio3 : 1; |
| 48 | u32 gpio4 : 1; |
| 49 | u32 gpio5 : 1; |
| 50 | u32 gpio6 : 1; |
| 51 | u32 gpio7 : 1; |
| 52 | u32 gpio8 : 1; |
| 53 | u32 gpio9 : 1; |
| 54 | u32 gpio10 : 1; |
| 55 | u32 gpio11 : 1; |
| 56 | u32 gpio12 : 1; |
| 57 | u32 gpio13 : 1; |
| 58 | u32 gpio14 : 1; |
| 59 | u32 gpio15 : 1; |
| 60 | u32 gpio16 : 1; |
| 61 | u32 gpio17 : 1; |
| 62 | u32 gpio18 : 1; |
| 63 | u32 gpio19 : 1; |
| 64 | u32 gpio20 : 1; |
| 65 | u32 gpio21 : 1; |
| 66 | u32 gpio22 : 1; |
| 67 | u32 gpio23 : 1; |
| 68 | u32 gpio24 : 1; |
| 69 | u32 gpio25 : 1; |
| 70 | u32 gpio26 : 1; |
| 71 | u32 gpio27 : 1; |
| 72 | u32 gpio28 : 1; |
| 73 | u32 gpio29 : 1; |
| 74 | u32 gpio30 : 1; |
| 75 | u32 gpio31 : 1; |
| 76 | } __attribute__ ((packed)); |
| 77 | |
| 78 | struct pch_gpio_set2 { |
| 79 | u32 gpio32 : 1; |
| 80 | u32 gpio33 : 1; |
| 81 | u32 gpio34 : 1; |
| 82 | u32 gpio35 : 1; |
| 83 | u32 gpio36 : 1; |
| 84 | u32 gpio37 : 1; |
| 85 | u32 gpio38 : 1; |
| 86 | u32 gpio39 : 1; |
| 87 | u32 gpio40 : 1; |
| 88 | u32 gpio41 : 1; |
| 89 | u32 gpio42 : 1; |
| 90 | u32 gpio43 : 1; |
| 91 | u32 gpio44 : 1; |
| 92 | u32 gpio45 : 1; |
| 93 | u32 gpio46 : 1; |
| 94 | u32 gpio47 : 1; |
| 95 | u32 gpio48 : 1; |
| 96 | u32 gpio49 : 1; |
| 97 | u32 gpio50 : 1; |
| 98 | u32 gpio51 : 1; |
| 99 | u32 gpio52 : 1; |
| 100 | u32 gpio53 : 1; |
| 101 | u32 gpio54 : 1; |
| 102 | u32 gpio55 : 1; |
| 103 | u32 gpio56 : 1; |
| 104 | u32 gpio57 : 1; |
| 105 | u32 gpio58 : 1; |
| 106 | u32 gpio59 : 1; |
| 107 | u32 gpio60 : 1; |
| 108 | u32 gpio61 : 1; |
| 109 | u32 gpio62 : 1; |
| 110 | u32 gpio63 : 1; |
| 111 | } __attribute__ ((packed)); |
| 112 | |
| 113 | struct pch_gpio_set3 { |
| 114 | u32 gpio64 : 1; |
| 115 | u32 gpio65 : 1; |
| 116 | u32 gpio66 : 1; |
| 117 | u32 gpio67 : 1; |
| 118 | u32 gpio68 : 1; |
| 119 | u32 gpio69 : 1; |
| 120 | u32 gpio70 : 1; |
| 121 | u32 gpio71 : 1; |
| 122 | u32 gpio72 : 1; |
| 123 | u32 gpio73 : 1; |
| 124 | u32 gpio74 : 1; |
| 125 | u32 gpio75 : 1; |
| 126 | u32 fill_bitfield : 20; |
| 127 | } __attribute__ ((packed)); |
| 128 | |
| 129 | struct pch_gpio_map { |
| 130 | union { |
| 131 | struct { |
| 132 | const struct pch_gpio_set1 *mode; |
| 133 | const struct pch_gpio_set1 *direction; |
| 134 | const struct pch_gpio_set1 *level; |
| 135 | const struct pch_gpio_set1 *reset; |
| 136 | const struct pch_gpio_set1 *invert; |
| 137 | const struct pch_gpio_set1 *blink; |
| 138 | } set1; |
| 139 | struct { |
| 140 | const u32 *mode; |
| 141 | const u32 *direction; |
| 142 | const u32 *level; |
| 143 | const u32 *reset; |
| 144 | const u32 *invert; |
| 145 | const u32 *blink; |
| 146 | } set1_vals; |
| 147 | }; |
| 148 | |
| 149 | union { |
| 150 | struct { |
| 151 | const struct pch_gpio_set2 *mode; |
| 152 | const struct pch_gpio_set2 *direction; |
| 153 | const struct pch_gpio_set2 *level; |
| 154 | const struct pch_gpio_set2 *reset; |
| 155 | } set2; |
| 156 | struct { |
| 157 | const u32 *mode; |
| 158 | const u32 *direction; |
| 159 | const u32 *level; |
| 160 | const u32 *reset; |
| 161 | } set2_vals; |
| 162 | }; |
| 163 | |
| 164 | union { |
| 165 | struct { |
| 166 | const struct pch_gpio_set3 *mode; |
| 167 | const struct pch_gpio_set3 *direction; |
| 168 | const struct pch_gpio_set3 *level; |
| 169 | const struct pch_gpio_set3 *reset; |
| 170 | } set3; |
| 171 | struct { |
| 172 | const u32 *mode; |
| 173 | const u32 *direction; |
| 174 | const u32 *level; |
| 175 | const u32 *reset; |
| 176 | } set3_vals; |
| 177 | }; |
| 178 | }; |
| 179 | |
| 180 | /* Configure GPIOs with mainboard provided settings */ |
| 181 | void setup_pch_gpios(const struct pch_gpio_map *gpio); |
| 182 | |
| 183 | /* get GPIO and set pin values */ |
| 184 | int get_gpio(int gpio_num); |
| 185 | void set_gpio(int gpio_num); |
| 186 | void clear_gpio(int gpio_num); |
| 187 | |
| 188 | /* |
| 189 | * get a number comprised of multiple GPIO values. gpio_num_array points to |
| 190 | * the array of gpio pin numbers to scan, terminated by -1. |
| 191 | */ |
| 192 | unsigned get_gpios(const int *gpio_num_array); |
| 193 | |
| 194 | #endif |