| Marc Jones | 5a4554a | 2015-09-15 12:44:37 -0600 | [diff] [blame] | 1 | /* |
| 2 | * This file is part of the coreboot project. |
| 3 | * |
| 4 | * Copyright (C) 2011 The Chromium OS Authors. All rights reserved. |
| 5 | * Copyright (C) 2013 Sage Electronic Engineering, LLC. |
| 6 | * |
| 7 | * This program is free software; you can redistribute it and/or modify |
| 8 | * it under the terms of the GNU General Public License as published by |
| 9 | * the Free Software Foundation; version 2 of the License. |
| 10 | * |
| 11 | * This program is distributed in the hope that it will be useful, |
| 12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 14 | * GNU General Public License for more details. |
| 15 | * |
| 16 | * You should have received a copy of the GNU General Public License |
| 17 | * along with this program; if not, write to the Free Software |
| 18 | * Foundation, Inc. |
| 19 | */ |
| 20 | |
| 21 | #include <stdint.h> |
| 22 | #include <string.h> |
| 23 | #include <arch/io.h> |
| 24 | |
| 25 | #include "pch.h" |
| 26 | #include "gpio.h" |
| 27 | |
| 28 | #define MAX_GPIO_NUMBER 75 /* zero based */ |
| 29 | static const int gpio_reg_offsets[] = {GP_LVL, GP_LVL2, GP_LVL3}; |
| 30 | |
| 31 | void setup_pch_gpios(const struct pch_gpio_map *gpio) |
| 32 | { |
| 33 | u16 gpiobase = pci_read_config16(PCH_LPC_DEV, GPIO_BASE) & 0xfffc; |
| 34 | |
| 35 | /* GPIO Set 1 */ |
| 36 | if (gpio->set1.level) |
| 37 | outl(*((u32*)gpio->set1.level), gpiobase + GP_LVL); |
| 38 | if (gpio->set1.mode) |
| 39 | outl(*((u32*)gpio->set1.mode), gpiobase + GPIO_USE_SEL); |
| 40 | if (gpio->set1.direction) |
| 41 | outl(*((u32*)gpio->set1.direction), gpiobase + GP_IO_SEL); |
| 42 | if (gpio->set1.reset) |
| 43 | outl(*((u32*)gpio->set1.reset), gpiobase + GP_RST_SEL1); |
| 44 | if (gpio->set1.invert) |
| 45 | outl(*((u32*)gpio->set1.invert), gpiobase + GPI_INV); |
| 46 | if (gpio->set1.blink) |
| 47 | outl(*((u32*)gpio->set1.blink), gpiobase + GPO_BLINK); |
| 48 | |
| 49 | /* GPIO Set 2 */ |
| 50 | if (gpio->set2.level) |
| 51 | outl(*((u32*)gpio->set2.level), gpiobase + GP_LVL2); |
| 52 | if (gpio->set2.mode) |
| 53 | outl(*((u32*)gpio->set2.mode), gpiobase + GPIO_USE_SEL2); |
| 54 | if (gpio->set2.direction) |
| 55 | outl(*((u32*)gpio->set2.direction), gpiobase + GP_IO_SEL2); |
| 56 | if (gpio->set2.reset) |
| 57 | outl(*((u32*)gpio->set2.reset), gpiobase + GP_RST_SEL2); |
| 58 | |
| 59 | /* GPIO Set 3 */ |
| 60 | if (gpio->set3.level) |
| 61 | outl(*((u32*)gpio->set3.level), gpiobase + GP_LVL3); |
| 62 | if (gpio->set3.mode) |
| 63 | outl(*((u32*)gpio->set3.mode), gpiobase + GPIO_USE_SEL3); |
| 64 | if (gpio->set3.direction) |
| 65 | outl(*((u32*)gpio->set3.direction), gpiobase + GP_IO_SEL3); |
| 66 | if (gpio->set3.reset) |
| 67 | outl(*((u32*)gpio->set3.reset), gpiobase + GP_RST_SEL3); |
| 68 | } |
| 69 | |
| 70 | int get_gpio(int gpio_num) |
| 71 | { |
| 72 | u16 gpio_base = pci_read_config16(PCH_LPC_DEV, GPIO_BASE) & 0xfffc; |
| 73 | int index, bit; |
| 74 | |
| 75 | if (gpio_num > MAX_GPIO_NUMBER) |
| 76 | return 0; /* Just ignore wrong gpio numbers. */ |
| 77 | |
| 78 | index = gpio_num / 32; |
| 79 | bit = gpio_num % 32; |
| 80 | |
| 81 | return (inl(gpio_base + gpio_reg_offsets[index]) >> bit) & 1; |
| 82 | } |
| 83 | |
| 84 | void set_gpio(int gpio_num) |
| 85 | { |
| 86 | u16 gpio_base = pci_read_config16(PCH_LPC_DEV, GPIO_BASE) & 0xfffc; |
| 87 | u32 index, bit, level; |
| 88 | |
| 89 | if (gpio_num <= MAX_GPIO_NUMBER){ |
| 90 | |
| 91 | index = gpio_num / 32; |
| 92 | bit = gpio_num % 32; |
| 93 | level = inl(gpio_base + gpio_reg_offsets[index]); |
| 94 | |
| 95 | outl((gpio_base + gpio_reg_offsets[index]), level | (1UL << bit)); |
| 96 | |
| 97 | } |
| 98 | |
| 99 | return; |
| 100 | } |
| 101 | void clear_gpio(int gpio_num) |
| 102 | { |
| 103 | u16 gpio_base = pci_read_config16(PCH_LPC_DEV, GPIO_BASE) & 0xfffc; |
| 104 | u32 index, bit, level; |
| 105 | |
| 106 | if (gpio_num <= MAX_GPIO_NUMBER){ |
| 107 | index = gpio_num / 32; |
| 108 | bit = gpio_num % 32; |
| 109 | level = inl(gpio_base + gpio_reg_offsets[index]); |
| 110 | |
| 111 | outl((gpio_base + gpio_reg_offsets[index]), level & (~(1UL << bit))); |
| 112 | } |
| 113 | |
| 114 | return; |
| 115 | } |
| 116 | |
| 117 | |
| 118 | /* |
| 119 | * get a number comprised of multiple GPIO values. gpio_num_array points to |
| 120 | * the array of gpio pin numbers to scan, terminated by -1. |
| 121 | */ |
| 122 | unsigned get_gpios(const int *gpio_num_array) |
| 123 | { |
| 124 | int gpio; |
| 125 | unsigned bitmask = 1; |
| 126 | unsigned vector = 0; |
| 127 | |
| 128 | while (bitmask && |
| 129 | ((gpio = *gpio_num_array++) != -1)) { |
| 130 | if (get_gpio(gpio)) |
| 131 | vector |= bitmask; |
| 132 | bitmask <<= 1; |
| 133 | } |
| 134 | return vector; |
| 135 | } |