blob: 190535b6ccaa9dc894f29c2f203af403f79d9905 [file] [log] [blame]
Marc Jones5a4554a2015-09-15 12:44:37 -06001/*
2 * This file is part of the coreboot project.
3 *
4 * Copyright (C) 2008-2009 coresystems GmbH
5 * Copyright (C) 2012 Sage Electronic Engineering, LLC
6 *
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License as
9 * published by the Free Software Foundation; version 2 of
10 * the License.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc.
20 */
21
22#include <arch/io.h>
23#include <console/console.h>
24#include <device/pci_ids.h>
25#include <device/pci_def.h>
26#include "pch.h"
27#include "smbus.h"
28
29void enable_smbus(void)
30{
31 device_t dev;
32
33 /* Set the SMBus device statically. */
34 dev = PCI_DEV(0x0, 0x1f, 0x3);
35
36 /* Check to make sure we've got the right device. */
37 if (pci_read_config16(dev, 0x0) != 0x8086) {
38 die("SMBus controller not found!");
39 }
40
41 /* Set SMBus I/O base. */
42 pci_write_config32(dev, SMB_BASE,
43 SMBUS_IO_BASE | PCI_BASE_ADDRESS_SPACE_IO);
44
45 /* Set SMBus enable. */
46 pci_write_config8(dev, HOSTC, HST_EN);
47
48 /* Set SMBus I/O space enable. */
49 pci_write_config16(dev, PCI_COMMAND, PCI_COMMAND_IO);
50
51 /* Disable interrupt generation. */
52 outb(0, SMBUS_IO_BASE + SMBHSTCTL);
53
54 /* Clear any lingering errors, so transactions can run. */
55 outb(inb(SMBUS_IO_BASE + SMBHSTSTAT), SMBUS_IO_BASE + SMBHSTSTAT);
56 printk(BIOS_DEBUG,"SMBus controller enabled.\n");
57}
58
59int smbus_read_byte(unsigned device, unsigned address)
60{
61 return do_smbus_read_byte(SMBUS_IO_BASE, device, address);
62}
63