| Marc Jones | 5a4554a | 2015-09-15 12:44:37 -0600 | [diff] [blame] | 1 | /* |
| 2 | * This file is part of the coreboot project. |
| 3 | * |
| 4 | * Copyright (C) 2011 Google Inc. |
| 5 | * |
| 6 | * This program is free software; you can redistribute it and/or modify |
| 7 | * it under the terms of the GNU General Public License as published by |
| 8 | * the Free Software Foundation; version 2 of the License. |
| 9 | * |
| 10 | * This program is distributed in the hope that it will be useful, |
| 11 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 12 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 13 | * GNU General Public License for more details. |
| 14 | * |
| 15 | * You should have received a copy of the GNU General Public License |
| 16 | * along with this program; if not, write to the Free Software |
| 17 | * Foundation, Inc. |
| 18 | */ |
| 19 | |
| 20 | #include <arch/io.h> |
| 21 | #include <cpu/x86/tsc.h> |
| 22 | #include "pch.h" |
| 23 | |
| 24 | /* |
| 25 | * Enable Prefetching and Caching. |
| 26 | */ |
| 27 | static void enable_spi_prefetch(void) |
| 28 | { |
| 29 | u8 reg8; |
| 30 | pci_devfn_t dev; |
| 31 | |
| 32 | dev = PCI_DEV(0, 0x1f, 0); |
| 33 | |
| 34 | reg8 = pci_read_config8(dev, 0xdc); |
| 35 | reg8 &= ~(3 << 2); |
| 36 | reg8 |= (2 << 2); /* Prefetching and Caching Enabled */ |
| 37 | pci_write_config8(dev, 0xdc, reg8); |
| 38 | } |
| 39 | |
| 40 | static void enable_port80_on_lpc(void) |
| 41 | { |
| 42 | pci_devfn_t dev = PCI_DEV(0, 0x1f, 0); |
| 43 | |
| 44 | /* Enable port 80 POST on LPC */ |
| 45 | pci_write_config32(dev, RCBA, (uintptr_t)DEFAULT_RCBA | 1); |
| 46 | volatile u32 *gcs = (volatile u32 *)(DEFAULT_RCBA + GCS); |
| 47 | u32 reg32 = *gcs; |
| 48 | reg32 = reg32 & ~0x04; |
| 49 | *gcs = reg32; |
| 50 | } |
| 51 | |
| 52 | static void set_spi_speed(void) |
| 53 | { |
| 54 | u32 fdod; |
| 55 | u8 ssfc; |
| 56 | |
| 57 | /* Observe SPI Descriptor Component Section 0 */ |
| 58 | RCBA32(0x38b0) = 0x1000; |
| 59 | |
| 60 | /* Extract the Write/Erase SPI Frequency from descriptor */ |
| 61 | fdod = RCBA32(0x38b4); |
| 62 | fdod >>= 24; |
| 63 | fdod &= 7; |
| 64 | |
| 65 | /* Set Software Sequence frequency to match */ |
| 66 | ssfc = RCBA8(0x3893); |
| 67 | ssfc &= ~7; |
| 68 | ssfc |= fdod; |
| 69 | RCBA8(0x3893) = ssfc; |
| 70 | } |
| 71 | |
| 72 | static void bootblock_southbridge_init(void) |
| 73 | { |
| 74 | enable_spi_prefetch(); |
| 75 | enable_port80_on_lpc(); |
| 76 | set_spi_speed(); |
| 77 | |
| 78 | /* Enable upper 128bytes of CMOS */ |
| 79 | RCBA32(RC) = (1 << 2); |
| 80 | } |