Martin Roth | bf6b83a | 2015-10-11 10:37:02 +0200 | [diff] [blame] | 1 | /* |
| 2 | * This file is part of the coreboot project. |
| 3 | * |
| 4 | * Copyright (C) 2008-2009 coresystems GmbH |
| 5 | * Copyright (C) 2012 The Chromium OS Authors. All rights reserved. |
| 6 | * |
| 7 | * This program is free software; you can redistribute it and/or |
| 8 | * modify it under the terms of the GNU General Public License as |
| 9 | * published by the Free Software Foundation; version 2 of |
| 10 | * the License. |
| 11 | * |
| 12 | * This program is distributed in the hope that it will be useful, |
| 13 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 14 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 15 | * GNU General Public License for more details. |
Martin Roth | bf6b83a | 2015-10-11 10:37:02 +0200 | [diff] [blame] | 16 | */ |
| 17 | |
| 18 | #include <console/console.h> |
| 19 | #include <delay.h> |
| 20 | #include <device/device.h> |
| 21 | #include <device/pci.h> |
| 22 | #include "pch.h" |
| 23 | |
| 24 | static int pch_revision_id = -1; |
| 25 | static int pch_type = -1; |
| 26 | |
| 27 | int pch_silicon_revision(void) |
| 28 | { |
| 29 | if (pch_revision_id < 0) |
| 30 | pch_revision_id = pci_read_config8( |
| 31 | dev_find_slot(0, PCI_DEVFN(0x1f, 0)), |
| 32 | PCI_REVISION_ID); |
| 33 | return pch_revision_id; |
| 34 | } |
| 35 | |
| 36 | int pch_silicon_type(void) |
| 37 | { |
| 38 | if (pch_type < 0) |
| 39 | pch_type = pci_read_config8( |
| 40 | dev_find_slot(0, PCI_DEVFN(0x1f, 0)), |
| 41 | PCI_DEVICE_ID + 1); |
| 42 | return pch_type; |
| 43 | } |
| 44 | |
| 45 | int pch_silicon_supported(int type, int rev) |
| 46 | { |
| 47 | int cur_type = pch_silicon_type(); |
| 48 | int cur_rev = pch_silicon_revision(); |
| 49 | |
| 50 | switch (type) { |
| 51 | case PCH_TYPE_CPT: |
| 52 | /* CougarPoint minimum revision */ |
| 53 | if (cur_type == PCH_TYPE_CPT && cur_rev >= rev) |
| 54 | return 1; |
| 55 | /* PantherPoint any revision */ |
| 56 | if (cur_type == PCH_TYPE_PPT) |
| 57 | return 1; |
| 58 | break; |
| 59 | |
| 60 | case PCH_TYPE_PPT: |
| 61 | /* PantherPoint minimum revision */ |
| 62 | if (cur_type == PCH_TYPE_PPT && cur_rev >= rev) |
| 63 | return 1; |
| 64 | break; |
| 65 | } |
| 66 | |
| 67 | return 0; |
| 68 | } |
| 69 | |
| 70 | /* Set bit in Function Disble register to hide this device */ |
| 71 | static void pch_hide_devfn(unsigned devfn) |
| 72 | { |
| 73 | switch (devfn) { |
| 74 | case PCI_DEVFN(22, 0): /* MEI #1 */ |
| 75 | RCBA32_OR(FD2, PCH_DISABLE_MEI1); |
| 76 | break; |
| 77 | case PCI_DEVFN(22, 1): /* MEI #2 */ |
| 78 | RCBA32_OR(FD2, PCH_DISABLE_MEI2); |
| 79 | break; |
| 80 | case PCI_DEVFN(22, 2): /* IDE-R */ |
| 81 | RCBA32_OR(FD2, PCH_DISABLE_IDER); |
| 82 | break; |
| 83 | case PCI_DEVFN(22, 3): /* KT */ |
| 84 | RCBA32_OR(FD2, PCH_DISABLE_KT); |
| 85 | break; |
| 86 | case PCI_DEVFN(25, 0): /* Gigabit Ethernet */ |
| 87 | RCBA32_OR(BUC, PCH_DISABLE_GBE); |
| 88 | break; |
| 89 | case PCI_DEVFN(26, 0): /* EHCI #2 */ |
| 90 | RCBA32_OR(FD, PCH_DISABLE_EHCI2); |
| 91 | break; |
| 92 | case PCI_DEVFN(27, 0): /* HD Audio Controller */ |
| 93 | RCBA32_OR(FD, PCH_DISABLE_HD_AUDIO); |
| 94 | break; |
| 95 | case PCI_DEVFN(28, 0): /* PCI Express Root Port 1 */ |
| 96 | case PCI_DEVFN(28, 1): /* PCI Express Root Port 2 */ |
| 97 | case PCI_DEVFN(28, 2): /* PCI Express Root Port 3 */ |
| 98 | case PCI_DEVFN(28, 3): /* PCI Express Root Port 4 */ |
| 99 | case PCI_DEVFN(28, 4): /* PCI Express Root Port 5 */ |
| 100 | case PCI_DEVFN(28, 5): /* PCI Express Root Port 6 */ |
| 101 | case PCI_DEVFN(28, 6): /* PCI Express Root Port 7 */ |
| 102 | case PCI_DEVFN(28, 7): /* PCI Express Root Port 8 */ |
| 103 | RCBA32_OR(FD, PCH_DISABLE_PCIE(PCI_FUNC(devfn))); |
| 104 | break; |
| 105 | case PCI_DEVFN(29, 0): /* EHCI #1 */ |
| 106 | RCBA32_OR(FD, PCH_DISABLE_EHCI1); |
| 107 | break; |
| 108 | case PCI_DEVFN(30, 0): /* PCI-to-PCI Bridge */ |
| 109 | RCBA32_OR(FD, PCH_DISABLE_P2P); |
| 110 | break; |
| 111 | case PCI_DEVFN(31, 0): /* LPC */ |
| 112 | RCBA32_OR(FD, PCH_DISABLE_LPC); |
| 113 | break; |
| 114 | case PCI_DEVFN(31, 2): /* SATA #1 */ |
| 115 | RCBA32_OR(FD, PCH_DISABLE_SATA1); |
| 116 | break; |
| 117 | case PCI_DEVFN(31, 3): /* SMBUS */ |
| 118 | RCBA32_OR(FD, PCH_DISABLE_SMBUS); |
| 119 | break; |
| 120 | case PCI_DEVFN(31, 5): /* SATA #22 */ |
| 121 | RCBA32_OR(FD, PCH_DISABLE_SATA2); |
| 122 | break; |
| 123 | case PCI_DEVFN(31, 6): /* Thermal Subsystem */ |
| 124 | RCBA32_OR(FD, PCH_DISABLE_THERMAL); |
| 125 | break; |
| 126 | } |
| 127 | } |
| 128 | |
| 129 | #define IOBP_RETRY 1000 |
| 130 | static inline int iobp_poll(void) |
| 131 | { |
| 132 | unsigned try = IOBP_RETRY; |
| 133 | u32 data; |
| 134 | |
| 135 | while (try--) { |
| 136 | data = RCBA32(IOBPS); |
| 137 | if ((data & 1) == 0) |
| 138 | return 1; |
| 139 | udelay(10); |
| 140 | } |
| 141 | |
| 142 | printk(BIOS_ERR, "IOBP timeout\n"); |
| 143 | return 0; |
| 144 | } |
| 145 | |
| 146 | void pch_iobp_update(u32 address, u32 andvalue, u32 orvalue) |
| 147 | { |
| 148 | u32 data; |
| 149 | |
| 150 | /* Set the address */ |
| 151 | RCBA32(IOBPIRI) = address; |
| 152 | |
| 153 | /* READ OPCODE */ |
| 154 | if (pch_silicon_supported(PCH_TYPE_CPT, PCH_STEP_B0)) |
| 155 | RCBA32(IOBPS) = IOBPS_RW_BX; |
| 156 | else |
| 157 | RCBA32(IOBPS) = IOBPS_READ_AX; |
| 158 | if (!iobp_poll()) |
| 159 | return; |
| 160 | |
| 161 | /* Read IOBP data */ |
| 162 | data = RCBA32(IOBPD); |
| 163 | if (!iobp_poll()) |
| 164 | return; |
| 165 | |
| 166 | /* Check for successful transaction */ |
| 167 | if ((RCBA32(IOBPS) & 0x6) != 0) { |
| 168 | printk(BIOS_ERR, "IOBP read 0x%08x failed\n", address); |
| 169 | return; |
| 170 | } |
| 171 | |
| 172 | /* Update the data */ |
| 173 | data &= andvalue; |
| 174 | data |= orvalue; |
| 175 | |
| 176 | /* WRITE OPCODE */ |
| 177 | if (pch_silicon_supported(PCH_TYPE_CPT, PCH_STEP_B0)) |
| 178 | RCBA32(IOBPS) = IOBPS_RW_BX; |
| 179 | else |
| 180 | RCBA32(IOBPS) = IOBPS_WRITE_AX; |
| 181 | if (!iobp_poll()) |
| 182 | return; |
| 183 | |
| 184 | /* Write IOBP data */ |
| 185 | RCBA32(IOBPD) = data; |
| 186 | if (!iobp_poll()) |
| 187 | return; |
| 188 | } |
| 189 | |
| 190 | /* Check if any port in set X to X+3 is enabled */ |
| 191 | static int pch_pcie_check_set_enabled(device_t dev) |
| 192 | { |
| 193 | device_t port; |
| 194 | int port_func; |
| 195 | int dev_func = PCI_FUNC(dev->path.pci.devfn); |
| 196 | |
| 197 | printk(BIOS_DEBUG, "%s: check set enabled\n", dev_path(dev)); |
| 198 | |
| 199 | /* Go through static device tree list of devices |
| 200 | * because enumeration is still in progress */ |
| 201 | for (port = all_devices; port; port = port->next) { |
| 202 | /* Only care about PCIe root ports */ |
| 203 | if (PCI_SLOT(port->path.pci.devfn) != |
| 204 | PCI_SLOT(dev->path.pci.devfn)) |
| 205 | continue; |
| 206 | |
| 207 | /* Check if port is in range and enabled */ |
| 208 | port_func = PCI_FUNC(port->path.pci.devfn); |
| 209 | if (port_func >= dev_func && |
| 210 | port_func < (dev_func + 4) && |
| 211 | port->enabled) |
| 212 | return 1; |
| 213 | } |
| 214 | |
| 215 | /* None of the ports in this set are enabled */ |
| 216 | return 0; |
| 217 | } |
| 218 | |
| 219 | /* RPFN is a write-once register so keep a copy until it is written */ |
| 220 | static u32 new_rpfn; |
| 221 | |
| 222 | /* Swap function numbers assigned to two PCIe Root Ports */ |
| 223 | static void pch_pcie_function_swap(u8 old_fn, u8 new_fn) |
| 224 | { |
| 225 | u32 old_rpfn = new_rpfn; |
| 226 | |
| 227 | printk(BIOS_DEBUG, "PCH: Remap PCIe function %d to %d\n", |
| 228 | old_fn, new_fn); |
| 229 | |
| 230 | new_rpfn &= ~(RPFN_FNMASK(old_fn) | RPFN_FNMASK(new_fn)); |
| 231 | |
| 232 | /* Old function set to new function and disabled */ |
| 233 | new_rpfn |= RPFN_FNSET(old_fn, RPFN_FNGET(old_rpfn, new_fn)); |
| 234 | new_rpfn |= RPFN_FNSET(new_fn, RPFN_FNGET(old_rpfn, old_fn)); |
| 235 | } |
| 236 | |
| 237 | /* Update devicetree with new Root Port function number assignment */ |
| 238 | static void pch_pcie_devicetree_update(void) |
| 239 | { |
| 240 | device_t dev; |
| 241 | |
| 242 | /* Update the function numbers in the static devicetree */ |
| 243 | for (dev = all_devices; dev; dev = dev->next) { |
| 244 | u8 new_devfn; |
| 245 | |
| 246 | /* Only care about PCH PCIe root ports */ |
| 247 | if (PCI_SLOT(dev->path.pci.devfn) != |
| 248 | PCH_PCIE_DEV_SLOT) |
| 249 | continue; |
| 250 | |
| 251 | /* Determine the new devfn for this port */ |
| 252 | new_devfn = PCI_DEVFN(PCH_PCIE_DEV_SLOT, |
| 253 | RPFN_FNGET(new_rpfn, |
| 254 | PCI_FUNC(dev->path.pci.devfn))); |
| 255 | |
| 256 | if (dev->path.pci.devfn != new_devfn) { |
| 257 | printk(BIOS_DEBUG, |
| 258 | "PCH: PCIe map %02x.%1x -> %02x.%1x\n", |
| 259 | PCI_SLOT(dev->path.pci.devfn), |
| 260 | PCI_FUNC(dev->path.pci.devfn), |
| 261 | PCI_SLOT(new_devfn), PCI_FUNC(new_devfn)); |
| 262 | |
| 263 | dev->path.pci.devfn = new_devfn; |
| 264 | } |
| 265 | } |
| 266 | } |
| 267 | |
| 268 | /* Special handling for PCIe Root Port devices */ |
| 269 | static void pch_pcie_enable(device_t dev) |
| 270 | { |
| 271 | struct southbridge_intel_fsp_bd82x6x_config *config = dev->chip_info; |
| 272 | u32 reg32; |
| 273 | |
| 274 | /* |
| 275 | * Save a copy of the Root Port Function Number map when |
| 276 | * starting to walk the list of PCIe Root Ports so it can |
| 277 | * be updated locally and written out when the last port |
| 278 | * has been processed. |
| 279 | */ |
| 280 | if (PCI_FUNC(dev->path.pci.devfn) == 0) { |
| 281 | new_rpfn = RCBA32(RPFN); |
| 282 | |
| 283 | /* |
| 284 | * Enable Root Port coalescing if the first port is disabled |
| 285 | * or the other devices will not be enumerated by the OS. |
| 286 | */ |
| 287 | if (!dev->enabled) |
| 288 | config->pcie_port_coalesce = 1; |
| 289 | |
| 290 | if (config->pcie_port_coalesce) |
| 291 | printk(BIOS_INFO, |
| 292 | "PCH: PCIe Root Port coalescing is enabled\n"); |
| 293 | } |
| 294 | |
| 295 | if (!dev->enabled) { |
| 296 | printk(BIOS_DEBUG, "%s: Disabling device\n", dev_path(dev)); |
| 297 | |
| 298 | /* |
| 299 | * PCIE Power Savings for PantherPoint and CougarPoint/B1+ |
| 300 | * |
| 301 | * If PCIe 0-3 disabled set Function 0 0xE2[0] = 1 |
| 302 | * If PCIe 4-7 disabled set Function 4 0xE2[0] = 1 |
| 303 | * |
| 304 | * This check is done here instead of pcie driver |
| 305 | * because the pcie driver enable() handler is not |
| 306 | * called unless the device is enabled. |
| 307 | */ |
| 308 | if ((PCI_FUNC(dev->path.pci.devfn) == 0 || |
| 309 | PCI_FUNC(dev->path.pci.devfn) == 4)) { |
| 310 | /* Handle workaround for PPT and CPT/B1+ */ |
| 311 | if (pch_silicon_supported(PCH_TYPE_CPT, PCH_STEP_B1) && |
| 312 | !pch_pcie_check_set_enabled(dev)) { |
| 313 | u8 reg8 = pci_read_config8(dev, 0xe2); |
| 314 | reg8 |= 1; |
| 315 | pci_write_config8(dev, 0xe2, reg8); |
| 316 | } |
| 317 | |
| 318 | /* |
| 319 | * Enable Clock Gating for shared PCIe resources |
| 320 | * before disabling this particular port. |
| 321 | */ |
| 322 | pci_write_config8(dev, 0xe1, 0x3c); |
| 323 | } |
| 324 | |
| 325 | /* Ensure memory, io, and bus master are all disabled */ |
| 326 | reg32 = pci_read_config32(dev, PCI_COMMAND); |
| 327 | reg32 &= ~(PCI_COMMAND_MASTER | |
| 328 | PCI_COMMAND_MEMORY | PCI_COMMAND_IO); |
| 329 | pci_write_config32(dev, PCI_COMMAND, reg32); |
| 330 | |
| 331 | /* Do not claim downstream transactions for PCIe ports */ |
| 332 | new_rpfn |= RPFN_HIDE(PCI_FUNC(dev->path.pci.devfn)); |
| 333 | |
| 334 | /* Hide this device if possible */ |
| 335 | pch_hide_devfn(dev->path.pci.devfn); |
| 336 | } else { |
| 337 | int fn; |
| 338 | |
| 339 | /* |
| 340 | * Check if there is a lower disabled port to swap with this |
| 341 | * port in order to maintain linear order starting at zero. |
| 342 | */ |
| 343 | if (config->pcie_port_coalesce) { |
| 344 | for (fn=0; fn < PCI_FUNC(dev->path.pci.devfn); fn++) { |
| 345 | if (!(new_rpfn & RPFN_HIDE(fn))) |
| 346 | continue; |
| 347 | |
| 348 | /* Swap places with this function */ |
| 349 | pch_pcie_function_swap( |
| 350 | PCI_FUNC(dev->path.pci.devfn), fn); |
| 351 | break; |
| 352 | } |
| 353 | } |
| 354 | |
| 355 | /* Enable SERR */ |
| 356 | reg32 = pci_read_config32(dev, PCI_COMMAND); |
| 357 | reg32 |= PCI_COMMAND_SERR; |
| 358 | pci_write_config32(dev, PCI_COMMAND, reg32); |
| 359 | } |
| 360 | |
| 361 | /* |
| 362 | * When processing the last PCIe root port we can now |
| 363 | * update the Root Port Function Number and Hide register. |
| 364 | */ |
| 365 | if (PCI_FUNC(dev->path.pci.devfn) == 7) { |
| 366 | printk(BIOS_SPEW, "PCH: RPFN 0x%08x -> 0x%08x\n", |
| 367 | RCBA32(RPFN), new_rpfn); |
| 368 | RCBA32(RPFN) = new_rpfn; |
| 369 | |
| 370 | /* Update static devictree with new function numbers */ |
| 371 | if (config->pcie_port_coalesce) |
| 372 | pch_pcie_devicetree_update(); |
| 373 | } |
| 374 | } |
| 375 | |
| 376 | void pch_enable(device_t dev) |
| 377 | { |
| 378 | u32 reg32; |
| 379 | |
| 380 | /* PCH PCIe Root Ports get special handling */ |
| 381 | if (PCI_SLOT(dev->path.pci.devfn) == PCH_PCIE_DEV_SLOT) |
| 382 | return pch_pcie_enable(dev); |
| 383 | |
| 384 | if (!dev->enabled) { |
| 385 | printk(BIOS_DEBUG, "%s: Disabling device\n", dev_path(dev)); |
| 386 | |
| 387 | /* Ensure memory, io, and bus master are all disabled */ |
| 388 | reg32 = pci_read_config32(dev, PCI_COMMAND); |
| 389 | reg32 &= ~(PCI_COMMAND_MASTER | |
| 390 | PCI_COMMAND_MEMORY | PCI_COMMAND_IO); |
| 391 | pci_write_config32(dev, PCI_COMMAND, reg32); |
| 392 | |
| 393 | /* Hide this device if possible */ |
| 394 | pch_hide_devfn(dev->path.pci.devfn); |
| 395 | } else { |
| 396 | /* Enable SERR */ |
| 397 | reg32 = pci_read_config32(dev, PCI_COMMAND); |
| 398 | reg32 |= PCI_COMMAND_SERR; |
| 399 | pci_write_config32(dev, PCI_COMMAND, reg32); |
| 400 | } |
| 401 | } |
| 402 | |
| 403 | struct chip_operations southbridge_intel_fsp_bd82x6x_ops = { |
| 404 | CHIP_NAME("Intel Series 6/7 (Cougar Point/Panther Point) Southbridge") |
| 405 | .enable_dev = pch_enable, |
| 406 | }; |