Martin Roth | bf6b83a | 2015-10-11 10:37:02 +0200 | [diff] [blame] | 1 | /* |
| 2 | * This file is part of the coreboot project. |
| 3 | * |
| 4 | * Copyright (C) 2011 The Chromium OS Authors. All rights reserved. |
| 5 | * |
| 6 | * This program is free software; you can redistribute it and/or |
| 7 | * modify it under the terms of the GNU General Public License as |
| 8 | * published by the Free Software Foundation; version 2 of |
| 9 | * the License. |
| 10 | * |
| 11 | * This program is distributed in the hope that it will be useful, |
| 12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 14 | * GNU General Public License for more details. |
Martin Roth | bf6b83a | 2015-10-11 10:37:02 +0200 | [diff] [blame] | 15 | */ |
| 16 | |
| 17 | #include <stdlib.h> |
| 18 | #include <console/console.h> |
| 19 | #include "me.h" |
| 20 | |
| 21 | #if (CONFIG_DEFAULT_CONSOLE_LOGLEVEL >= BIOS_DEBUG) |
| 22 | /* HFS1[3:0] Current Working State Values */ |
| 23 | static const char *me_cws_values[] = { |
| 24 | [ME_HFS_CWS_RESET] = "Reset", |
| 25 | [ME_HFS_CWS_INIT] = "Initializing", |
| 26 | [ME_HFS_CWS_REC] = "Recovery", |
| 27 | [ME_HFS_CWS_NORMAL] = "Normal", |
| 28 | [ME_HFS_CWS_WAIT] = "Platform Disable Wait", |
| 29 | [ME_HFS_CWS_TRANS] = "OP State Transition", |
| 30 | [ME_HFS_CWS_INVALID] = "Invalid CPU Plugged In" |
| 31 | }; |
| 32 | |
| 33 | /* HFS1[8:6] Current Operation State Values */ |
| 34 | static const char *me_opstate_values[] = { |
| 35 | [ME_HFS_STATE_PREBOOT] = "Preboot", |
| 36 | [ME_HFS_STATE_M0_UMA] = "M0 with UMA", |
| 37 | [ME_HFS_STATE_M3] = "M3 without UMA", |
| 38 | [ME_HFS_STATE_M0] = "M0 without UMA", |
| 39 | [ME_HFS_STATE_BRINGUP] = "Bring up", |
| 40 | [ME_HFS_STATE_ERROR] = "M0 without UMA but with error" |
| 41 | }; |
| 42 | |
| 43 | /* HFS[19:16] Current Operation Mode Values */ |
| 44 | static const char *me_opmode_values[] = { |
| 45 | [ME_HFS_MODE_NORMAL] = "Normal", |
| 46 | [ME_HFS_MODE_DEBUG] = "Debug", |
| 47 | [ME_HFS_MODE_DIS] = "Soft Temporary Disable", |
| 48 | [ME_HFS_MODE_OVER_JMPR] = "Security Override via Jumper", |
| 49 | [ME_HFS_MODE_OVER_MEI] = "Security Override via MEI Message" |
| 50 | }; |
| 51 | |
| 52 | /* HFS[15:12] Error Code Values */ |
| 53 | static const char *me_error_values[] = { |
| 54 | [ME_HFS_ERROR_NONE] = "No Error", |
| 55 | [ME_HFS_ERROR_UNCAT] = "Uncategorized Failure", |
| 56 | [ME_HFS_ERROR_IMAGE] = "Image Failure", |
| 57 | [ME_HFS_ERROR_DEBUG] = "Debug Failure" |
| 58 | }; |
| 59 | |
| 60 | /* GMES[31:28] ME Progress Code */ |
| 61 | static const char *me_progress_values[] = { |
| 62 | [ME_GMES_PHASE_ROM] = "ROM Phase", |
| 63 | [ME_GMES_PHASE_BUP] = "BUP Phase", |
| 64 | [ME_GMES_PHASE_UKERNEL] = "uKernel Phase", |
| 65 | [ME_GMES_PHASE_POLICY] = "Policy Module", |
| 66 | [ME_GMES_PHASE_MODULE] = "Module Loading", |
| 67 | [ME_GMES_PHASE_UNKNOWN] = "Unknown", |
| 68 | [ME_GMES_PHASE_HOST] = "Host Communication" |
| 69 | }; |
| 70 | |
| 71 | /* GMES[27:24] Power Management Event */ |
| 72 | static const char *me_pmevent_values[] = { |
| 73 | [0x00] = "Clean Moff->Mx wake", |
| 74 | [0x01] = "Moff->Mx wake after an error", |
| 75 | [0x02] = "Clean global reset", |
| 76 | [0x03] = "Global reset after an error", |
| 77 | [0x04] = "Clean Intel ME reset", |
| 78 | [0x05] = "Intel ME reset due to exception", |
| 79 | [0x06] = "Pseudo-global reset", |
| 80 | [0x07] = "S0/M0->Sx/M3", |
| 81 | [0x08] = "Sx/M3->S0/M0", |
| 82 | [0x09] = "Non-power cycle reset", |
| 83 | [0x0a] = "Power cycle reset through M3", |
| 84 | [0x0b] = "Power cycle reset through Moff", |
| 85 | [0x0c] = "Sx/Mx->Sx/Moff" |
| 86 | }; |
| 87 | |
| 88 | /* Progress Code 0 states */ |
| 89 | static const char *me_progress_rom_values[] = { |
| 90 | [0x00] = "BEGIN", |
| 91 | [0x06] = "DISABLE" |
| 92 | }; |
| 93 | |
| 94 | /* Progress Code 1 states */ |
| 95 | static const char *me_progress_bup_values[] = { |
| 96 | [0x00] = "Initialization starts", |
| 97 | [0x01] = "Disable the host wake event", |
| 98 | [0x04] = "Flow determination start process", |
| 99 | [0x08] = "Error reading/matching the VSCC table in the descriptor", |
| 100 | [0x0a] = "Check to see if straps say ME DISABLED", |
| 101 | [0x0b] = "Timeout waiting for PWROK", |
| 102 | [0x0d] = "Possibly handle BUP manufacturing override strap", |
| 103 | [0x11] = "Bringup in M3", |
| 104 | [0x12] = "Bringup in M0", |
| 105 | [0x13] = "Flow detection error", |
| 106 | [0x15] = "M3 clock switching error", |
| 107 | [0x18] = "M3 kernel load", |
| 108 | [0x1c] = "T34 missing - cannot program ICC", |
| 109 | [0x1f] = "Waiting for DID BIOS message", |
| 110 | [0x20] = "Waiting for DID BIOS message failure", |
| 111 | [0x21] = "DID reported an error", |
| 112 | [0x22] = "Enabling UMA", |
| 113 | [0x23] = "Enabling UMA error", |
| 114 | [0x24] = "Sending DID Ack to BIOS", |
| 115 | [0x25] = "Sending DID Ack to BIOS error", |
| 116 | [0x26] = "Switching clocks in M0", |
| 117 | [0x27] = "Switching clocks in M0 error", |
| 118 | [0x28] = "ME in temp disable", |
| 119 | [0x32] = "M0 kernel load", |
| 120 | }; |
| 121 | |
| 122 | /* Progress Code 3 states */ |
| 123 | static const char *me_progress_policy_values[] = { |
| 124 | [0x00] = "Entery into Policy Module", |
| 125 | [0x03] = "Received S3 entry", |
| 126 | [0x04] = "Received S4 entry", |
| 127 | [0x05] = "Received S5 entry", |
| 128 | [0x06] = "Received UPD entry", |
| 129 | [0x07] = "Received PCR entry", |
| 130 | [0x08] = "Received NPCR entry", |
| 131 | [0x09] = "Received host wake", |
| 132 | [0x0a] = "Received AC<>DC switch", |
| 133 | [0x0b] = "Received DRAM Init Done", |
| 134 | [0x0c] = "VSCC Data not found for flash device", |
| 135 | [0x0d] = "VSCC Table is not valid", |
| 136 | [0x0e] = "Flash Partition Boundary is outside address space", |
| 137 | [0x0f] = "ME cannot access the chipset descriptor region", |
| 138 | [0x10] = "Required VSCC values for flash parts do not match", |
| 139 | }; |
| 140 | #endif |
| 141 | |
| 142 | void intel_me_status(struct me_hfs *hfs, struct me_gmes *gmes) |
| 143 | { |
| 144 | #if (CONFIG_DEFAULT_CONSOLE_LOGLEVEL >= BIOS_DEBUG) |
| 145 | /* Check Current States */ |
| 146 | printk(BIOS_DEBUG, "ME: FW Partition Table : %s\n", |
| 147 | hfs->fpt_bad ? "BAD" : "OK"); |
| 148 | printk(BIOS_DEBUG, "ME: Bringup Loader Failure : %s\n", |
| 149 | hfs->ft_bup_ld_flr ? "YES" : "NO"); |
| 150 | printk(BIOS_DEBUG, "ME: Firmware Init Complete : %s\n", |
| 151 | hfs->fw_init_complete ? "YES" : "NO"); |
| 152 | printk(BIOS_DEBUG, "ME: Manufacturing Mode : %s\n", |
| 153 | hfs->mfg_mode ? "YES" : "NO"); |
| 154 | printk(BIOS_DEBUG, "ME: Boot Options Present : %s\n", |
| 155 | hfs->boot_options_present ? "YES" : "NO"); |
| 156 | printk(BIOS_DEBUG, "ME: Update In Progress : %s\n", |
| 157 | hfs->update_in_progress ? "YES" : "NO"); |
| 158 | printk(BIOS_DEBUG, "ME: Current Working State : %s\n", |
| 159 | me_cws_values[hfs->working_state]); |
| 160 | printk(BIOS_DEBUG, "ME: Current Operation State : %s\n", |
| 161 | me_opstate_values[hfs->operation_state]); |
| 162 | printk(BIOS_DEBUG, "ME: Current Operation Mode : %s\n", |
| 163 | me_opmode_values[hfs->operation_mode]); |
| 164 | printk(BIOS_DEBUG, "ME: Error Code : %s\n", |
| 165 | me_error_values[hfs->error_code]); |
| 166 | printk(BIOS_DEBUG, "ME: Progress Phase : %s\n", |
| 167 | me_progress_values[gmes->progress_code]); |
| 168 | printk(BIOS_DEBUG, "ME: Power Management Event : %s\n", |
| 169 | me_pmevent_values[gmes->current_pmevent]); |
| 170 | |
| 171 | printk(BIOS_DEBUG, "ME: Progress Phase State : "); |
| 172 | switch (gmes->progress_code) { |
| 173 | case ME_GMES_PHASE_ROM: /* ROM Phase */ |
| 174 | printk(BIOS_DEBUG, "%s", |
| 175 | me_progress_rom_values[gmes->current_state]); |
| 176 | break; |
| 177 | |
| 178 | case ME_GMES_PHASE_BUP: /* Bringup Phase */ |
| 179 | if (gmes->current_state < ARRAY_SIZE(me_progress_bup_values) |
| 180 | && me_progress_bup_values[gmes->current_state]) |
| 181 | printk(BIOS_DEBUG, "%s", |
| 182 | me_progress_bup_values[gmes->current_state]); |
| 183 | else |
| 184 | printk(BIOS_DEBUG, "0x%02x", gmes->current_state); |
| 185 | break; |
| 186 | |
| 187 | case ME_GMES_PHASE_POLICY: /* Policy Module Phase */ |
| 188 | if (gmes->current_state < ARRAY_SIZE(me_progress_policy_values) |
| 189 | && me_progress_policy_values[gmes->current_state]) |
| 190 | printk(BIOS_DEBUG, "%s", |
| 191 | me_progress_policy_values[gmes->current_state]); |
| 192 | else |
| 193 | printk(BIOS_DEBUG, "0x%02x", gmes->current_state); |
| 194 | break; |
| 195 | |
| 196 | case ME_GMES_PHASE_HOST: /* Host Communication Phase */ |
| 197 | if (!gmes->current_state) |
| 198 | printk(BIOS_DEBUG, "Host communication established"); |
| 199 | else |
| 200 | printk(BIOS_DEBUG, "0x%02x", gmes->current_state); |
| 201 | break; |
| 202 | |
| 203 | default: |
| 204 | printk(BIOS_DEBUG, "Unknown 0x%02x", gmes->current_state); |
| 205 | } |
| 206 | printk(BIOS_DEBUG, "\n"); |
| 207 | #endif |
| 208 | } |