Martin Roth | bf6b83a | 2015-10-11 10:37:02 +0200 | [diff] [blame] | 1 | /* |
| 2 | * This file is part of the coreboot project. |
| 3 | * |
| 4 | * Copyright (C) 2011 The Chromium OS Authors. All rights reserved. |
| 5 | * |
| 6 | * This program is free software; you can redistribute it and/or |
| 7 | * modify it under the terms of the GNU General Public License as |
| 8 | * published by the Free Software Foundation; version 2 of |
| 9 | * the License. |
| 10 | * |
| 11 | * This program is distributed in the hope that it will be useful, |
| 12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 14 | * GNU General Public License for more details. |
Martin Roth | bf6b83a | 2015-10-11 10:37:02 +0200 | [diff] [blame] | 15 | */ |
| 16 | |
| 17 | #ifndef _INTEL_ME_H |
| 18 | #define _INTEL_ME_H |
| 19 | |
| 20 | #define ME_RETRY 100000 /* 1 second */ |
| 21 | #define ME_DELAY 10 /* 10 us */ |
| 22 | |
| 23 | /* |
| 24 | * Management Engine PCI registers |
| 25 | */ |
| 26 | |
| 27 | #define PCI_CPU_DEVICE PCI_DEV(0,0,0) |
| 28 | #define PCI_CPU_MEBASE_L 0x70 /* Set by MRC */ |
| 29 | #define PCI_CPU_MEBASE_H 0x74 /* Set by MRC */ |
| 30 | |
| 31 | #define PCI_ME_HFS 0x40 |
| 32 | #define ME_HFS_CWS_RESET 0 |
| 33 | #define ME_HFS_CWS_INIT 1 |
| 34 | #define ME_HFS_CWS_REC 2 |
| 35 | #define ME_HFS_CWS_NORMAL 5 |
| 36 | #define ME_HFS_CWS_WAIT 6 |
| 37 | #define ME_HFS_CWS_TRANS 7 |
| 38 | #define ME_HFS_CWS_INVALID 8 |
| 39 | #define ME_HFS_STATE_PREBOOT 0 |
| 40 | #define ME_HFS_STATE_M0_UMA 1 |
| 41 | #define ME_HFS_STATE_M3 4 |
| 42 | #define ME_HFS_STATE_M0 5 |
| 43 | #define ME_HFS_STATE_BRINGUP 6 |
| 44 | #define ME_HFS_STATE_ERROR 7 |
| 45 | #define ME_HFS_ERROR_NONE 0 |
| 46 | #define ME_HFS_ERROR_UNCAT 1 |
| 47 | #define ME_HFS_ERROR_IMAGE 3 |
| 48 | #define ME_HFS_ERROR_DEBUG 4 |
| 49 | #define ME_HFS_MODE_NORMAL 0 |
| 50 | #define ME_HFS_MODE_DEBUG 2 |
| 51 | #define ME_HFS_MODE_DIS 3 |
| 52 | #define ME_HFS_MODE_OVER_JMPR 4 |
| 53 | #define ME_HFS_MODE_OVER_MEI 5 |
| 54 | #define ME_HFS_BIOS_DRAM_ACK 1 |
| 55 | #define ME_HFS_ACK_NO_DID 0 |
| 56 | #define ME_HFS_ACK_RESET 1 |
| 57 | #define ME_HFS_ACK_PWR_CYCLE 2 |
| 58 | #define ME_HFS_ACK_S3 3 |
| 59 | #define ME_HFS_ACK_S4 4 |
| 60 | #define ME_HFS_ACK_S5 5 |
| 61 | #define ME_HFS_ACK_GBL_RESET 6 |
| 62 | #define ME_HFS_ACK_CONTINUE 7 |
| 63 | |
| 64 | struct me_hfs { |
| 65 | u32 working_state: 4; |
| 66 | u32 mfg_mode: 1; |
| 67 | u32 fpt_bad: 1; |
| 68 | u32 operation_state: 3; |
| 69 | u32 fw_init_complete: 1; |
| 70 | u32 ft_bup_ld_flr: 1; |
| 71 | u32 update_in_progress: 1; |
| 72 | u32 error_code: 4; |
| 73 | u32 operation_mode: 4; |
| 74 | u32 reserved: 4; |
| 75 | u32 boot_options_present: 1; |
| 76 | u32 ack_data: 3; |
| 77 | u32 bios_msg_ack: 4; |
| 78 | } __attribute__ ((packed)); |
| 79 | |
| 80 | #define PCI_ME_UMA 0x44 |
| 81 | |
| 82 | struct me_uma { |
| 83 | u32 size: 6; |
| 84 | u32 reserved_1: 10; |
| 85 | u32 valid: 1; |
| 86 | u32 reserved_0: 14; |
| 87 | u32 set_to_one: 1; |
| 88 | } __attribute__ ((packed)); |
| 89 | |
| 90 | #define PCI_ME_H_GS 0x4c |
| 91 | #define ME_INIT_DONE 1 |
| 92 | #define ME_INIT_STATUS_SUCCESS 0 |
| 93 | #define ME_INIT_STATUS_NOMEM 1 |
| 94 | #define ME_INIT_STATUS_ERROR 2 |
| 95 | |
| 96 | struct me_did { |
| 97 | u32 uma_base: 16; |
| 98 | u32 reserved: 8; |
| 99 | u32 status: 4; |
| 100 | u32 init_done: 4; |
| 101 | } __attribute__ ((packed)); |
| 102 | |
| 103 | #define PCI_ME_GMES 0x48 |
| 104 | #define ME_GMES_PHASE_ROM 0 |
| 105 | #define ME_GMES_PHASE_BUP 1 |
| 106 | #define ME_GMES_PHASE_UKERNEL 2 |
| 107 | #define ME_GMES_PHASE_POLICY 3 |
| 108 | #define ME_GMES_PHASE_MODULE 4 |
| 109 | #define ME_GMES_PHASE_UNKNOWN 5 |
| 110 | #define ME_GMES_PHASE_HOST 6 |
| 111 | |
| 112 | struct me_gmes { |
| 113 | u32 bist_in_prog : 1; |
| 114 | u32 icc_prog_sts : 2; |
| 115 | u32 invoke_mebx : 1; |
| 116 | u32 cpu_replaced_sts : 1; |
| 117 | u32 mbp_rdy : 1; |
| 118 | u32 mfs_failure : 1; |
| 119 | u32 warm_rst_req_for_df : 1; |
| 120 | u32 cpu_replaced_valid : 1; |
| 121 | u32 reserved_1 : 2; |
| 122 | u32 fw_upd_ipu : 1; |
| 123 | u32 reserved_2 : 4; |
| 124 | u32 current_state: 8; |
| 125 | u32 current_pmevent: 4; |
| 126 | u32 progress_code: 4; |
| 127 | } __attribute__ ((packed)); |
| 128 | |
| 129 | #define PCI_ME_HERES 0xbc |
| 130 | #define PCI_ME_EXT_SHA1 0x00 |
| 131 | #define PCI_ME_EXT_SHA256 0x02 |
| 132 | #define PCI_ME_HER(x) (0xc0+(4*(x))) |
| 133 | |
| 134 | struct me_heres { |
| 135 | u32 extend_reg_algorithm: 4; |
| 136 | u32 reserved: 26; |
| 137 | u32 extend_feature_present: 1; |
| 138 | u32 extend_reg_valid: 1; |
| 139 | } __attribute__ ((packed)); |
| 140 | |
| 141 | /* |
| 142 | * Management Engine MEI registers |
| 143 | */ |
| 144 | |
| 145 | #define MEI_H_CB_WW 0x00 |
| 146 | #define MEI_H_CSR 0x04 |
| 147 | #define MEI_ME_CB_RW 0x08 |
| 148 | #define MEI_ME_CSR_HA 0x0c |
| 149 | |
| 150 | struct mei_csr { |
| 151 | u32 interrupt_enable: 1; |
| 152 | u32 interrupt_status: 1; |
| 153 | u32 interrupt_generate: 1; |
| 154 | u32 ready: 1; |
| 155 | u32 reset: 1; |
| 156 | u32 reserved: 3; |
| 157 | u32 buffer_read_ptr: 8; |
| 158 | u32 buffer_write_ptr: 8; |
| 159 | u32 buffer_depth: 8; |
| 160 | } __attribute__ ((packed)); |
| 161 | |
| 162 | #define MEI_ADDRESS_CORE 0x01 |
| 163 | #define MEI_ADDRESS_AMT 0x02 |
| 164 | #define MEI_ADDRESS_RESERVED 0x03 |
| 165 | #define MEI_ADDRESS_WDT 0x04 |
| 166 | #define MEI_ADDRESS_MKHI 0x07 |
| 167 | #define MEI_ADDRESS_ICC 0x08 |
| 168 | #define MEI_ADDRESS_THERMAL 0x09 |
| 169 | |
| 170 | #define MEI_HOST_ADDRESS 0 |
| 171 | |
| 172 | struct mei_header { |
| 173 | u32 client_address: 8; |
| 174 | u32 host_address: 8; |
| 175 | u32 length: 9; |
| 176 | u32 reserved: 6; |
| 177 | u32 is_complete: 1; |
| 178 | } __attribute__ ((packed)); |
| 179 | |
| 180 | #define MKHI_GROUP_ID_CBM 0x00 |
| 181 | #define MKHI_GROUP_ID_FWCAPS 0x03 |
| 182 | #define MKHI_GROUP_ID_MDES 0x08 |
| 183 | #define MKHI_GROUP_ID_GEN 0xff |
| 184 | |
| 185 | #define MKHI_GLOBAL_RESET 0x0b |
| 186 | |
| 187 | #define MKHI_FWCAPS_GET_RULE 0x02 |
| 188 | |
| 189 | #define MKHI_MDES_ENABLE 0x09 |
| 190 | |
| 191 | #define MKHI_GET_FW_VERSION 0x02 |
| 192 | #define MKHI_END_OF_POST 0x0c |
| 193 | #define MKHI_FEATURE_OVERRIDE 0x14 |
| 194 | |
| 195 | struct mkhi_header { |
| 196 | u32 group_id: 8; |
| 197 | u32 command: 7; |
| 198 | u32 is_response: 1; |
| 199 | u32 reserved: 8; |
| 200 | u32 result: 8; |
| 201 | } __attribute__ ((packed)); |
| 202 | |
| 203 | struct me_fw_version { |
| 204 | u16 code_minor; |
| 205 | u16 code_major; |
| 206 | u16 code_build_number; |
| 207 | u16 code_hot_fix; |
| 208 | u16 recovery_minor; |
| 209 | u16 recovery_major; |
| 210 | u16 recovery_build_number; |
| 211 | u16 recovery_hot_fix; |
| 212 | } __attribute__ ((packed)); |
| 213 | |
| 214 | |
| 215 | #define HECI_EOP_STATUS_SUCCESS 0x0 |
| 216 | #define HECI_EOP_PERFORM_GLOBAL_RESET 0x1 |
| 217 | |
| 218 | #define CBM_RR_GLOBAL_RESET 0x01 |
| 219 | |
| 220 | #define GLOBAL_RESET_BIOS_MRC 0x01 |
| 221 | #define GLOBAL_RESET_BIOS_POST 0x02 |
| 222 | #define GLOBAL_RESET_MEBX 0x03 |
| 223 | |
| 224 | struct me_global_reset { |
| 225 | u8 request_origin; |
| 226 | u8 reset_type; |
| 227 | } __attribute__ ((packed)); |
| 228 | |
| 229 | typedef enum { |
| 230 | ME_NORMAL_BIOS_PATH, |
| 231 | ME_S3WAKE_BIOS_PATH, |
| 232 | ME_ERROR_BIOS_PATH, |
| 233 | ME_RECOVERY_BIOS_PATH, |
| 234 | ME_DISABLE_BIOS_PATH, |
| 235 | ME_FIRMWARE_UPDATE_BIOS_PATH, |
| 236 | } me_bios_path; |
| 237 | |
| 238 | /* Defined in me_status.c for both romstage and ramstage */ |
| 239 | void intel_me_status(struct me_hfs *hfs, struct me_gmes *gmes); |
| 240 | |
| 241 | #ifdef __PRE_RAM__ |
| 242 | void intel_early_me_status(void); |
| 243 | int intel_early_me_init(void); |
| 244 | int intel_early_me_uma_size(void); |
| 245 | int intel_early_me_init_done(u8 status); |
| 246 | #endif |
| 247 | |
| 248 | #ifdef __SMM__ |
| 249 | void intel_me_finalize_smm(void); |
| 250 | void intel_me8_finalize_smm(void); |
| 251 | #endif |
| 252 | typedef struct { |
| 253 | u32 major_version : 16; |
| 254 | u32 minor_version : 16; |
| 255 | u32 hotfix_version : 16; |
| 256 | u32 build_version : 16; |
| 257 | } __attribute__ ((packed)) mbp_fw_version_name; |
| 258 | |
| 259 | typedef struct { |
| 260 | u8 num_icc_profiles; |
| 261 | u8 icc_profile_soft_strap; |
| 262 | u8 icc_profile_index; |
| 263 | u8 reserved; |
| 264 | u32 register_lock_mask[3]; |
| 265 | } __attribute__ ((packed)) mbp_icc_profile; |
| 266 | |
| 267 | typedef struct { |
| 268 | u32 full_net : 1; |
| 269 | u32 std_net : 1; |
| 270 | u32 manageability : 1; |
| 271 | u32 small_business : 1; |
| 272 | u32 l3manageability : 1; |
| 273 | u32 intel_at : 1; |
| 274 | u32 intel_cls : 1; |
| 275 | u32 reserved : 3; |
| 276 | u32 intel_mpc : 1; |
| 277 | u32 icc_over_clocking : 1; |
| 278 | u32 pavp : 1; |
| 279 | u32 reserved_1 : 4; |
| 280 | u32 ipv6 : 1; |
| 281 | u32 kvm : 1; |
| 282 | u32 och : 1; |
| 283 | u32 vlan : 1; |
| 284 | u32 tls : 1; |
| 285 | u32 reserved_4 : 1; |
| 286 | u32 wlan : 1; |
| 287 | u32 reserved_5 : 8; |
| 288 | } __attribute__ ((packed)) mefwcaps_sku; |
| 289 | |
| 290 | typedef struct { |
| 291 | u16 lock_state : 1; |
| 292 | u16 authenticate_module : 1; |
| 293 | u16 s3authentication : 1; |
| 294 | u16 flash_wear_out : 1; |
| 295 | u16 flash_variable_security : 1; |
| 296 | u16 wwan3gpresent : 1; |
| 297 | u16 wwan3goob : 1; |
| 298 | u16 reserved : 9; |
| 299 | } __attribute__ ((packed)) tdt_state_flag; |
| 300 | |
| 301 | typedef struct { |
| 302 | u8 state; |
| 303 | u8 last_theft_trigger; |
| 304 | tdt_state_flag flags; |
| 305 | } __attribute__ ((packed)) tdt_state_info; |
| 306 | |
| 307 | typedef struct { |
| 308 | u32 platform_target_usage_type : 4; |
| 309 | u32 platform_target_market_type : 2; |
| 310 | u32 super_sku : 1; |
| 311 | u32 reserved : 1; |
| 312 | u32 intel_me_fw_image_type : 4; |
| 313 | u32 platform_brand : 4; |
| 314 | u32 reserved_1 : 16; |
| 315 | } __attribute__ ((packed)) platform_type_rule_data; |
| 316 | |
| 317 | typedef struct { |
| 318 | mefwcaps_sku fw_capabilities; |
| 319 | u8 available; |
| 320 | } mbp_fw_caps; |
| 321 | |
| 322 | typedef struct { |
| 323 | u16 device_id; |
| 324 | u16 fuse_test_flags; |
| 325 | u32 umchid[4]; |
| 326 | } __attribute__ ((packed)) mbp_rom_bist_data; |
| 327 | |
| 328 | typedef struct { |
| 329 | u32 key[8]; |
| 330 | } mbp_platform_key; |
| 331 | |
| 332 | typedef struct { |
| 333 | platform_type_rule_data rule_data; |
| 334 | u8 available; |
| 335 | } mbp_plat_type; |
| 336 | |
| 337 | typedef struct { |
| 338 | mbp_fw_version_name fw_version_name; |
| 339 | mbp_fw_caps fw_caps_sku; |
| 340 | mbp_rom_bist_data rom_bist_data; |
| 341 | mbp_platform_key platform_key; |
| 342 | mbp_plat_type fw_plat_type; |
| 343 | mbp_icc_profile icc_profile; |
| 344 | tdt_state_info at_state; |
| 345 | u32 mfsintegrity; |
| 346 | } me_bios_payload; |
| 347 | |
| 348 | typedef struct { |
| 349 | u32 mbp_size : 8; |
| 350 | u32 num_entries : 8; |
| 351 | u32 rsvd : 16; |
| 352 | } __attribute__ ((packed)) mbp_header; |
| 353 | |
| 354 | typedef struct { |
| 355 | u32 app_id : 8; |
| 356 | u32 item_id : 8; |
| 357 | u32 length : 8; |
| 358 | u32 rsvd : 8; |
| 359 | } __attribute__ ((packed)) mbp_item_header; |
| 360 | |
| 361 | struct me_fwcaps { |
| 362 | u32 id; |
| 363 | u8 length; |
| 364 | mefwcaps_sku caps_sku; |
| 365 | u8 reserved[3]; |
| 366 | } __attribute__ ((packed)); |
| 367 | |
| 368 | #endif /* _INTEL_ME_H */ |