Martin Roth | bf6b83a | 2015-10-11 10:37:02 +0200 | [diff] [blame] | 1 | /* |
| 2 | * This file is part of the coreboot project. |
| 3 | * |
| 4 | * Copyright (C) 2012 The ChromiumOS Authors. All rights reserved. |
| 5 | * |
| 6 | * This program is free software; you can redistribute it and/or modify |
| 7 | * it under the terms of the GNU General Public License as published by |
| 8 | * the Free Software Foundation; version 2 of the License. |
| 9 | * |
| 10 | * This program is distributed in the hope that it will be useful, |
| 11 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 12 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 13 | * GNU General Public License for more details. |
Martin Roth | bf6b83a | 2015-10-11 10:37:02 +0200 | [diff] [blame] | 14 | */ |
| 15 | |
| 16 | #include <arch/io.h> |
| 17 | #include <arch/acpi.h> |
| 18 | #include <console/console.h> |
| 19 | #include <device/device.h> |
| 20 | #include <device/pci.h> |
| 21 | #include <device/pci_ops.h> |
| 22 | #include <stdint.h> |
| 23 | #include <string.h> |
| 24 | #include <elog.h> |
| 25 | #include "pch.h" |
| 26 | |
| 27 | void pch_log_state(void) |
| 28 | { |
| 29 | u16 pm1_sts, gen_pmcon_3, tco2_sts; |
| 30 | u32 gpe0_sts, gpe0_en; |
| 31 | u8 gen_pmcon_2; |
| 32 | int i; |
| 33 | struct device *lpc = dev_find_slot(0, PCI_DEVFN(0x1f, 0)); |
| 34 | if (!lpc) |
| 35 | return; |
| 36 | |
| 37 | pm1_sts = inw(DEFAULT_PMBASE + PM1_STS); |
| 38 | gpe0_sts = inl(DEFAULT_PMBASE + GPE0_STS); |
| 39 | gpe0_en = inl(DEFAULT_PMBASE + GPE0_EN); |
| 40 | tco2_sts = inw(DEFAULT_PMBASE + TCO2_STS); |
| 41 | gen_pmcon_2 = pci_read_config8(lpc, GEN_PMCON_2); |
| 42 | gen_pmcon_3 = pci_read_config16(lpc, GEN_PMCON_3); |
| 43 | |
| 44 | /* PWR_FLR Power Failure */ |
| 45 | if (gen_pmcon_2 & (1 << 0)) |
| 46 | elog_add_event(ELOG_TYPE_POWER_FAIL); |
| 47 | |
| 48 | /* SUS Well Power Failure */ |
| 49 | if (gen_pmcon_3 & (1 << 14)) |
| 50 | elog_add_event(ELOG_TYPE_SUS_POWER_FAIL); |
| 51 | |
| 52 | /* SYS_PWROK Failure */ |
| 53 | if (gen_pmcon_2 & (1 << 1)) |
| 54 | elog_add_event(ELOG_TYPE_SYS_PWROK_FAIL); |
| 55 | |
| 56 | /* PWROK Failure */ |
| 57 | if (gen_pmcon_2 & (1 << 0)) |
| 58 | elog_add_event(ELOG_TYPE_PWROK_FAIL); |
| 59 | |
| 60 | /* Second TCO Timeout */ |
| 61 | if (tco2_sts & (1 << 1)) |
| 62 | elog_add_event(ELOG_TYPE_TCO_RESET); |
| 63 | |
| 64 | /* Power Button Override */ |
| 65 | if (pm1_sts & (1 << 11)) |
| 66 | elog_add_event(ELOG_TYPE_POWER_BUTTON_OVERRIDE); |
| 67 | |
| 68 | /* System Reset Status (reset button pushed) */ |
| 69 | if (gen_pmcon_2 & (1 << 4)) |
| 70 | elog_add_event(ELOG_TYPE_RESET_BUTTON); |
| 71 | |
| 72 | /* General Reset Status */ |
| 73 | if (gen_pmcon_3 & (1 << 9)) |
| 74 | elog_add_event(ELOG_TYPE_SYSTEM_RESET); |
| 75 | |
| 76 | /* ACPI Wake */ |
| 77 | if (pm1_sts & (1 << 15)) |
| 78 | elog_add_event_byte(ELOG_TYPE_ACPI_WAKE, |
| 79 | acpi_is_wakeup_s3() ? 3 : 5); |
| 80 | |
| 81 | /* |
| 82 | * Wake sources |
| 83 | */ |
| 84 | |
| 85 | /* RTC */ |
| 86 | if (pm1_sts & (1 << 10)) |
| 87 | elog_add_event_wake(ELOG_WAKE_SOURCE_RTC, 0); |
| 88 | |
| 89 | /* PCI Express (TODO: determine wake device) */ |
| 90 | if (pm1_sts & (1 << 14)) |
| 91 | elog_add_event_wake(ELOG_WAKE_SOURCE_PCIE, 0); |
| 92 | |
| 93 | /* PME (TODO: determine wake device) */ |
| 94 | if (gpe0_sts & (1 << 13)) |
| 95 | elog_add_event_wake(ELOG_WAKE_SOURCE_PME, 0); |
| 96 | |
| 97 | /* Internal PME (TODO: determine wake device) */ |
| 98 | if (gpe0_sts & (1 << 13)) |
| 99 | elog_add_event_wake(ELOG_WAKE_SOURCE_PME_INTERNAL, 0); |
| 100 | |
| 101 | /* GPIO 0-15 */ |
| 102 | for (i = 0; i < 16; i++) { |
| 103 | if ((gpe0_sts & (1 << (16+i))) && (gpe0_en & (1 << (16+i)))) |
| 104 | elog_add_event_wake(ELOG_WAKE_SOURCE_GPIO, i); |
| 105 | } |
| 106 | |
| 107 | /* SMBUS Wake */ |
| 108 | if (gpe0_sts & (1 << 7)) |
| 109 | elog_add_event_wake(ELOG_WAKE_SOURCE_SMBUS, 0); |
| 110 | } |