Martin Roth | bf6b83a | 2015-10-11 10:37:02 +0200 | [diff] [blame] | 1 | /* |
| 2 | * This file is part of the coreboot project. |
| 3 | * |
| 4 | * Copyright (C) 2007-2010 coresystems GmbH |
| 5 | * Copyright (C) 2011 Google Inc |
| 6 | * |
| 7 | * This program is free software; you can redistribute it and/or modify |
| 8 | * it under the terms of the GNU General Public License as published by |
| 9 | * the Free Software Foundation; version 2 of the License. |
| 10 | * |
| 11 | * This program is distributed in the hope that it will be useful, |
| 12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 14 | * GNU General Public License for more details. |
Martin Roth | bf6b83a | 2015-10-11 10:37:02 +0200 | [diff] [blame] | 15 | */ |
| 16 | |
| 17 | #include <stdint.h> |
| 18 | #include <stdlib.h> |
| 19 | #include <console/console.h> |
| 20 | #include <arch/io.h> |
| 21 | #include <device/pci_def.h> |
| 22 | #include <elog.h> |
| 23 | #include "pch.h" |
| 24 | |
| 25 | #define FD_ENTRIES 32 |
| 26 | #define FD2_ENTRIES 5 |
| 27 | |
| 28 | const static char *fd_set_strings[FD_ENTRIES] = { |
| 29 | "", |
| 30 | "PCI Bridge (D30:F0) Disabled\n", |
| 31 | "SATA 1(D31:F2) Disabled\n", |
| 32 | "SMBus Config space Disabled\n", |
| 33 | "High Definition Audio Disabled\n", |
| 34 | "Reserved bit 5 set\n", |
| 35 | "Reserved bit 6 set\n", |
| 36 | "Reserved bit 7 set\n", |
| 37 | "Reserved bit 8 set\n", |
| 38 | "Reserved bit 9 set\n", |
| 39 | "Reserved bit 10 set\n", |
| 40 | "Reserved bit 11 set\n", |
| 41 | "Reserved bit 12 set\n", |
| 42 | "EHCI #2 Disabled\n", |
| 43 | "LPC Bridge Disabled\n", |
| 44 | "EHCI #1 Disabled\n", |
| 45 | "PCIe bridge 1 Disabled\n", |
| 46 | "PCIe bridge 2 Disabled\n", |
| 47 | "PCIe bridge 3 Disabled\n", |
| 48 | "PCIe bridge 4 Disabled\n", |
| 49 | "PCIe bridge 5 Disabled\n", |
| 50 | "PCIe bridge 6 Disabled\n", |
| 51 | "PCIe bridge 7 Disabled\n", |
| 52 | "PCIe bridge 8 Disabled\n", |
| 53 | "Thermal Sensor (D31:F6) Registers Disabled\n", |
| 54 | "SATA 2 (D31:F5) Disabled\n", |
| 55 | "Reserved bit 26 set\n", |
| 56 | "Reserved bit 27 set\n", |
| 57 | "Reserved bit 28 set\n", |
| 58 | "Reserved bit 29 set\n", |
| 59 | "Reserved bit 30 set\n", |
| 60 | "Reserved bit 31 set\n", |
| 61 | }; |
| 62 | |
| 63 | const static char *fd_notset_strings[FD_ENTRIES] = { |
| 64 | "ERROR: Required field NOT programmed\n", |
| 65 | "PCI Bridge (D30:F0) enabled\n", |
| 66 | "SATA 1(D31:F2) enabled\n", |
| 67 | "SMBus Config space enabled\n", |
| 68 | "High Definition Audio enabled\n", |
| 69 | "", |
| 70 | "", |
| 71 | "", |
| 72 | "", |
| 73 | "", |
| 74 | "", |
| 75 | "", |
| 76 | "", |
| 77 | "EHCI #2 Enabled\n", |
| 78 | "LPC Bridge Enabled\n", |
| 79 | "EHCI #1 Enabled\n", |
| 80 | "PCIe bridge 1 Enabled\n", |
| 81 | "PCIe bridge 2 Enabled\n", |
| 82 | "PCIe bridge 3 Enabled\n", |
| 83 | "PCIe bridge 4 Enabled\n", |
| 84 | "PCIe bridge 5 Enabled\n", |
| 85 | "PCIe bridge 6 Enabled\n", |
| 86 | "PCIe bridge 7 Enabled\n", |
| 87 | "PCIe bridge 8 Enabled\n", |
| 88 | "Thermal Sensor (D31:F6) Registers Enabled\n", |
| 89 | "SATA 2 (D31:F5) Enabled\n", |
| 90 | "", |
| 91 | "", |
| 92 | "", |
| 93 | "", |
| 94 | "", |
| 95 | "", |
| 96 | }; |
| 97 | |
| 98 | const static char *fd2_set_strings[FD2_ENTRIES] = { |
| 99 | "Display BDF Enabled\n", |
| 100 | "MEI #1 (D22:F0) Disabled\n", |
| 101 | "MEI #2 (D22:F1) Disabled\n", |
| 102 | "IDE-R (D22:F2) Disabled\n", |
| 103 | "KT (D22:F3) Disabled\n" |
| 104 | }; |
| 105 | |
| 106 | const static char *fd2_notset_strings[FD2_ENTRIES] = { |
| 107 | "Display BDF Disabled\n", |
| 108 | "MEI #1 (D22:F0) Enabled\n", |
| 109 | "MEI #2 (D22:F1) Enabled\n", |
| 110 | "IDE-R (D22:F2) Enabled\n", |
| 111 | "KT (D22:F3) Enabled\n" |
| 112 | }; |
| 113 | |
| 114 | void display_fd_settings(void) |
| 115 | { |
| 116 | u32 reg32; |
| 117 | int i; |
| 118 | |
| 119 | reg32 = RCBA32(FD); |
| 120 | for (i = 0; i < FD_ENTRIES; i++) { |
| 121 | if (reg32 & (1 << i)) { |
| 122 | printk(BIOS_SPEW, "%s", fd_set_strings[i]); |
| 123 | } else { |
| 124 | printk(BIOS_SPEW, "%s", fd_notset_strings[i]); |
| 125 | } |
| 126 | } |
| 127 | |
| 128 | reg32 = RCBA32(FD2); |
| 129 | for (i = 0; i < FD2_ENTRIES; i++) { |
| 130 | if (reg32 & (1 << i)) { |
| 131 | printk(BIOS_SPEW, "%s", fd2_set_strings[i]); |
| 132 | } else { |
| 133 | printk(BIOS_SPEW, "%s", fd2_notset_strings[i]); |
| 134 | } |
| 135 | } |
| 136 | } |
| 137 | |
| 138 | static void sandybridge_setup_bars(void) |
| 139 | { |
| 140 | /* Setting up Southbridge. */ |
| 141 | printk(BIOS_DEBUG, "Setting up static southbridge registers..."); |
| 142 | pci_write_config32(PCI_DEV(0, 0x1f, 0), RCBA, (uintptr_t)DEFAULT_RCBA | 1); |
| 143 | |
| 144 | pci_write_config32(PCI_DEV(0, 0x1f, 0), PMBASE, DEFAULT_PMBASE | 1); |
| 145 | pci_write_config8(PCI_DEV(0, 0x1f, 0), 0x44 /* ACPI_CNTL */ , 0x80); /* Enable ACPI BAR */ |
| 146 | |
| 147 | printk(BIOS_DEBUG, " done.\n"); |
| 148 | |
| 149 | printk(BIOS_DEBUG, "Disabling Watchdog reboot..."); |
| 150 | RCBA32(GCS) = RCBA32(GCS) | (1 << 5); /* No reset */ |
| 151 | outw((1 << 11), DEFAULT_PMBASE | 0x60 | 0x08); /* halt timer */ |
| 152 | printk(BIOS_DEBUG, " done.\n"); |
| 153 | |
| 154 | #if CONFIG_ELOG_BOOT_COUNT |
| 155 | /* Increment Boot Counter for non-S3 resume */ |
| 156 | if ((inw(DEFAULT_PMBASE + PM1_STS) & WAK_STS) && |
| 157 | ((inl(DEFAULT_PMBASE + PM1_CNT) >> 10) & 7) != SLP_TYP_S3) |
| 158 | boot_count_increment(); |
| 159 | #endif |
| 160 | |
| 161 | printk(BIOS_DEBUG, " done.\n"); |
| 162 | |
| 163 | #if CONFIG_ELOG_BOOT_COUNT |
| 164 | /* Increment Boot Counter except when resuming from S3 */ |
| 165 | if ((inw(DEFAULT_PMBASE + PM1_STS) & WAK_STS) && |
| 166 | ((inl(DEFAULT_PMBASE + PM1_CNT) >> 10) & 7) == SLP_TYP_S3) |
| 167 | return; |
| 168 | boot_count_increment(); |
| 169 | #endif |
| 170 | } |
| 171 | |
| 172 | void sandybridge_sb_early_initialization(void) |
| 173 | { |
| 174 | /* Setup all BARs required for early PCIe and raminit */ |
| 175 | sandybridge_setup_bars(); |
| 176 | } |
| 177 | |
| 178 | void early_pch_init(void) |
| 179 | { |
| 180 | u8 reg8; |
| 181 | |
| 182 | // reset rtc power status |
| 183 | reg8 = pci_read_config8(PCH_LPC_DEV, 0xa4); |
| 184 | reg8 &= ~(1 << 2); |
| 185 | pci_write_config8(PCH_LPC_DEV, 0xa4, reg8); |
| 186 | } |