| Vladimir Serbinenko | 33b535f | 2014-10-19 10:13:14 +0200 | [diff] [blame] | 1 | /* |
| 2 | * This file is part of the coreboot project. |
| 3 | * |
| 4 | * Copyright (C) 2007-2010 coresystems GmbH |
| 5 | * Copyright (C) 2011 The ChromiumOS Authors. All rights reserved. |
| 6 | * Copyright (C) 2014 Vladimir Serbinenko |
| 7 | * |
| 8 | * This program is free software; you can redistribute it and/or modify |
| 9 | * it under the terms of the GNU General Public License as published by |
| 10 | * the Free Software Foundation; version 2 of the License. |
| 11 | * |
| 12 | * This program is distributed in the hope that it will be useful, |
| 13 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 14 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 15 | * GNU General Public License for more details. |
| Vladimir Serbinenko | 33b535f | 2014-10-19 10:13:14 +0200 | [diff] [blame] | 16 | */ |
| 17 | |
| 18 | #include <stdint.h> |
| 19 | #include "pch.h" |
| 20 | #include "northbridge/intel/sandybridge/sandybridge.h" |
| 21 | |
| 22 | void |
| 23 | southbridge_configure_default_intmap(void) |
| 24 | { |
| 25 | /* |
| 26 | * GFX INTA -> PIRQA (MSI) |
| 27 | * D28IP_P1IP SLOT1 INTA -> PIRQB |
| 28 | * D28IP_P2IP SLOT2 INTB -> PIRQF |
| 29 | * D28IP_P3IP SLOT3 INTC -> PIRQD |
| 30 | * D28IP_P5IP SLOT5 INTC -> PIRQD |
| 31 | * D29IP_E1P EHCI1 INTA -> PIRQD |
| 32 | * D26IP_E2P EHCI2 INTA -> PIRQF |
| 33 | * D31IP_SIP SATA INTA -> PIRQB (MSI) |
| 34 | * D31IP_SMIP SMBUS INTB -> PIRQH |
| 35 | * D31IP_TTIP THRT INTC -> PIRQA |
| 36 | * D27IP_ZIP HDA INTA -> PIRQA (MSI) |
| 37 | * |
| 38 | |
| 39 | */ |
| 40 | |
| 41 | RCBA32(D31IP) = (INTC << D31IP_TTIP) | (NOINT << D31IP_SIP2) | |
| 42 | (INTB << D31IP_SMIP) | (INTA << D31IP_SIP); |
| 43 | RCBA32(D30IP) = (NOINT << D30IP_PIP); |
| 44 | RCBA32(D29IP) = (INTA << D29IP_E1P); |
| 45 | RCBA32(D28IP) = (INTA << D28IP_P1IP) | (INTB << D28IP_P2IP) | |
| 46 | (INTC << D28IP_P3IP) | (INTC << D28IP_P5IP); |
| 47 | RCBA32(D27IP) = (INTA << D27IP_ZIP); |
| 48 | RCBA32(D26IP) = (INTA << D26IP_E2P); |
| 49 | RCBA32(D25IP) = (NOINT << D25IP_LIP); |
| 50 | RCBA32(D22IP) = (NOINT << D22IP_MEI1IP); |
| 51 | |
| 52 | /* Device interrupt route registers */ |
| 53 | DIR_ROUTE(D31IR, PIRQB, PIRQH, PIRQA, PIRQC); |
| 54 | DIR_ROUTE(D29IR, PIRQD, PIRQE, PIRQF, PIRQG); |
| 55 | DIR_ROUTE(D28IR, PIRQB, PIRQF, PIRQD, PIRQE); |
| 56 | DIR_ROUTE(D27IR, PIRQA, PIRQH, PIRQA, PIRQB); |
| 57 | DIR_ROUTE(D26IR, PIRQF, PIRQE, PIRQG, PIRQH); |
| 58 | DIR_ROUTE(D25IR, PIRQA, PIRQB, PIRQC, PIRQD); |
| 59 | DIR_ROUTE(D22IR, PIRQA, PIRQB, PIRQC, PIRQD); |
| 60 | |
| 61 | /* Enable IOAPIC (generic) */ |
| 62 | RCBA16(OIC) = 0x0100; |
| 63 | /* PCH BWG says to read back the IOAPIC enable register */ |
| 64 | (void) RCBA16(OIC); |
| 65 | } |