Uwe Hermann | c6a1062 | 2010-10-17 19:30:58 +0000 | [diff] [blame] | 1 | /* |
| 2 | * This file is part of the coreboot project. |
| 3 | * |
| 4 | * Copyright (C) 2005 AMD |
| 5 | * Written by Yinghai Lu <yinghai.lu@amd.com> for AMD. |
| 6 | * |
| 7 | * This program is free software; you can redistribute it and/or modify |
| 8 | * it under the terms of the GNU General Public License as published by |
| 9 | * the Free Software Foundation; version 2 of the License. |
| 10 | * |
| 11 | * This program is distributed in the hope that it will be useful, |
| 12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 14 | * GNU General Public License for more details. |
Uwe Hermann | c6a1062 | 2010-10-17 19:30:58 +0000 | [diff] [blame] | 15 | */ |
| 16 | |
Uwe Hermann | 42b1c43 | 2010-12-09 18:09:14 +0000 | [diff] [blame] | 17 | #include <stdint.h> |
| 18 | #include <arch/io.h> |
Uwe Hermann | 42b1c43 | 2010-12-09 18:09:14 +0000 | [diff] [blame] | 19 | #include <device/pci_ids.h> |
| 20 | |
| 21 | /* Enable 4MB ROM access at 0xFFC00000 - 0xFFFFFFFF. */ |
| 22 | static void bcm5785_enable_rom(void) |
| 23 | { |
| 24 | u8 byte; |
Edward O'Callaghan | 9a817ef | 2014-10-26 10:12:15 +1100 | [diff] [blame] | 25 | pci_devfn_t dev; |
Uwe Hermann | 42b1c43 | 2010-12-09 18:09:14 +0000 | [diff] [blame] | 26 | |
| 27 | dev = pci_locate_device(PCI_ID(PCI_VENDOR_ID_SERVERWORKS, |
| 28 | PCI_DEVICE_ID_SERVERWORKS_BCM5785_SB_PCI_MAIN), 0); |
| 29 | |
| 30 | /* Set the 4MB enable bits. */ |
| 31 | byte = pci_read_config8(dev, 0x41); |
| 32 | byte |= 0x0e; |
| 33 | pci_write_config8(dev, 0x41, byte); |
| 34 | } |
Patrick Georgi | 78c733c | 2010-05-22 15:07:15 +0000 | [diff] [blame] | 35 | |
Uwe Hermann | 39124dd | 2010-11-26 22:42:41 +0000 | [diff] [blame] | 36 | static void bootblock_southbridge_init(void) |
| 37 | { |
| 38 | bcm5785_enable_rom(); |
Patrick Georgi | 78c733c | 2010-05-22 15:07:15 +0000 | [diff] [blame] | 39 | } |