Zheng Bao | d098575 | 2011-01-20 04:45:48 +0000 | [diff] [blame] | 1 | /* |
| 2 | * This file is part of the coreboot project. |
| 3 | * |
| 4 | * Copyright (C) 2010 Advanced Micro Devices, Inc. |
| 5 | * |
| 6 | * This program is free software; you can redistribute it and/or modify |
| 7 | * it under the terms of the GNU General Public License as published by |
| 8 | * the Free Software Foundation; version 2 of the License. |
| 9 | * |
| 10 | * This program is distributed in the hope that it will be useful, |
| 11 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 12 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 13 | * GNU General Public License for more details. |
Zheng Bao | d098575 | 2011-01-20 04:45:48 +0000 | [diff] [blame] | 14 | */ |
| 15 | |
| 16 | #include <console/console.h> |
| 17 | #include <device/device.h> |
| 18 | #include <device/pci.h> |
| 19 | #include <device/pci_ids.h> |
| 20 | #include <device/pci_ops.h> |
| 21 | #include <device/smbus.h> |
| 22 | #include <pc80/mc146818rtc.h> |
Zheng Bao | d098575 | 2011-01-20 04:45:48 +0000 | [diff] [blame] | 23 | #include <arch/io.h> |
| 24 | #include <cpu/x86/lapic.h> |
| 25 | #include <arch/ioapic.h> |
| 26 | #include <stdlib.h> |
| 27 | #include "sb800.h" |
| 28 | #include "smbus.c" |
| 29 | |
| 30 | #define NMI_OFF 0 |
| 31 | |
| 32 | #define MAINBOARD_POWER_OFF 0 |
| 33 | #define MAINBOARD_POWER_ON 1 |
| 34 | |
| 35 | #ifndef CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL |
| 36 | #define CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL MAINBOARD_POWER_ON |
| 37 | #endif |
| 38 | |
| 39 | #define BIT0 (1 << 0) |
| 40 | #define BIT1 (1 << 1) |
| 41 | #define BIT2 (1 << 2) |
| 42 | #define BIT3 (1 << 3) |
| 43 | #define BIT4 (1 << 4) |
| 44 | #define BIT5 (1 << 5) |
| 45 | #define BIT6 (1 << 6) |
| 46 | #define BIT7 (1 << 7) |
| 47 | |
| 48 | #define BIT8 (1 << 8 ) |
| 49 | #define BIT9 (1 << 9 ) |
| 50 | #define BIT10 (1 << 10) |
| 51 | #define BIT11 (1 << 11) |
| 52 | #define BIT12 (1 << 12) |
| 53 | #define BIT13 (1 << 13) |
| 54 | #define BIT14 (1 << 14) |
| 55 | #define BIT15 (1 << 15) |
| 56 | |
| 57 | #define BIT16 (1 << 16) |
| 58 | #define BIT17 (1 << 17) |
| 59 | #define BIT18 (1 << 18) |
| 60 | #define BIT19 (1 << 19) |
| 61 | #define BIT20 (1 << 20) |
| 62 | #define BIT21 (1 << 21) |
| 63 | #define BIT22 (1 << 22) |
| 64 | #define BIT23 (1 << 23) |
| 65 | #define BIT24 (1 << 24) |
| 66 | #define BIT25 (1 << 25) |
| 67 | #define BIT26 (1 << 26) |
| 68 | #define BIT27 (1 << 27) |
| 69 | #define BIT28 (1 << 28) |
| 70 | #define BIT29 (1 << 29) |
| 71 | #define BIT30 (1 << 30) |
| 72 | #define BIT31 (1 << 31) |
| 73 | |
| 74 | /* |
| 75 | * SB800 enables all USB controllers by default in SMBUS Control. |
| 76 | * SB800 enables SATA by default in SMBUS Control. |
| 77 | */ |
| 78 | |
| 79 | static void sm_init(device_t dev) |
| 80 | { |
| 81 | u8 byte; |
Zheng Bao | d098575 | 2011-01-20 04:45:48 +0000 | [diff] [blame] | 82 | |
| 83 | printk(BIOS_INFO, "sm_init().\n"); |
| 84 | |
Zheng Bao | d098575 | 2011-01-20 04:45:48 +0000 | [diff] [blame] | 85 | /* Don't rename APIC ID */ |
| 86 | /* TODO: We should call setup_ioapic() here. But kernel hangs if cpu is K8. |
| 87 | * We need to check out why and change back. */ |
Kevin Paul Herbert | bde6d30 | 2014-12-24 18:43:20 -0800 | [diff] [blame] | 88 | clear_ioapic(VIO_APIC_VADDR); |
Patrick Georgi | 2c2e78d | 2012-02-16 18:54:37 +0100 | [diff] [blame] | 89 | //setup_ioapic(IO_APIC_ADDR, 0); |
Zheng Bao | d098575 | 2011-01-20 04:45:48 +0000 | [diff] [blame] | 90 | |
| 91 | /* enable serial irq */ |
| 92 | byte = pm_ioread(0x54); |
| 93 | byte |= 1 << 7; /* enable serial irq function */ |
| 94 | byte &= ~(0xF << 2); |
| 95 | byte |= 4 << 2; /* set NumSerIrqBits=4 */ |
| 96 | pm_iowrite(0x54, byte); |
| 97 | |
| 98 | pm_iowrite(0x00, 0x0E); |
| 99 | pm_iowrite(0x0B, 0x02); |
| 100 | /* 2.11 IO Trap Settings */ |
| 101 | abcfg_reg(0x10090, 1 << 16, 1 << 16); |
| 102 | |
| 103 | /* 4.1 ab index */ |
| 104 | //pci_write_config32(dev, 0xF0, AB_INDX); |
| 105 | pm_iowrite(0xE0, AB_INDX & 0xFF); |
| 106 | pm_iowrite(0xE1, (AB_INDX >> 8) & 0xFF); |
| 107 | pm_iowrite(0xE2, (AB_INDX >> 16) & 0xFF); |
| 108 | pm_iowrite(0xE3, (AB_INDX >> 24) & 0xFF); |
| 109 | /* Initialize the real time clock */ |
Gabe Black | b3f08c6 | 2014-04-30 17:12:25 -0700 | [diff] [blame] | 110 | cmos_init(0); |
Zheng Bao | d098575 | 2011-01-20 04:45:48 +0000 | [diff] [blame] | 111 | |
| 112 | byte = pm_ioread(0x8); |
| 113 | byte |= 1 << 2 | 1 << 4; |
| 114 | pm_iowrite(0x08, byte); |
| 115 | byte = pm_ioread(0x9); |
| 116 | byte |= 1 << 0; |
| 117 | pm_iowrite(0x09, byte); |
| 118 | |
| 119 | abcfg_reg(0x10060, (BIT31), BIT31); |
| 120 | abcfg_reg(0x1009C, (BIT4 + BIT5), BIT4 + BIT5); |
| 121 | abcfg_reg(0x9C, (BIT2 + BIT3 + BIT4 + BIT5 + BIT6 + BIT7), BIT2 + BIT3 + BIT4 + BIT5 + BIT6 + BIT7); |
| 122 | abcfg_reg(0x90, (BIT21 + BIT22 + BIT23), BIT21 + BIT22 + BIT23); |
| 123 | abcfg_reg(0xF0, (BIT6 + BIT5), BIT6 + BIT5); |
| 124 | abcfg_reg(0x10090, (BIT9 + BIT10 + BIT11 + BIT12), BIT9 + BIT10 + BIT11 + BIT12); |
| 125 | abcfg_reg(0x58, (BIT10), BIT10); |
| 126 | abcfg_reg(0xF0, (BIT3 + BIT4), BIT3 + BIT4); |
| 127 | abcfg_reg(0x54, (BIT1), BIT1); |
| 128 | // |
| 129 | axindxc_reg(0x02, BIT9, BIT9); |
| 130 | axindxc_reg(0x10, BIT9, BIT9); |
| 131 | |
| 132 | /* 4.2 Enabling Upstream DMA Access */ |
| 133 | axcfg_reg(0x04, 1 << 2, 1 << 2); |
| 134 | /* 4.3 Enabling PCIB Prefetch Settings */ |
| 135 | abcfg_reg(0x10060, 1 << 20, 1 << 20); |
| 136 | abcfg_reg(0x10064, 1 << 20, 1 << 20); |
| 137 | |
| 138 | /* 4.4 Enabling OHCI Prefetch for Performance Enhancement, A12 */ |
| 139 | abcfg_reg(0x80, 1 << 0, 1<< 0); |
| 140 | |
| 141 | /* 4.5 B-Link Client's Credit Variable Settings for the Downstream Arbitration Equation */ |
| 142 | /* 4.6 Enabling Additional Address Bits Checking in Downstream */ |
| 143 | abcfg_reg(0x9c, 1 << 0, 1 << 0); |
| 144 | //abcfg_reg(0x9c, 3 << 0, 3 << 0); //A11 |
| 145 | |
| 146 | /* 4.7 Set B-Link Prefetch Mode */ |
| 147 | abcfg_reg(0x80, 3 << 17, 3 << 17); |
| 148 | |
| 149 | // RPR Enabled SMI ordering enhancement. ABCFG 0x90[21] |
| 150 | // RPR USB Delay A-Link Express L1 State. ABCFG 0x90[17] |
| 151 | abcfg_reg(0x90, 1 << 17 | 1 << 21, 1 << 17 | 1 << 21); |
| 152 | /* 4.8 Enabling Detection of Upstream Interrupts */ |
| 153 | abcfg_reg(0x94, 1 << 20 | 0x7FFFF, 1 << 20 | 0x00FEE); |
| 154 | |
| 155 | /* 4.9: Enabling Downstream Posted Transactions to Pass Non-Posted |
| 156 | * Transactions for the K8 Platform (for All Revisions) */ |
| 157 | abcfg_reg(0x10090, 1 << 8, 1 << 8); |
| 158 | |
| 159 | /* 4.10:Programming Cycle Delay for AB and BIF Clock Gating */ |
| 160 | /* 4.11:Enabling AB Int_Arbiter Enhancement (for All Revisions) */ |
| 161 | abcfg_reg(0x10054, 0xFFFF0000, 0x01040000); |
| 162 | abcfg_reg(0x54, 0xFF << 16, 4 << 16); |
| 163 | abcfg_reg(0x54, 1 << 24, 0 << 24); |
| 164 | abcfg_reg(0x54, 1 << 26, 1 << 26); |
| 165 | abcfg_reg(0x98, 0xFFFFFF00, 0x00004700); |
| 166 | |
| 167 | /* 4.12: Enabling AB and BIF Clock Gating */ |
| 168 | abcfg_reg(0x10054, 0x0000FFFF, 0x07FF); |
| 169 | |
| 170 | /* 4.13:Enabling Requester ID for upstream traffic. */ |
| 171 | abcfg_reg(0x98, 3 << 16, 3 << 16); |
| 172 | |
| 173 | abcfg_reg(0x50, 1 << 2, 0 << 2); |
| 174 | |
| 175 | /* 5.2 Enabling GPP Port A/B/C/D */ |
| 176 | //abcfg_reg(0xC0, 0xF << 4, 0xF << 4); |
| 177 | |
| 178 | /* Enable SCI as irq9. */ |
| 179 | outb(0x10, 0xC00); |
| 180 | outb(0x9, 0xC01); |
| 181 | /* Enabled IRQ input */ |
| 182 | outb(0x9, 0xC00); |
| 183 | outb(0xF7, 0xC01); |
| 184 | |
| 185 | abcfg_reg(0x90, 0xFFFFFFFF, 0x00F80040); |
| 186 | abcfg_reg(0xA0, 0xFFFFFFFF, 0x00000000); |
| 187 | abcfg_reg(0xA4, 0xFFFFFFFF, 0x00000000); |
| 188 | abcfg_reg(0xC0, 0xFFFFFFFF, 0x0000F014); |
| 189 | abcfg_reg(0x98, 0xFFFFFFFF, 0X01034700); |
| 190 | } |
| 191 | |
| 192 | static int lsmbus_recv_byte(device_t dev) |
| 193 | { |
| 194 | u32 device; |
| 195 | struct resource *res; |
| 196 | struct bus *pbus; |
| 197 | |
| 198 | device = dev->path.i2c.device; |
| 199 | pbus = get_pbus_smbus(dev); |
| 200 | |
| 201 | res = find_resource(pbus->dev, 0x90); |
| 202 | |
| 203 | return do_smbus_recv_byte(res->base, device); |
| 204 | } |
| 205 | |
| 206 | static int lsmbus_send_byte(device_t dev, u8 val) |
| 207 | { |
| 208 | u32 device; |
| 209 | struct resource *res; |
| 210 | struct bus *pbus; |
| 211 | |
| 212 | device = dev->path.i2c.device; |
| 213 | pbus = get_pbus_smbus(dev); |
| 214 | |
| 215 | res = find_resource(pbus->dev, 0x90); |
| 216 | |
| 217 | return do_smbus_send_byte(res->base, device, val); |
| 218 | } |
| 219 | |
| 220 | static int lsmbus_read_byte(device_t dev, u8 address) |
| 221 | { |
| 222 | u32 device; |
| 223 | struct resource *res; |
| 224 | struct bus *pbus; |
| 225 | |
| 226 | device = dev->path.i2c.device; |
| 227 | pbus = get_pbus_smbus(dev); |
| 228 | |
| 229 | res = find_resource(pbus->dev, 0x90); |
| 230 | |
| 231 | return do_smbus_read_byte(res->base, device, address); |
| 232 | } |
| 233 | |
| 234 | static int lsmbus_write_byte(device_t dev, u8 address, u8 val) |
| 235 | { |
| 236 | u32 device; |
| 237 | struct resource *res; |
| 238 | struct bus *pbus; |
| 239 | |
| 240 | device = dev->path.i2c.device; |
| 241 | pbus = get_pbus_smbus(dev); |
| 242 | |
| 243 | res = find_resource(pbus->dev, 0x90); |
| 244 | |
| 245 | return do_smbus_write_byte(res->base, device, address, val); |
| 246 | } |
| 247 | static struct smbus_bus_operations lops_smbus_bus = { |
| 248 | .recv_byte = lsmbus_recv_byte, |
| 249 | .send_byte = lsmbus_send_byte, |
| 250 | .read_byte = lsmbus_read_byte, |
| 251 | .write_byte = lsmbus_write_byte, |
| 252 | }; |
| 253 | |
| 254 | static void sb800_sm_read_resources(device_t dev) |
| 255 | { |
| 256 | struct resource *res; |
| 257 | u8 byte; |
| 258 | |
| 259 | /* rpr2.14: Hides SM bus controller Bar1 where stores HPET MMIO base address */ |
| 260 | byte = pm_ioread(0x55); |
| 261 | byte |= 1 << 7; |
| 262 | pm_iowrite(0x55, byte); |
| 263 | |
| 264 | /* Get the normal pci resources of this device */ |
| 265 | /* pci_dev_read_resources(dev); */ |
| 266 | |
| 267 | byte = pm_ioread(0x55); |
| 268 | byte &= ~(1 << 7); |
| 269 | pm_iowrite(0x55, byte); |
| 270 | |
| 271 | /* apic */ |
| 272 | res = new_resource(dev, 0x74); |
Patrick Georgi | 2c2e78d | 2012-02-16 18:54:37 +0100 | [diff] [blame] | 273 | res->base = IO_APIC_ADDR; |
Zheng Bao | d098575 | 2011-01-20 04:45:48 +0000 | [diff] [blame] | 274 | res->size = 256 * 0x10; |
| 275 | res->limit = 0xFEFFFFFUL; /* res->base + res->size -1; */ |
| 276 | res->align = 8; |
| 277 | res->gran = 8; |
| 278 | res->flags = IORESOURCE_MEM | IORESOURCE_FIXED; |
| 279 | |
| 280 | #if 0 /* Linux ACPI crashes when it is 1. For late debugging. */ |
| 281 | res = new_resource(dev, 0x14); /* TODO: hpet */ |
| 282 | res->base = 0xfed00000; /* reset hpet to widely accepted address */ |
| 283 | res->size = 0x400; |
| 284 | res->limit = 0xFFFFFFFFUL; /* res->base + res->size -1; */ |
| 285 | res->align = 8; |
| 286 | res->gran = 8; |
| 287 | res->flags = IORESOURCE_MEM | IORESOURCE_FIXED; |
| 288 | #endif |
| 289 | /* dev->command |= PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER; */ |
| 290 | |
| 291 | /* smbus */ |
| 292 | //res = new_resource(dev, 0x90); |
| 293 | //res->base = 0xB00; |
| 294 | //res->size = 0x10; |
| 295 | //res->limit = 0xFFFFUL; /* res->base + res->size -1; */ |
| 296 | //res->align = 8; |
| 297 | //res->gran = 8; |
| 298 | //res->flags = IORESOURCE_IO | IORESOURCE_FIXED; |
| 299 | |
| 300 | |
| 301 | compact_resources(dev); |
| 302 | } |
| 303 | |
| 304 | static void sb800_sm_set_resources(struct device *dev) |
| 305 | { |
| 306 | struct resource *res; |
| 307 | u8 byte; |
| 308 | |
| 309 | pci_dev_set_resources(dev); |
| 310 | |
| 311 | |
Martin Roth | dcf253c | 2014-12-16 20:51:31 -0700 | [diff] [blame] | 312 | /* rpr2.14: Make HPET MMIO decoding controlled by the memory enable bit in command register of LPC ISA bridge */ |
Zheng Bao | d098575 | 2011-01-20 04:45:48 +0000 | [diff] [blame] | 313 | byte = pm_ioread(0x52); |
| 314 | byte |= 1 << 6; |
| 315 | pm_iowrite(0x52, byte); |
| 316 | |
| 317 | res = find_resource(dev, 0x74); |
| 318 | |
| 319 | printk(BIOS_INFO, "sb800_sm_set_resources, res->base=0x%llx\n", res->base); |
| 320 | |
| 321 | //pci_write_config32(dev, 0x74, res->base | 1 << 3); |
| 322 | pm_iowrite(0x34, res->base | 0x7); |
| 323 | pm_iowrite(0x35, (res->base >> 8) & 0xFF); |
| 324 | pm_iowrite(0x36, (res->base >> 16) & 0xFF); |
| 325 | pm_iowrite(0x37, (res->base >> 24) & 0xFF); |
| 326 | #if 0 /* TODO:hpet */ |
| 327 | res = find_resource(dev, 0x14); |
| 328 | pci_write_config32(dev, 0x14, res->base); |
| 329 | #endif |
| 330 | //res = find_resource(dev, 0x90); |
| 331 | //pci_write_config32(dev, 0x90, res->base | 1); |
| 332 | } |
| 333 | |
| 334 | static struct pci_operations lops_pci = { |
| 335 | .set_subsystem = pci_dev_set_subsystem, |
| 336 | }; |
| 337 | static struct device_operations smbus_ops = { |
| 338 | .read_resources = sb800_sm_read_resources, |
| 339 | .set_resources = sb800_sm_set_resources, |
| 340 | .enable_resources = pci_dev_enable_resources, |
| 341 | .init = sm_init, |
Kyösti Mälkki | d0e212c | 2015-02-26 20:47:47 +0200 | [diff] [blame] | 342 | .scan_bus = scan_smbus, |
Zheng Bao | d098575 | 2011-01-20 04:45:48 +0000 | [diff] [blame] | 343 | .ops_pci = &lops_pci, |
| 344 | .ops_smbus_bus = &lops_smbus_bus, |
| 345 | }; |
| 346 | static const struct pci_driver smbus_driver __pci_driver = { |
| 347 | .ops = &smbus_ops, |
| 348 | .vendor = PCI_VENDOR_ID_ATI, |
| 349 | .device = PCI_DEVICE_ID_ATI_SB800_SM, |
| 350 | }; |