Zheng Bao | d098575 | 2011-01-20 04:45:48 +0000 | [diff] [blame] | 1 | /* |
| 2 | * This file is part of the coreboot project. |
| 3 | * |
| 4 | * Copyright (C) 2010 Advanced Micro Devices, Inc. |
| 5 | * |
| 6 | * This program is free software; you can redistribute it and/or modify |
| 7 | * it under the terms of the GNU General Public License as published by |
| 8 | * the Free Software Foundation; version 2 of the License. |
| 9 | * |
| 10 | * This program is distributed in the hope that it will be useful, |
| 11 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 12 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 13 | * GNU General Public License for more details. |
Zheng Bao | d098575 | 2011-01-20 04:45:48 +0000 | [diff] [blame] | 14 | */ |
| 15 | |
| 16 | #include <console/console.h> |
| 17 | |
| 18 | #include <arch/io.h> |
| 19 | |
| 20 | #include <device/device.h> |
| 21 | #include <device/pci.h> |
| 22 | #include <device/pci_ids.h> |
| 23 | #include <device/pci_ops.h> |
| 24 | #include "sb800.h" |
| 25 | #include "smbus.h" |
| 26 | |
| 27 | static device_t find_sm_dev(device_t dev, u32 devfn) |
| 28 | { |
| 29 | device_t sm_dev; |
| 30 | |
| 31 | sm_dev = dev_find_slot(dev->bus->secondary, devfn); |
| 32 | if (!sm_dev) |
| 33 | return sm_dev; |
| 34 | |
| 35 | if ((sm_dev->vendor != PCI_VENDOR_ID_ATI) || |
| 36 | ((sm_dev->device != PCI_DEVICE_ID_ATI_SB800_SM))) { |
| 37 | u32 id; |
| 38 | id = pci_read_config32(sm_dev, PCI_VENDOR_ID); |
| 39 | if ((id != |
| 40 | (PCI_VENDOR_ID_ATI | (PCI_DEVICE_ID_ATI_SB800_SM << 16)))) |
| 41 | { |
| 42 | sm_dev = 0; |
| 43 | } |
| 44 | } |
| 45 | |
| 46 | return sm_dev; |
| 47 | } |
| 48 | |
| 49 | void set_sm_enable_bits(device_t sm_dev, u32 reg_pos, u32 mask, u32 val) |
| 50 | { |
| 51 | u32 reg_old, reg; |
| 52 | reg = reg_old = pci_read_config32(sm_dev, reg_pos); |
| 53 | reg &= ~mask; |
| 54 | reg |= val; |
| 55 | if (reg != reg_old) { |
| 56 | pci_write_config32(sm_dev, reg_pos, reg); |
| 57 | } |
| 58 | } |
| 59 | |
| 60 | static void pmio_write_index(u16 port_base, u8 reg, u8 value) |
| 61 | { |
| 62 | outb(reg, port_base); |
| 63 | outb(value, port_base + 1); |
| 64 | } |
| 65 | |
| 66 | static u8 pmio_read_index(u16 port_base, u8 reg) |
| 67 | { |
| 68 | outb(reg, port_base); |
| 69 | return inb(port_base + 1); |
| 70 | } |
| 71 | |
| 72 | void pm_iowrite(u8 reg, u8 value) |
| 73 | { |
| 74 | pmio_write_index(PM_INDEX, reg, value); |
| 75 | } |
| 76 | |
| 77 | u8 pm_ioread(u8 reg) |
| 78 | { |
| 79 | return pmio_read_index(PM_INDEX, reg); |
| 80 | } |
| 81 | |
| 82 | void pm2_iowrite(u8 reg, u8 value) |
| 83 | { |
| 84 | pmio_write_index(PM2_INDEX, reg, value); |
| 85 | } |
| 86 | |
| 87 | u8 pm2_ioread(u8 reg) |
| 88 | { |
| 89 | return pmio_read_index(PM2_INDEX, reg); |
| 90 | } |
| 91 | |
| 92 | static void set_pmio_enable_bits(u32 reg_pos, u32 mask, u32 val) |
| 93 | { |
| 94 | u8 reg_old, reg; |
| 95 | reg = reg_old = pm_ioread(reg_pos); |
| 96 | reg &= ~mask; |
| 97 | reg |= val; |
| 98 | if (reg != reg_old) { |
| 99 | pm_iowrite(reg_pos, reg); |
| 100 | } |
| 101 | } |
| 102 | |
| 103 | u16 tx_convert_table[] = { |
| 104 | [0x0] = 0xFFFF, |
| 105 | [0x1] = 0xFFFE, |
| 106 | [0x2] = 0xFFFC, |
| 107 | [0x3] = 0xFFF8, |
| 108 | [0x4] = 0xFFF0, |
| 109 | [0x5] = 0xFFE0, |
| 110 | [0x6] = 0xFFC0, |
| 111 | [0x7] = 0xFF80, |
| 112 | [0x8] = 0xFF00, |
| 113 | [0x9] = 0xFE00, |
| 114 | [0xA] = 0xFC00, |
| 115 | [0xB] = 0xF800, |
| 116 | [0xC] = 0xF000, |
| 117 | [0xD] = 0xE000, |
| 118 | [0xE] = 0xC000, |
| 119 | [0xF] = 0x8000 |
| 120 | }; |
| 121 | |
| 122 | u16 rx_convert_table[] = { |
| 123 | [0x0] = 0x0001, |
| 124 | [0x1] = 0x0003, |
| 125 | [0x2] = 0x0007, |
| 126 | [0x3] = 0x000F, |
| 127 | [0x4] = 0x001F, |
| 128 | [0x5] = 0x003F, |
| 129 | [0x6] = 0x007F, |
| 130 | [0x7] = 0x00FF, |
| 131 | [0x8] = 0x01FF, |
| 132 | [0x9] = 0x03FF, |
| 133 | [0xA] = 0x07FF, |
| 134 | [0xB] = 0x0FFF, |
| 135 | [0xC] = 0x1FFF, |
| 136 | [0xD] = 0x3FFF, |
| 137 | [0xE] = 0x7FFF, |
| 138 | [0xF] = 0xFFFF |
| 139 | }; |
| 140 | |
| 141 | /* PCIe General Purpose Ports */ |
| 142 | /* v:1814, d:3090. cp421A */ |
| 143 | static void set_sb800_gpp(device_t dev) |
| 144 | { |
| 145 | struct southbridge_amd_sb800_config *conf; |
| 146 | u32 imp_rb, lc_status; |
| 147 | u8 port; |
| 148 | |
| 149 | conf = dev->chip_info; |
| 150 | port = dev->path.pci.devfn & 3; |
| 151 | |
| 152 | /* 5.1 GPP Lane Configuration */ |
| 153 | /* To support one of 4 legal configurations: |
| 154 | * 0000: PortA lanes[3:0] |
| 155 | * 0001: N/A |
| 156 | * 0010: PortA lanes[1:0], PortB lanes[3:2] |
| 157 | * 0011: PortA lanes[1:0], PortB lane2, PortC lane3 |
| 158 | * 0100: PortA lane0, PortB lane1, PortC lane2, PortD lane3. |
| 159 | * Other combinations are not supported. |
| 160 | */ |
| 161 | /* CIMx: Set abcfg:0x90[20] = 1 to enable GPP bridge multi-function */ |
| 162 | abcfg_reg(0x90, 1 << 20, 1 << 20); |
| 163 | |
| 164 | printk(BIOS_DEBUG, "set_sb800_gpp() 1\n"); |
| 165 | //abcfg_reg(0xC0, 0xF << 0, 0x4 << 0); /* bimini:4; tarpon:3 */ |
| 166 | abcfg_reg(0xC0, 0xF << 0, (conf->gpp_configuration & 0xF) << 0); /* bimini:4; tarpon:3 */ |
| 167 | |
| 168 | printk(BIOS_DEBUG, "set_sb800_gpp() 2,\n"); |
| 169 | /* 5.2 Enabling GPP Port A/B/C/D */ |
| 170 | //abcfg_reg(0xC0, 0xF << 4, 0x1 << 4); |
| 171 | abcfg_reg(0xC0, 0xF << 4, dev->enabled ? 0x1 << (4 + port) : 0); |
| 172 | |
| 173 | printk(BIOS_DEBUG, "set_sb800_gpp() 3\n"); |
| 174 | /* 5.3 Releasing GPP Reset */ |
| 175 | abcfg_reg(0xC0, 0x1 << 8, 0x0 << 8); |
| 176 | |
| 177 | /* release training */ |
| 178 | abcfg_reg(0xC0, 0xF << 12, 0x0 << 12); |
| 179 | /* 5.4 Power Saving Feature for GPP Lanes. Skip */ |
| 180 | /* 5.5 PCIe Ports De-emphasis Settings. Skip */ |
| 181 | abcfg_reg(0x340, 1 << 21, 0 << 21); |
| 182 | abcfg_reg(0x344, 1 << 21, 0 << 21); |
| 183 | abcfg_reg(0x348, 1 << 21, 0 << 21); |
| 184 | abcfg_reg(0x34C, 1 << 21, 0 << 21); |
| 185 | /* 5.6 PCIe PHY Calibration Impedance Value Setting */ |
| 186 | /* AXINDC_Reg 0x60: TX_IMP_RB */ |
| 187 | outl(0x30, 0xCD8); |
| 188 | outl(0x60, 0xCDC); |
| 189 | outl(0x34, 0xCD8); |
| 190 | imp_rb = inl(0xCDC); |
| 191 | |
| 192 | printk(BIOS_DEBUG, "imp_rb 1=%x\n", imp_rb); |
| 193 | /* tx */ |
| 194 | abcfg_reg(0xA4, 0x1FFF, (rx_convert_table[(imp_rb>>8)&0xF]) & 0x1FFF); |
| 195 | abcfg_reg(0xA4, 0x1FFF<<19, ((tx_convert_table[(imp_rb>>4)&0xF] >> 3) & 0x1FFF) << 19); |
| 196 | |
| 197 | /* 5.4. */ |
| 198 | abcfg_reg(0xA0, 3 << 12, 3 << 12); |
| 199 | |
| 200 | axindxp_reg(0xa0, 0xf<<4, 3<<4); |
| 201 | rcindxp_reg(0xA0, 0, 0xF << 4, 1 << 0); |
| 202 | rcindxp_reg(0xA0, 1, 0xF << 4, 1 << 0); |
| 203 | rcindxp_reg(0xA0, 2, 0xF << 4, 1 << 0); |
| 204 | rcindxp_reg(0xA0, 3, 0xF << 4, 1 << 0); |
| 205 | |
| 206 | /* 5.8 Disabling Serial Number Capability */ |
| 207 | abcfg_reg(0x330, 1 << 26, 0 << 26); |
| 208 | |
| 209 | abcfg_reg(0x50, 0xFFFFFFFF, 0x04000004); |
| 210 | abcfg_reg(0x54, 0xFFFFFFFF, 0x00040000); |
| 211 | abcfg_reg(0x80, 0xFFFFFFFF, 0x03060001); |
| 212 | abcfg_reg(0x90, 0xFFFFFFFF, 0x00300000); |
| 213 | abcfg_reg(0x98, 0xFFFFFFFF, 0x03034700); |
| 214 | |
| 215 | pci_write_config32(dev, 0x80, 0x00000006); |
| 216 | /* Set PCIEIND_P:PCIE_RX_CNTL[RX_RCB_CPL_TIMEOUT_MODE] (0x70:[19]) = 1 */ |
| 217 | rcindxp_reg(0x70, 0, 1 << 19, 1 << 19); |
| 218 | //outl(3<<29|0<<24|0x70, 0xCD8); |
| 219 | /* Set PCIEIND_P:PCIE_TX_CNTL[TX_FLUSH_TLP_DIS] (0x20:[19]) = 0 */ |
| 220 | rcindxp_reg(0x20, 0, 1 << 19, 0 << 19); |
| 221 | printk(BIOS_DEBUG, "imp_rb 5=%x\n", imp_rb); |
| 222 | outl(3<<29|0<<24|0xA5, 0xCD8); |
| 223 | lc_status = inl(0xCDC); |
| 224 | printk(BIOS_DEBUG, "lc_status=%x\n", lc_status); |
| 225 | } |
| 226 | |
| 227 | void sb800_enable(device_t dev) |
| 228 | { |
| 229 | device_t sm_dev = 0; |
| 230 | device_t bus_dev = 0; |
| 231 | int index = -1; |
| 232 | u32 deviceid; |
| 233 | u32 vendorid; |
| 234 | |
| 235 | /* struct southbridge_ati_sb800_config *conf; */ |
| 236 | /* conf = dev->chip_info; */ |
| 237 | int i; |
| 238 | |
| 239 | u32 devfn, dword; |
| 240 | |
| 241 | printk(BIOS_DEBUG, "sb800_enable()\n"); |
| 242 | |
| 243 | /* |
| 244 | * 0:11.0 SATA bit 8 of pmio 0xDA : 1 - enable |
| 245 | * 0:12.0 OHCI-USB1 bit 0 of pmio 0xEF |
| 246 | * 0:12.2 EHCI-USB1 bit 1 of pmio 0xEF |
| 247 | * 0:13.0 OHCI-USB2 bit 2 of pmio 0xEF |
| 248 | * 0:13.2 EHCI-USB2 bit 3 of pmio 0xEF |
| 249 | * 0:16.1 OHCI-USB3 bit 4 of pmio 0xEF |
| 250 | * 0:16.2 EHCI-USB3 bit 5 of pmio 0xEF |
| 251 | * 0:14.5 OHCI-USB4 bit 6 of pmio 0xEF |
| 252 | * 0:14.0 SMBUS 0 |
| 253 | * 0:14.1 IDE 1 |
| 254 | * 0:14.2 HDA bit 0 of pm_io 0xEB : 1 - enable |
| 255 | * 0:14.3 LPC bit 0 of pm_io 0xEC : 1 - enable |
| 256 | * 0:14.4 PCI bit 0 of pm_io 0xEA : 0 - enable |
| 257 | * 0:14.6 GEC bit 0 of pm_io 0xF6 : 0 - enable |
| 258 | */ |
| 259 | if (dev->device == 0x0000) { |
| 260 | vendorid = pci_read_config32(dev, PCI_VENDOR_ID); |
| 261 | deviceid = (vendorid >> 16) & 0xffff; |
| 262 | vendorid &= 0xffff; |
| 263 | } else { |
| 264 | vendorid = dev->vendor; |
| 265 | deviceid = dev->device; |
| 266 | } |
| 267 | bus_dev = dev->bus->dev; |
| 268 | if ((bus_dev->vendor == PCI_VENDOR_ID_ATI) && |
| 269 | (bus_dev->device == PCI_DEVICE_ID_ATI_SB800_PCI)) { |
| 270 | devfn = (bus_dev->path.pci.devfn) & ~7; |
| 271 | sm_dev = find_sm_dev(bus_dev, devfn); |
| 272 | if (!sm_dev) |
| 273 | return; |
| 274 | |
| 275 | /* something under 00:01.0 */ |
| 276 | switch (dev->path.pci.devfn) { |
| 277 | case 5 << 3: |
| 278 | ; |
| 279 | } |
| 280 | |
| 281 | return; |
| 282 | } |
| 283 | printk(BIOS_DEBUG, "sb800_enable() 1\n"); |
| 284 | |
| 285 | i = (dev->path.pci.devfn) & ~7; |
| 286 | i += (3 << 3); |
| 287 | for (devfn = (0x14 << 3); devfn <= i; devfn += (1 << 3)) { |
| 288 | sm_dev = find_sm_dev(dev, devfn); |
| 289 | if (sm_dev) |
| 290 | break; |
| 291 | } |
| 292 | if (!sm_dev) |
| 293 | return; |
| 294 | printk(BIOS_DEBUG, "sb800_enable() 2\n"); |
| 295 | |
| 296 | switch (dev->path.pci.devfn - (devfn - (0x14 << 3))) { |
| 297 | case (0x11 << 3) | 0: |
| 298 | index = 8; |
| 299 | set_pmio_enable_bits(0xDA, 1 << 0, |
| 300 | (dev->enabled ? 1 : 0) << 0); |
| 301 | /* Set the device ID of SATA as 0x4390 to reduce the confusing. */ |
| 302 | dword = pci_read_config32(dev, 0x40); |
| 303 | dword |= 1 << 0; |
| 304 | pci_write_config32(dev, 0x40, dword); |
| 305 | pci_write_config16(dev, 0x2, 0x4390); |
| 306 | dword &= ~1; |
| 307 | pci_write_config32(dev, 0x40, dword);//for (;;); |
| 308 | index += 32 * 3; |
| 309 | break; |
| 310 | case (0x12 << 3) | 0: |
| 311 | case (0x12 << 3) | 2: |
| 312 | index = (dev->path.pci.devfn & 0x3) / 2; |
| 313 | set_pmio_enable_bits(0xEF, 1 << index, |
| 314 | (dev->enabled ? 1 : 0) << index); |
| 315 | break; |
| 316 | case (0x13 << 3) | 0: |
| 317 | case (0x13 << 3) | 2: |
| 318 | index = (dev->path.pci.devfn & 0x3) / 2 + 2; |
| 319 | set_pmio_enable_bits(0xEF, 1 << index, |
| 320 | (dev->enabled ? 1 : 0) << index); |
| 321 | index += 32 * 2; |
| 322 | break; |
| 323 | case (0x14 << 3) | 0: |
| 324 | index = 0; |
| 325 | break; |
| 326 | case (0x14 << 3) | 1: |
| 327 | index = 1; |
| 328 | set_pmio_enable_bits(0xDA, 1 << 3, |
| 329 | (dev->enabled ? 0 : 1) << 3); |
| 330 | break; |
| 331 | case (0x14 << 3) | 2: |
| 332 | index = 0; |
| 333 | set_pmio_enable_bits(0xEB, 1 << index, |
| 334 | (dev->enabled ? 1 : 0) << index); |
| 335 | break; |
| 336 | case (0x14 << 3) | 3: |
| 337 | index = 0; |
| 338 | set_pmio_enable_bits(0xEC, 1 << index, |
| 339 | (dev->enabled ? 1 : 0) << index); |
| 340 | index += 32 * 1; |
| 341 | break; |
| 342 | case (0x14 << 3) | 4: |
| 343 | index = 0; |
| 344 | set_pmio_enable_bits(0xEA, 1 << index, |
| 345 | (dev->enabled ? 0 : 1) << index); |
| 346 | break; |
| 347 | case (0x14 << 3) | 5: |
| 348 | index = 6; |
| 349 | set_pmio_enable_bits(0xEF, 1 << index, |
| 350 | (dev->enabled ? 1 : 0) << index); |
| 351 | break; |
| 352 | case (0x14 << 3) | 6: |
Zheng Bao | d098575 | 2011-01-20 04:45:48 +0000 | [diff] [blame] | 353 | index = 0; |
| 354 | set_pmio_enable_bits(0xF6, 1 << index, |
| 355 | (dev->enabled ? 0 : 1) << index); |
| 356 | break; |
| 357 | case (0x15 << 3) | 0: |
| 358 | set_sb800_gpp(dev); |
| 359 | index = 4; |
| 360 | break; |
| 361 | case (0x15 << 3) | 1: |
| 362 | case (0x15 << 3) | 2: |
| 363 | case (0x15 << 3) | 3: |
| 364 | break; |
| 365 | case (0x16 << 3) | 0: |
| 366 | case (0x16 << 3) | 2: |
| 367 | index = (dev->path.pci.devfn & 0x3) / 2 + 4; |
| 368 | set_pmio_enable_bits(0xEF, 1 << index, |
| 369 | (dev->enabled ? 1 : 0) << index); |
| 370 | break; |
| 371 | default: |
| 372 | printk(BIOS_DEBUG, "unknown dev: %s deviceid=%4x\n", dev_path(dev), |
| 373 | deviceid); |
| 374 | } |
| 375 | } |
| 376 | |
| 377 | struct chip_operations southbridge_amd_sb800_ops = { |
| 378 | CHIP_NAME("ATI SB800") |
| 379 | .enable_dev = sb800_enable, |
| 380 | }; |