Zheng Bao | d098575 | 2011-01-20 04:45:48 +0000 | [diff] [blame] | 1 | /* |
| 2 | * This file is part of the coreboot project. |
| 3 | * |
| 4 | * Copyright (C) 2010 Advanced Micro Devices, Inc. |
| 5 | * |
| 6 | * This program is free software; you can redistribute it and/or modify |
| 7 | * it under the terms of the GNU General Public License as published by |
| 8 | * the Free Software Foundation; version 2 of the License. |
| 9 | * |
| 10 | * This program is distributed in the hope that it will be useful, |
| 11 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 12 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 13 | * GNU General Public License for more details. |
Zheng Bao | d098575 | 2011-01-20 04:45:48 +0000 | [diff] [blame] | 14 | */ |
| 15 | |
Elyes HAOUAS | 65fa598 | 2014-07-22 23:12:38 +0200 | [diff] [blame] | 16 | #ifndef _SB800_EARLY_SETUP_C_ |
| 17 | #define _SB800_EARLY_SETUP_C_ |
Zheng Bao | d098575 | 2011-01-20 04:45:48 +0000 | [diff] [blame] | 18 | |
| 19 | #include <reset.h> |
Kyösti Mälkki | 207880c | 2013-12-10 09:03:17 +0200 | [diff] [blame] | 20 | #include <arch/acpi.h> |
Zheng Bao | d098575 | 2011-01-20 04:45:48 +0000 | [diff] [blame] | 21 | #include <arch/cpu.h> |
| 22 | #include <cbmem.h> |
| 23 | #include "sb800.h" |
| 24 | #include "smbus.c" |
| 25 | |
| 26 | #define SMBUS_IO_BASE 0x6000 /* Is it a temporary SMBus I/O base address? */ |
| 27 | /*SIZE 0x40 */ |
| 28 | |
| 29 | static void pmio_write(u8 reg, u8 value) |
| 30 | { |
| 31 | outb(reg, PM_INDEX); |
| 32 | outb(value, PM_INDEX + 1); |
| 33 | } |
| 34 | |
| 35 | static u8 pmio_read(u8 reg) |
| 36 | { |
| 37 | outb(reg, PM_INDEX); |
| 38 | return inb(PM_INDEX + 1); |
| 39 | } |
| 40 | |
Zheng Bao | a5c949e | 2011-01-27 03:31:50 +0000 | [diff] [blame] | 41 | static void sb800_acpi_init(void) |
| 42 | { |
Zheng Bao | d098575 | 2011-01-20 04:45:48 +0000 | [diff] [blame] | 43 | pmio_write(0x60, ACPI_PM_EVT_BLK & 0xFF); |
| 44 | pmio_write(0x61, ACPI_PM_EVT_BLK >> 8); |
| 45 | pmio_write(0x62, ACPI_PM1_CNT_BLK & 0xFF); |
| 46 | pmio_write(0x63, ACPI_PM1_CNT_BLK >> 8); |
| 47 | pmio_write(0x64, ACPI_PM_TMR_BLK & 0xFF); |
| 48 | pmio_write(0x65, ACPI_PM_TMR_BLK >> 8); |
| 49 | pmio_write(0x68, ACPI_GPE0_BLK & 0xFF); |
| 50 | pmio_write(0x69, ACPI_GPE0_BLK >> 8); |
| 51 | |
Timothy Pearson | 033bb4b | 2015-02-10 22:21:39 -0600 | [diff] [blame] | 52 | /* CpuControl is in \_PR.CP00, 6 bytes */ |
Zheng Bao | d098575 | 2011-01-20 04:45:48 +0000 | [diff] [blame] | 53 | pmio_write(0x66, ACPI_CPU_CONTROL & 0xFF); |
| 54 | pmio_write(0x67, ACPI_CPU_CONTROL >> 8); |
| 55 | |
Zheng Bao | a302b58 | 2011-01-24 07:50:07 +0000 | [diff] [blame] | 56 | pmio_write(0x6A, 0xB0); /* AcpiSmiCmdLo */ |
Zheng Bao | d098575 | 2011-01-20 04:45:48 +0000 | [diff] [blame] | 57 | pmio_write(0x6B, 0); /* AcpiSmiCmdHi */ |
| 58 | |
Zheng Bao | a302b58 | 2011-01-24 07:50:07 +0000 | [diff] [blame] | 59 | pmio_write(0x6E, 0xB8); /* AcpiPmaCntBlkLo */ |
| 60 | pmio_write(0x6F, 0); /* AcpiPmaCntBlkHi */ |
| 61 | |
Zheng Bao | d098575 | 2011-01-20 04:45:48 +0000 | [diff] [blame] | 62 | pmio_write(0x6C, ACPI_PMA_CNT_BLK & 0xFF); |
| 63 | pmio_write(0x6D, ACPI_PMA_CNT_BLK >> 8); |
| 64 | |
Zheng Bao | 79c04d5 | 2011-01-20 05:41:11 +0000 | [diff] [blame] | 65 | pmio_write(0x74, 1<<0 | 1<<1 | 1<<4 | 1<<2); /* AcpiDecodeEnable, When set, SB uses |
Zheng Bao | d098575 | 2011-01-20 04:45:48 +0000 | [diff] [blame] | 66 | * the contents of the PM registers at |
| 67 | * index 60-6B to decode ACPI I/O address. |
| 68 | * AcpiSmiEn & SmiCmdEn*/ |
Zheng Bao | 72cc87f | 2011-01-21 08:46:27 +0000 | [diff] [blame] | 69 | /* RTC_En_En, TMR_En_En, GBL_EN_EN */ |
| 70 | outl(0x1, ACPI_PM1_CNT_BLK); /* set SCI_EN */ |
Zheng Bao | d098575 | 2011-01-20 04:45:48 +0000 | [diff] [blame] | 71 | } |
| 72 | |
| 73 | /* RPR 2.28 Get SB ASIC Revision.*/ |
| 74 | static u8 get_sb800_revision(void) |
| 75 | { |
| 76 | device_t dev; |
| 77 | u8 rev_id; |
| 78 | u8 rev = 0; |
| 79 | |
| 80 | /* if (rev != 0) return rev; */ |
| 81 | |
| 82 | dev = PCI_DEV(0, 0x14, 0);//pci_locate_device(PCI_ID(0x1002, 0x4385), 0); |
| 83 | |
| 84 | if (dev == PCI_DEV_INVALID) { |
| 85 | die("SMBUS controller not found\n"); |
| 86 | /* NOT REACHED */ |
| 87 | } |
| 88 | rev_id = pci_read_config8(dev, 0x08); |
| 89 | |
| 90 | if (rev_id == 0x40) { |
| 91 | rev = REV_SB800_A11; |
| 92 | } else if (rev_id == 0x41) { |
| 93 | rev = REV_SB800_A12; |
| 94 | } else { |
| 95 | die("It is not SB800 or SB810\r\n"); |
| 96 | } |
| 97 | |
| 98 | return rev; |
| 99 | } |
| 100 | |
Zheng Bao | 79c04d5 | 2011-01-20 05:41:11 +0000 | [diff] [blame] | 101 | void sb800_clk_output_48Mhz(void) |
Zheng Bao | d098575 | 2011-01-20 04:45:48 +0000 | [diff] [blame] | 102 | { |
| 103 | /* AcpiMMioDecodeEn */ |
| 104 | u8 reg8; |
| 105 | reg8 = pmio_read(0x24); |
| 106 | reg8 |= 1; |
| 107 | reg8 &= ~(1 << 1); |
| 108 | pmio_write(0x24, reg8); |
| 109 | |
| 110 | *(volatile u32 *)(0xFED80000+0xE00+0x40) &= ~((1 << 0) | (1 << 2)); /* 48Mhz */ |
| 111 | *(volatile u32 *)(0xFED80000+0xE00+0x40) |= 1 << 1; /* 48Mhz */ |
| 112 | } |
Zheng Bao | d098575 | 2011-01-20 04:45:48 +0000 | [diff] [blame] | 113 | /*************************************** |
| 114 | * Legacy devices are mapped to LPC space. |
| 115 | * Serial port 0 |
| 116 | * KBC Port |
| 117 | * ACPI Micro-controller port |
| 118 | * LPC ROM size |
| 119 | * This function does not change port 0x80 decoding. |
| 120 | * Console output through any port besides 0x3f8 is unsupported. |
| 121 | * If you use FWH ROMs, you have to setup IDSEL. |
| 122 | ***************************************/ |
| 123 | static void sb800_lpc_init(void) |
| 124 | { |
| 125 | u8 reg8; |
| 126 | device_t dev; |
| 127 | |
| 128 | //dev = pci_locate_device(PCI_ID(0x1002, 0x4385), 0); /* SMBUS controller */ |
| 129 | dev = PCI_DEV(0, 0x14, 0); |
| 130 | /* NOTE: Set BootTimerDisable, otherwise it would keep rebooting!! |
| 131 | * This bit has no meaning if debug strap is not enabled. So if the |
| 132 | * board keeps rebooting and the code fails to reach here, we could |
| 133 | * disable the debug strap first. */ |
| 134 | reg8 = pmio_read(0x44+3); |
| 135 | reg8 |= 1 << 7; |
| 136 | pmio_write(0x44+3, reg8); |
| 137 | |
| 138 | /* Enable lpc controller */ |
| 139 | reg8 = pmio_read(0xEC); |
| 140 | reg8 |= 1 << 0; |
| 141 | pmio_write(0xEC, reg8); |
| 142 | |
| 143 | dev = PCI_DEV(0, 0x14, 3);//pci_locate_device(PCI_ID(0x1002, 0x439d), 0); /* LPC Controller */ |
| 144 | /* Decode port 0x3f8-0x3ff (Serial 0) */ |
| 145 | //#warning Serial port decode on LPC is hardcoded to 0x3f8 |
| 146 | reg8 = pci_read_config8(dev, 0x44); |
| 147 | reg8 |= 1 << 6; |
| 148 | pci_write_config8(dev, 0x44, reg8); |
| 149 | |
| 150 | /* Decode port 0x60 & 0x64 (PS/2 keyboard) and port 0x62 & 0x66 (ACPI)*/ |
| 151 | reg8 = pci_read_config8(dev, 0x47); |
| 152 | reg8 |= (1 << 5) | (1 << 6); |
| 153 | pci_write_config8(dev, 0x47, reg8); |
| 154 | |
| 155 | /* SuperIO, LPC ROM */ |
| 156 | reg8 = pci_read_config8(dev, 0x48); |
| 157 | /* Decode ports 0x2e-0x2f, 0x4e-0x4f (SuperI/O configuration) */ |
| 158 | reg8 |= (1 << 1) | (1 << 0); |
| 159 | /* Decode variable LPC ROM address ranges 1&2 (see register 0x68-0x6b, 0x6c-0x6f) */ |
| 160 | reg8 |= (1 << 3) | (1 << 4); |
| 161 | /* Decode port 0x70-0x73 (RTC) */ |
| 162 | reg8 |= 1 << 6; |
| 163 | pci_write_config8(dev, 0x48, reg8); |
| 164 | } |
| 165 | |
| 166 | /* what is its usage? */ |
| 167 | static u32 get_sbdn(u32 bus) |
| 168 | { |
| 169 | device_t dev; |
| 170 | |
| 171 | /* Find the device. */ |
| 172 | dev = PCI_DEV(bus, 0x14, 0);//pci_locate_device_on_bus(PCI_ID(0x1002, 0x4385), bus); |
| 173 | return (dev >> 15) & 0x1f; |
| 174 | } |
| 175 | |
| 176 | static u8 dual_core(void) |
| 177 | { |
| 178 | return (pci_read_config32(PCI_DEV(0, 0x18, 3), 0xE8) & (0x3<<12)) != 0; |
| 179 | } |
| 180 | |
| 181 | /* |
| 182 | * RPR 2.6 C-state and VID/FID change for the K8 platform. |
| 183 | */ |
| 184 | static void enable_fid_change_on_sb(u32 sbbusn, u32 sbdn) |
| 185 | { |
| 186 | u8 byte; |
| 187 | byte = pmio_read(0x80); |
| 188 | if (dual_core()) |
| 189 | byte |= 1 << 2 | 1 << 1; |
| 190 | byte |= 1 << 3; |
| 191 | byte |= 1 << 4; |
| 192 | byte &= ~(1 << 7); |
| 193 | pmio_write(0x80, byte); |
| 194 | |
| 195 | byte = pmio_read(0x7E); |
| 196 | byte |= 1 << 6; |
| 197 | byte &= ~(1 << 2); |
| 198 | pmio_write(0x7E, byte); |
| 199 | |
| 200 | pmio_write(0x94, 0x01); |
| 201 | |
| 202 | byte = pmio_read(0x89); |
| 203 | byte |= 1 << 4; |
| 204 | pmio_write(0x89, byte); |
| 205 | |
| 206 | byte = pmio_read(0x9b); |
| 207 | byte &= ~(7 << 4); |
| 208 | byte |= 1 << 4; |
| 209 | pmio_write(0x9b, byte); |
| 210 | |
| 211 | pmio_write(0x99, 0x10); |
| 212 | |
| 213 | pmio_write(0x9A, 0x00); |
| 214 | pmio_write(0x96, 0x10); |
| 215 | pmio_write(0x97, 0x00); |
| 216 | |
| 217 | byte = pmio_read(0x81); |
| 218 | byte &= ~(1 << 1); |
| 219 | pmio_write(0x81, byte); |
| 220 | } |
| 221 | |
| 222 | void hard_reset(void) |
| 223 | { |
| 224 | set_bios_reset(); |
| 225 | |
| 226 | /* full reset */ |
| 227 | outb(0x0a, 0x0cf9); |
| 228 | outb(0x0e, 0x0cf9); |
| 229 | } |
| 230 | |
| 231 | void soft_reset(void) |
| 232 | { |
| 233 | set_bios_reset(); |
| 234 | /* link reset */ |
| 235 | outb(0x06, 0x0cf9); |
| 236 | } |
| 237 | |
Zheng Bao | 79c04d5 | 2011-01-20 05:41:11 +0000 | [diff] [blame] | 238 | void sb800_pci_port80(void) |
Zheng Bao | d098575 | 2011-01-20 04:45:48 +0000 | [diff] [blame] | 239 | { |
| 240 | u8 byte; |
| 241 | device_t dev; |
| 242 | |
| 243 | /* P2P Bridge */ |
| 244 | dev = PCI_DEV(0, 0x14, 4);//pci_locate_device(PCI_ID(0x1002, 0x4384), 0); |
| 245 | |
| 246 | /* Chip Control: Enable subtractive decoding */ |
| 247 | byte = pci_read_config8(dev, 0x40); |
| 248 | byte |= 1 << 5; |
| 249 | pci_write_config8(dev, 0x40, byte); |
| 250 | |
| 251 | /* Misc Control: Enable subtractive decoding if 0x40 bit 5 is set */ |
| 252 | byte = pci_read_config8(dev, 0x4B); |
| 253 | byte |= 1 << 7; |
| 254 | pci_write_config8(dev, 0x4B, byte); |
| 255 | |
| 256 | /* The same IO Base and IO Limit here is meaningful because we set the |
| 257 | * bridge to be subtractive. During early setup stage, we have to make |
| 258 | * sure that data can go through port 0x80. |
| 259 | */ |
| 260 | /* IO Base: 0xf000 */ |
| 261 | byte = pci_read_config8(dev, 0x1C); |
| 262 | byte |= 0xF << 4; |
| 263 | pci_write_config8(dev, 0x1C, byte); |
| 264 | |
| 265 | /* IO Limit: 0xf000 */ |
| 266 | byte = pci_read_config8(dev, 0x1D); |
| 267 | byte |= 0xF << 4; |
| 268 | pci_write_config8(dev, 0x1D, byte); |
| 269 | |
| 270 | /* PCI Command: Enable IO response */ |
| 271 | byte = pci_read_config8(dev, 0x04); |
| 272 | byte |= 1 << 0; |
| 273 | pci_write_config8(dev, 0x04, byte); |
| 274 | |
| 275 | /* LPC controller */ |
Idwer Vollering | d26da9c | 2013-12-22 21:38:18 +0000 | [diff] [blame] | 276 | dev = PCI_DEV(0, 0x14, 3);//pci_locate_device(PCI_ID(0x1002, 0x439D), 0); |
Zheng Bao | d098575 | 2011-01-20 04:45:48 +0000 | [diff] [blame] | 277 | |
| 278 | byte = pci_read_config8(dev, 0x4A); |
| 279 | byte &= ~(1 << 5); /* disable lpc port 80 */ |
| 280 | pci_write_config8(dev, 0x4A, byte); |
| 281 | } |
Zheng Bao | 79c04d5 | 2011-01-20 05:41:11 +0000 | [diff] [blame] | 282 | |
Zheng Bao | d098575 | 2011-01-20 04:45:48 +0000 | [diff] [blame] | 283 | #define BIT0 (1 << 0) |
| 284 | #define BIT1 (1 << 1) |
| 285 | #define BIT2 (1 << 2) |
| 286 | #define BIT3 (1 << 3) |
| 287 | #define BIT4 (1 << 4) |
| 288 | #define BIT5 (1 << 5) |
| 289 | #define BIT6 (1 << 6) |
| 290 | #define BIT7 (1 << 7) |
| 291 | |
| 292 | struct pm_entry { |
| 293 | u8 port; |
| 294 | u8 mask; |
| 295 | u8 bit; |
| 296 | }; |
| 297 | struct pm_entry const pm_table[] = |
| 298 | { |
Zheng Bao | 79c04d5 | 2011-01-20 05:41:11 +0000 | [diff] [blame] | 299 | {0x5D, 0x00, BIT0}, |
| 300 | {0xD2, 0xCF, BIT4 + BIT5}, |
| 301 | {0x12, 0x00, BIT0}, |
| 302 | {0x28, 0xFF, BIT0}, |
| 303 | {0x44 + 3, 0x7F, BIT7}, |
| 304 | {0x48, 0xFF, BIT0}, |
| 305 | {0x00, 0xFF, 0x0E}, |
| 306 | {0x00 + 2, 0xFF, 0x40}, |
| 307 | {0x00 + 3, 0xFF, 0x08}, |
| 308 | {0x34, 0xEF, BIT0 + BIT1}, |
| 309 | {0xEC, 0xFD, BIT1}, |
| 310 | {0x5B, 0xF9, BIT1 + BIT2}, |
| 311 | {0x08, 0xFE, BIT2 + BIT4}, |
| 312 | {0x08 + 1, 0xFF, BIT0}, |
| 313 | {0x54, 0x00, BIT4 + BIT7}, |
| 314 | {0x04 + 3, 0xFD, BIT1}, |
| 315 | {0x74, 0xF6, BIT0 + BIT3}, |
| 316 | {0xF0, ~BIT2, 0x00}, |
| 317 | {0xF8, 0x00, 0x6C}, |
| 318 | {0xF8 + 1, 0x00, 0x27}, |
| 319 | {0xF8 + 2, 0x00, 0x00}, |
| 320 | {0xC4, 0xFE, 0x14}, |
| 321 | {0xC0 + 2, 0xBF, 0x40}, |
| 322 | {0xBE, 0xDD, BIT5}, |
| 323 | // HPET workaround |
| 324 | {0x54 + 3, 0xFC, BIT0 + BIT1}, |
| 325 | {0x54 + 2, 0x7F, BIT7}, |
| 326 | {0x54 + 2, 0x7F, 0x00}, |
| 327 | {0xC4, ~(BIT2 + BIT4), BIT2 + BIT4}, |
| 328 | {0xC0, 0, 0xF9}, |
| 329 | {0xC0 + 1, 0x04, 0x03}, |
| 330 | {0xC2, 0x20, 0x58}, |
| 331 | {0xC2 + 1, 0, 0x40}, |
| 332 | {0xC2, ~(BIT4), BIT4}, |
| 333 | {0x74, 0x00, BIT0 + BIT1 + BIT2 + BIT4}, |
| 334 | {0xDE + 1, ~(BIT0 + BIT1), BIT0 + BIT1}, |
| 335 | {0xDE, ~BIT4, BIT4}, |
| 336 | {0xBA, ~BIT3, BIT3}, |
| 337 | {0xBA + 1, ~BIT6, BIT6}, |
| 338 | {0xBC, ~BIT1, BIT1}, |
| 339 | {0xED, ~(BIT0 + BIT1), 0}, |
| 340 | {0xDC, 0x7C, BIT0}, |
Zheng Bao | d098575 | 2011-01-20 04:45:48 +0000 | [diff] [blame] | 341 | // {0xFF, 0xFF, 0xFF}, |
Zheng Bao | d098575 | 2011-01-20 04:45:48 +0000 | [diff] [blame] | 342 | }; |
| 343 | |
Zheng Bao | 79c04d5 | 2011-01-20 05:41:11 +0000 | [diff] [blame] | 344 | void sb800_lpc_port80(void) |
Zheng Bao | d098575 | 2011-01-20 04:45:48 +0000 | [diff] [blame] | 345 | { |
| 346 | u8 byte; |
| 347 | device_t dev; |
| 348 | |
| 349 | /* Enable LPC controller */ |
| 350 | byte = pmio_read(0xEC); |
| 351 | byte |= 1 << 0; |
| 352 | pmio_write(0xEC, byte); |
| 353 | |
| 354 | /* Enable port 80 LPC decode in pci function 3 configuration space. */ |
| 355 | dev = PCI_DEV(0, 0x14, 3);//pci_locate_device(PCI_ID(0x1002, 0x439D), 0); |
| 356 | byte = pci_read_config8(dev, 0x4a); |
| 357 | byte |= 1 << 5; /* enable port 80 */ |
| 358 | pci_write_config8(dev, 0x4a, byte); |
| 359 | } |
| 360 | |
| 361 | /* sbDevicesPorInitTable */ |
| 362 | static void sb800_devices_por_init(void) |
| 363 | { |
| 364 | device_t dev; |
| 365 | u8 byte; |
| 366 | |
| 367 | printk(BIOS_INFO, "sb800_devices_por_init()\n"); |
| 368 | /* SMBus Device, BDF:0-20-0 */ |
| 369 | printk(BIOS_INFO, "sb800_devices_por_init(): SMBus Device, BDF:0-20-0\n"); |
| 370 | dev = PCI_DEV(0, 0x14, 0);//pci_locate_device(PCI_ID(0x1002, 0x4385), 0); |
| 371 | |
| 372 | if (dev == PCI_DEV_INVALID) { |
| 373 | die("SMBUS controller not found\n"); |
| 374 | /* NOT REACHED */ |
| 375 | } |
| 376 | printk(BIOS_INFO, "SMBus controller enabled, sb revision is A%x\n", |
| 377 | get_sb800_revision()); |
| 378 | |
| 379 | /* sbPorAtStartOfTblCfg */ |
| 380 | /* rpr 4.1.Set A-Link bridge access address. |
Martin Roth | dcf253c | 2014-12-16 20:51:31 -0700 | [diff] [blame] | 381 | * This is an I/O address. The I/O address must be on 16-byte boundary. */ |
Zheng Bao | d098575 | 2011-01-20 04:45:48 +0000 | [diff] [blame] | 382 | //pci_write_config32(dev, 0xf0, AB_INDX); |
| 383 | pmio_write(0xE0, AB_INDX & 0xFF); |
| 384 | pmio_write(0xE1, (AB_INDX >> 8) & 0xFF); |
| 385 | pmio_write(0xE2, (AB_INDX >> 16) & 0xFF); |
| 386 | pmio_write(0xE3, (AB_INDX >> 24) & 0xFF); |
| 387 | |
| 388 | /* To enable AB/BIF DMA access, a specific register inside the BIF register space needs to be configured first. */ |
| 389 | /* 4.2:Enables the SB800 to send transactions upstream over A-Link Express interface. */ |
| 390 | axcfg_reg(0x04, 1 << 2, 1 << 2); |
| 391 | //axindxc_reg(0x21, 0xff, 0); |
| 392 | |
| 393 | /* 4.15:Enabling Non-Posted Memory Write for the K8 Platform */ |
| 394 | axindxc_reg(0x10, 1 << 9, 1 << 9); |
| 395 | /* END of sbPorAtStartOfTblCfg */ |
| 396 | |
| 397 | /* sbDevicesPorInitTables */ |
| 398 | /* set smbus iobase */ |
| 399 | //pci_write_config32(dev, 0x90, SMBUS_IO_BASE | 1); |
| 400 | /* The base address of SMBUS is set in a different way with sb700. */ |
| 401 | byte = (SMBUS_IO_BASE & 0xFF) | 1; |
| 402 | pmio_write(0x2c, byte & 0xFF); |
| 403 | pmio_write(0x2d, SMBUS_IO_BASE >> 8); |
| 404 | |
| 405 | /* AcpiMMioDecodeEn */ |
| 406 | byte = pmio_read(0x24); |
| 407 | byte |= 1; |
| 408 | byte &= ~(1 << 1); |
| 409 | pmio_write(0x24, byte); |
| 410 | /* enable smbus controller interface */ |
| 411 | //byte = pci_read_config8(dev, 0xd2); |
| 412 | //byte |= (1 << 0); |
| 413 | //pci_write_config8(dev, 0xd2, byte); |
| 414 | |
| 415 | /* KB2RstEnable */ |
| 416 | //pci_write_config8(dev, 0x40, 0x44); |
| 417 | |
| 418 | /* Enable ISA Address 0-960K decoding */ |
| 419 | //pci_write_config8(dev, 0x48, 0x0f); |
| 420 | |
| 421 | /* Enable ISA Address 0xC0000-0xDFFFF decode */ |
| 422 | //pci_write_config8(dev, 0x49, 0xff); |
| 423 | |
| 424 | /* Enable decode cycles to IO C50, C51, C52 GPM controls. */ |
| 425 | //byte = pci_read_config8(dev, 0x41); |
| 426 | //byte &= 0x80; |
| 427 | //byte |= 0x33; |
| 428 | //pci_write_config8(dev, 0x41, byte); |
| 429 | |
| 430 | /* Legacy DMA Prefetch Enhancement, CIM masked it. */ |
| 431 | /* pci_write_config8(dev, 0x43, 0x1); */ |
| 432 | |
| 433 | /* clear any lingering errors, so the transaction will run */ |
| 434 | outb(inb(SMBUS_IO_BASE + SMBHSTSTAT), SMBUS_IO_BASE + SMBHSTSTAT); |
| 435 | |
| 436 | /* IDE Device, BDF:0-20-1 */ |
| 437 | printk(BIOS_INFO, "sb800_devices_por_init(): IDE Device, BDF:0-20-1\n"); |
| 438 | dev = PCI_DEV(0, 0x14, 1);//pci_locate_device(PCI_ID(0x1002, 0x439C), 0); |
| 439 | /* Disable prefetch */ |
| 440 | byte = pci_read_config8(dev, 0x63); |
| 441 | byte |= 0x1; |
| 442 | pci_write_config8(dev, 0x63, byte); |
| 443 | |
| 444 | /* LPC Device, BDF:0-20-3 */ |
| 445 | printk(BIOS_INFO, "sb800_devices_por_init(): LPC Device, BDF:0-20-3\n"); |
| 446 | dev = PCI_DEV(0, 0x14, 3);//pci_locate_device(PCI_ID(0x1002, 0x439D), 0); |
| 447 | /* DMA enable */ |
| 448 | pci_write_config8(dev, 0x40, 0x04); |
| 449 | |
Rudolf Marek | 74ad66c | 2011-02-12 16:24:48 +0000 | [diff] [blame] | 450 | /* LPC Sync Timeout */ |
Zheng Bao | d098575 | 2011-01-20 04:45:48 +0000 | [diff] [blame] | 451 | pci_write_config8(dev, 0x49, 0xFF); |
Zheng Bao | d098575 | 2011-01-20 04:45:48 +0000 | [diff] [blame] | 452 | |
| 453 | /* Set LPC ROM size, it has been done in sb800_lpc_init(). |
| 454 | * enable LPC ROM range, 0xfff8: 512KB, 0xfff0: 1MB; |
| 455 | * enable LPC ROM range, 0xfff8: 512KB, 0xfff0: 1MB |
| 456 | * pci_write_config16(dev, 0x68, 0x000e) |
| 457 | * pci_write_config16(dev, 0x6c, 0xfff0);*/ |
| 458 | |
| 459 | /* Enable Tpm12_en and Tpm_legacy. I don't know what is its usage and copied from CIM. */ |
| 460 | pci_write_config8(dev, 0x7C, 0x05); |
| 461 | |
| 462 | /* P2P Bridge, BDF:0-20-4, the configuration of the registers in this dev are copied from CIM, |
| 463 | */ |
| 464 | printk(BIOS_INFO, "sb800_devices_por_init(): P2P Bridge, BDF:0-20-4\n"); |
| 465 | dev = PCI_DEV(0, 0x14, 4);//pci_locate_device(PCI_ID(0x1002, 0x4384), 0); |
| 466 | |
| 467 | /* Arbiter enable. */ |
| 468 | pci_write_config8(dev, 0x43, 0xff); |
| 469 | |
Martin Roth | dcf253c | 2014-12-16 20:51:31 -0700 | [diff] [blame] | 470 | /* Set PCDMA request into height priority list. */ |
Zheng Bao | d098575 | 2011-01-20 04:45:48 +0000 | [diff] [blame] | 471 | /* pci_write_config8(dev, 0x49, 0x1) */ ; |
| 472 | |
| 473 | pci_write_config8(dev, 0x40, 0x26); |
| 474 | |
| 475 | pci_write_config8(dev, 0x0d, 0x40); |
| 476 | pci_write_config8(dev, 0x1b, 0x40); |
| 477 | /* Enable PCIB_DUAL_EN_UP will fix potential problem with PCI cards. */ |
| 478 | pci_write_config8(dev, 0x50, 0x01); |
| 479 | |
| 480 | /* SATA Device, BDF:0-17-0, Non-Raid-5 SATA controller */ |
| 481 | printk(BIOS_INFO, "sb800_devices_por_init(): SATA Device, BDF:0-18-0\n"); |
| 482 | dev = PCI_DEV(0, 0x11, 0);//pci_locate_device(PCI_ID(0x1002, 0x4390), 0); |
| 483 | |
| 484 | /*PHY Global Control*/ |
| 485 | pci_write_config16(dev, 0x86, 0x2C00); |
| 486 | } |
| 487 | |
| 488 | /* sbPmioPorInitTable, Pre-initializing PMIO register space |
| 489 | * The power management (PM) block is resident in the PCI/LPC/ISA bridge. |
| 490 | * The PM regs are accessed via IO mapped regs 0xcd6 and 0xcd7. |
| 491 | * The index address is first programmed into IO reg 0xcd6. |
| 492 | * Read or write values are accessed through IO reg 0xcd7. |
| 493 | */ |
| 494 | #if 0 |
| 495 | static void sb800_pmio_por_init(void) |
| 496 | { |
| 497 | u8 byte, i; |
| 498 | |
| 499 | printk(BIOS_INFO, "sb800_pmio_por_init()\n"); |
| 500 | |
| 501 | byte = pmio_read(0xD2); |
| 502 | byte |= 3 << 4; |
| 503 | pmio_write(0xD2, byte); |
| 504 | |
| 505 | byte = pmio_read(0x5D); |
| 506 | byte &= 3; |
| 507 | byte |= 1; |
| 508 | pmio_write(0x5D, byte); |
| 509 | |
| 510 | /* Watch Dog Timer Control |
| 511 | * Set watchdog time base to 0xfec000f0 to avoid SCSI card boot failure. |
| 512 | * But I don't find WDT is enabled in SMBUS 0x41 bit3 in CIM. |
| 513 | */ |
| 514 | pmio_write(0x6c, 0xf0); |
| 515 | pmio_write(0x6d, 0x00); |
| 516 | pmio_write(0x6e, 0xc0); |
| 517 | pmio_write(0x6f, 0xfe); |
| 518 | |
| 519 | /* rpr2.15: Enabling Spread Spectrum */ |
| 520 | byte = pmio_read(0x42); |
| 521 | byte |= 1 << 7; |
| 522 | pmio_write(0x42, byte); |
| 523 | /* TODO: Check if it is necessary. IDE reset */ |
| 524 | byte = pmio_read(0xB2); |
| 525 | byte |= 1 << 0; |
| 526 | pmio_write(0xB2, byte); |
| 527 | |
| 528 | for (i=0; i<sizeof(pm_table)/sizeof(struct pm_entry); i++) { |
| 529 | byte = pmio_read(pm_table[i].port); |
| 530 | byte &= pm_table[i].mask; |
| 531 | byte |= pm_table[i].bit; |
| 532 | pmio_write(pm_table[i].port, byte); |
| 533 | } |
| 534 | pmio_write(0x00, 0x0E); |
| 535 | pmio_write(0x01, 0x00); |
| 536 | pmio_write(0x02, 0x4F); |
| 537 | pmio_write(0x03, 0x4A); |
| 538 | } |
| 539 | #endif |
| 540 | |
| 541 | /* |
| 542 | * Add any south bridge setting. |
| 543 | */ |
| 544 | static void sb800_pci_cfg(void) |
| 545 | { |
| 546 | device_t dev; |
| 547 | u8 byte; |
| 548 | |
| 549 | /* SMBus Device, BDF:0-20-0 */ |
| 550 | dev = PCI_DEV(0, 0x14, 0);//pci_locate_device(PCI_ID(0x1002, 0x4385), 0); |
| 551 | /* Enable watchdog decode timer */ |
| 552 | byte = pci_read_config8(dev, 0x41); |
| 553 | byte |= (1 << 3); |
| 554 | pci_write_config8(dev, 0x41, byte); |
| 555 | |
Zheng Bao | 72cc87f | 2011-01-21 08:46:27 +0000 | [diff] [blame] | 556 | /* rpr 7.4. Set to 1 to reset USB on the software (such as IO-64 or IO-CF9 cycles) |
Zheng Bao | d098575 | 2011-01-20 04:45:48 +0000 | [diff] [blame] | 557 | * generated PCIRST#. */ |
Zheng Bao | 72cc87f | 2011-01-21 08:46:27 +0000 | [diff] [blame] | 558 | byte = pmio_read(0xF0); |
| 559 | byte |= (1 << 2); |
| 560 | pmio_write(0xF0, byte); |
Zheng Bao | d098575 | 2011-01-20 04:45:48 +0000 | [diff] [blame] | 561 | |
| 562 | /* IDE Device, BDF:0-20-1 */ |
| 563 | dev = PCI_DEV(0, 0x14, 1);//pci_locate_device(PCI_ID(0x1002, 0x439C), 0); |
| 564 | /* Enable IDE Explicit prefetch, 0x63[0] clear */ |
| 565 | byte = pci_read_config8(dev, 0x63); |
| 566 | byte &= 0xfe; |
| 567 | pci_write_config8(dev, 0x63, byte); |
| 568 | |
| 569 | /* LPC Device, BDF:0-20-3 */ |
| 570 | /* The code below is ported from old chipset. It is not |
Martin Roth | dcf253c | 2014-12-16 20:51:31 -0700 | [diff] [blame] | 571 | * Mentioned in RPR. But I keep them. The registers and the |
Zheng Bao | d098575 | 2011-01-20 04:45:48 +0000 | [diff] [blame] | 572 | * comments are compatible. */ |
| 573 | dev = PCI_DEV(0, 0x14, 3);//pci_locate_device(PCI_ID(0x1002, 0x439D), 0); |
| 574 | /* Enabling LPC DMA function. */ |
| 575 | byte = pci_read_config8(dev, 0x40); |
| 576 | byte |= (1 << 2); |
| 577 | pci_write_config8(dev, 0x40, byte); |
| 578 | /* Disabling LPC TimeOut. 0x48[7] clear. */ |
| 579 | byte = pci_read_config8(dev, 0x48); |
| 580 | byte &= 0x7f; |
| 581 | pci_write_config8(dev, 0x48, byte); |
| 582 | /* Disabling LPC MSI Capability, 0x78[1] clear. */ |
| 583 | byte = pci_read_config8(dev, 0x78); |
| 584 | byte &= 0xfd; |
| 585 | pci_write_config8(dev, 0x78, byte); |
| 586 | |
| 587 | /* SATA Device, BDF:0-17-0, Non-Raid-5 SATA controller */ |
| 588 | dev = PCI_DEV(0, 0x11, 0);//pci_locate_device(PCI_ID(0x1002, 0x4390), 0); |
| 589 | /* rpr7.12 SATA MSI and D3 Power State Capability. */ |
| 590 | byte = pci_read_config8(dev, 0x40); |
| 591 | byte |= 1 << 0; |
| 592 | pci_write_config8(dev, 0x40, byte); |
| 593 | if (get_sb800_revision() <= 0x12) |
| 594 | pci_write_config8(dev, 0x34, 0x70); /* set 0x61 to 0x70 if S1 is not supported. */ |
| 595 | else |
| 596 | pci_write_config8(dev, 0x34, 0x50); /* set 0x61 to 0x50 if S1 is not supported. */ |
| 597 | byte &= ~(1 << 0); |
| 598 | pci_write_config8(dev, 0x40, byte); |
| 599 | } |
| 600 | |
| 601 | /* |
| 602 | */ |
| 603 | static void sb800_por_init(void) |
| 604 | { |
| 605 | /* sbDevicesPorInitTable + sbK8PorInitTable */ |
| 606 | sb800_devices_por_init(); |
| 607 | |
| 608 | /* sbPmioPorInitTable + sbK8PmioPorInitTable */ |
| 609 | //sb800_pmio_por_init(); |
| 610 | } |
| 611 | |
| 612 | /* |
| 613 | * It should be called during early POST after memory detection and BIOS shadowing but before PCI bus enumeration. |
| 614 | */ |
| 615 | static void sb800_before_pci_init(void) |
| 616 | { |
| 617 | sb800_pci_cfg(); |
| 618 | } |
| 619 | |
| 620 | /* |
| 621 | * This function should be called after enable_sb800_smbus(). |
| 622 | */ |
| 623 | static void sb800_early_setup(void) |
| 624 | { |
| 625 | printk(BIOS_INFO, "sb800_early_setup()\n"); |
| 626 | sb800_por_init(); |
| 627 | sb800_acpi_init(); |
| 628 | } |
| 629 | |
| 630 | static int smbus_read_byte(u32 device, u32 address) |
| 631 | { |
| 632 | return do_smbus_read_byte(SMBUS_IO_BASE, device, address); |
| 633 | } |
Zheng Bao | a4da254 | 2011-01-20 05:59:22 +0000 | [diff] [blame] | 634 | |
Zheng Bao | a5c949e | 2011-01-27 03:31:50 +0000 | [diff] [blame] | 635 | int s3_save_nvram_early(u32 dword, int size, int nvram_pos) |
| 636 | { |
Zheng Bao | a4da254 | 2011-01-20 05:59:22 +0000 | [diff] [blame] | 637 | int i; |
| 638 | printk(BIOS_DEBUG, "Writing %x of size %d to nvram pos: %d\n", dword, size, nvram_pos); |
| 639 | |
| 640 | for (i = 0; i<size; i++) { |
| 641 | outb(nvram_pos, BIOSRAM_INDEX); |
| 642 | outb((dword >>(8 * i)) & 0xff , BIOSRAM_DATA); |
| 643 | nvram_pos++; |
| 644 | } |
| 645 | |
| 646 | return nvram_pos; |
| 647 | } |
| 648 | |
Zheng Bao | a5c949e | 2011-01-27 03:31:50 +0000 | [diff] [blame] | 649 | int s3_load_nvram_early(int size, u32 *old_dword, int nvram_pos) |
| 650 | { |
Zheng Bao | a4da254 | 2011-01-20 05:59:22 +0000 | [diff] [blame] | 651 | u32 data = *old_dword; |
| 652 | int i; |
| 653 | for (i = 0; i<size; i++) { |
| 654 | outb(nvram_pos, BIOSRAM_INDEX); |
| 655 | data &= ~(0xff << (i * 8)); |
| 656 | data |= inb(BIOSRAM_DATA) << (i *8); |
| 657 | nvram_pos++; |
| 658 | } |
| 659 | *old_dword = data; |
| 660 | printk(BIOS_DEBUG, "Loading %x of size %d to nvram pos:%d\n", *old_dword, size, |
| 661 | nvram_pos-size); |
| 662 | return nvram_pos; |
| 663 | } |
| 664 | |
Kyösti Mälkki | 78c5d58 | 2015-01-09 23:48:47 +0200 | [diff] [blame] | 665 | int acpi_get_sleep_type(void) |
Zheng Bao | a5c949e | 2011-01-27 03:31:50 +0000 | [diff] [blame] | 666 | { |
Zheng Bao | a4da254 | 2011-01-20 05:59:22 +0000 | [diff] [blame] | 667 | u16 tmp; |
| 668 | tmp = inw(ACPI_PM1_CNT_BLK); |
Kyösti Mälkki | 78c5d58 | 2015-01-09 23:48:47 +0200 | [diff] [blame] | 669 | return ((tmp & (7 << 10)) >> 10); |
Zheng Bao | a4da254 | 2011-01-20 05:59:22 +0000 | [diff] [blame] | 670 | } |
Zheng Bao | a4da254 | 2011-01-20 05:59:22 +0000 | [diff] [blame] | 671 | |
Kyösti Mälkki | 4da487e | 2015-03-19 06:58:15 +0200 | [diff] [blame] | 672 | #if IS_ENABLED(CONFIG_LATE_CBMEM_INIT) |
Kyösti Mälkki | bc90e15 | 2013-09-04 13:26:11 +0300 | [diff] [blame] | 673 | unsigned long get_top_of_ram(void) |
Zheng Bao | a5c949e | 2011-01-27 03:31:50 +0000 | [diff] [blame] | 674 | { |
Zheng Bao | a4da254 | 2011-01-20 05:59:22 +0000 | [diff] [blame] | 675 | uint32_t xdata = 0; |
| 676 | int xnvram_pos = 0xfc, xi; |
Kyösti Mälkki | 78c5d58 | 2015-01-09 23:48:47 +0200 | [diff] [blame] | 677 | if (acpi_get_sleep_type() != 3) |
Kyösti Mälkki | bc90e15 | 2013-09-04 13:26:11 +0300 | [diff] [blame] | 678 | return 0; |
Zheng Bao | a4da254 | 2011-01-20 05:59:22 +0000 | [diff] [blame] | 679 | for (xi = 0; xi<4; xi++) { |
| 680 | outb(xnvram_pos, BIOSRAM_INDEX); |
| 681 | xdata &= ~(0xff << (xi * 8)); |
| 682 | xdata |= inb(BIOSRAM_DATA) << (xi *8); |
| 683 | xnvram_pos++; |
| 684 | } |
Kyösti Mälkki | bc90e15 | 2013-09-04 13:26:11 +0300 | [diff] [blame] | 685 | return (unsigned long) xdata; |
Zheng Bao | a4da254 | 2011-01-20 05:59:22 +0000 | [diff] [blame] | 686 | } |
Kyösti Mälkki | 4da487e | 2015-03-19 06:58:15 +0200 | [diff] [blame] | 687 | #endif |
Zheng Bao | a4da254 | 2011-01-20 05:59:22 +0000 | [diff] [blame] | 688 | |
Zheng Bao | d098575 | 2011-01-20 04:45:48 +0000 | [diff] [blame] | 689 | #endif |