blob: beb35d11b1fd2643c1c09928970b759d6d82cbc8 [file] [log] [blame]
Michael Xie7586cef2008-09-22 13:11:39 +00001/*
2 * This file is part of the coreboot project.
3 *
4 * Copyright (C) 2008 Advanced Micro Devices, Inc.
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; version 2 of the License.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
Michael Xie7586cef2008-09-22 13:11:39 +000014 */
15
Kyösti Mälkkief844012013-06-25 23:17:43 +030016// Use simple device model for this file even in ramstage
17#define __SIMPLE_DEVICE__
18
Michael Xie7586cef2008-09-22 13:11:39 +000019#include <arch/io.h>
Stefan Reinauer6a445e82010-04-09 11:34:59 +000020#include <reset.h>
Michael Xie7586cef2008-09-22 13:11:39 +000021
Stefan Reinauer24d1d4b2013-03-21 11:51:41 -070022#include <northbridge/amd/amdk8/reset_test.c>
Michael Xie7586cef2008-09-22 13:11:39 +000023
24void hard_reset(void)
25{
26 set_bios_reset();
27 /* Try rebooting through port 0xcf9 */
28 /* Actually it is not a real hard_reset --- it only reset coherent link table, but not reset link freq and width */
29 outb((0 << 3) | (0 << 2) | (1 << 1), 0xcf9);
30 outb((0 << 3) | (1 << 2) | (1 << 1), 0xcf9);
31}