Michael Xie | 7586cef | 2008-09-22 13:11:39 +0000 | [diff] [blame] | 1 | /* |
| 2 | * This file is part of the coreboot project. |
| 3 | * |
| 4 | * Copyright (C) 2008 Advanced Micro Devices, Inc. |
| 5 | * |
| 6 | * This program is free software; you can redistribute it and/or modify |
| 7 | * it under the terms of the GNU General Public License as published by |
| 8 | * the Free Software Foundation; version 2 of the License. |
| 9 | * |
| 10 | * This program is distributed in the hope that it will be useful, |
| 11 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 12 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 13 | * GNU General Public License for more details. |
Michael Xie | 7586cef | 2008-09-22 13:11:39 +0000 | [diff] [blame] | 14 | */ |
| 15 | |
Stefan Reinauer | 94c27b3 | 2010-04-16 01:14:50 +0000 | [diff] [blame] | 16 | #include <reset.h> |
Michael Xie | 7586cef | 2008-09-22 13:11:39 +0000 | [diff] [blame] | 17 | #include <arch/cpu.h> |
Uwe Hermann | 039255c | 2008-10-21 16:27:38 +0000 | [diff] [blame] | 18 | #include "sb600.h" |
stepan | 836ae29 | 2010-12-08 05:42:47 +0000 | [diff] [blame] | 19 | #include "smbus.c" |
Michael Xie | 7586cef | 2008-09-22 13:11:39 +0000 | [diff] [blame] | 20 | |
| 21 | #define SMBUS_IO_BASE 0x1000 /* Is it a temporary SMBus I/O base address? */ |
| 22 | /*SIZE 0x40 */ |
| 23 | |
Michael Xie | 7586cef | 2008-09-22 13:11:39 +0000 | [diff] [blame] | 24 | static void pmio_write(u8 reg, u8 value) |
| 25 | { |
Uwe Hermann | 039255c | 2008-10-21 16:27:38 +0000 | [diff] [blame] | 26 | outb(reg, PM_INDEX); |
| 27 | outb(value, PM_INDEX + 1); |
Michael Xie | 7586cef | 2008-09-22 13:11:39 +0000 | [diff] [blame] | 28 | } |
| 29 | |
| 30 | static u8 pmio_read(u8 reg) |
| 31 | { |
Uwe Hermann | 039255c | 2008-10-21 16:27:38 +0000 | [diff] [blame] | 32 | outb(reg, PM_INDEX); |
| 33 | return inb(PM_INDEX + 1); |
Michael Xie | 7586cef | 2008-09-22 13:11:39 +0000 | [diff] [blame] | 34 | } |
| 35 | |
Uwe Hermann | ff492b1 | 2010-09-24 23:37:25 +0000 | [diff] [blame] | 36 | /* RPR 2.1: Get SB ASIC Revision. */ |
Stefan Reinauer | 3839a8e | 2009-07-14 19:10:10 +0000 | [diff] [blame] | 37 | static u8 get_sb600_revision(void) |
Michael Xie | 7586cef | 2008-09-22 13:11:39 +0000 | [diff] [blame] | 38 | { |
| 39 | device_t dev; |
| 40 | dev = pci_locate_device(PCI_ID(0x1002, 0x4385), 0); |
| 41 | |
| 42 | if (dev == PCI_DEV_INVALID) { |
Stefan Reinauer | 64ed2b7 | 2010-03-31 14:47:43 +0000 | [diff] [blame] | 43 | die("SMBUS controller not found\n"); |
Joe Bao | 164463c | 2008-12-01 19:37:21 +0000 | [diff] [blame] | 44 | /* NOT REACHED */ |
Michael Xie | 7586cef | 2008-09-22 13:11:39 +0000 | [diff] [blame] | 45 | } |
| 46 | return pci_read_config8(dev, 0x08); |
| 47 | } |
| 48 | |
| 49 | |
| 50 | /*************************************** |
| 51 | * Legacy devices are mapped to LPC space. |
Patrick Georgi | 390a337 | 2011-10-07 14:43:27 +0200 | [diff] [blame] | 52 | * Serial port 0, 1 |
Michael Xie | 7586cef | 2008-09-22 13:11:39 +0000 | [diff] [blame] | 53 | * KBC Port |
| 54 | * ACPI Micro-controller port |
Carl-Daniel Hailfinger | 42f03e5 | 2008-12-12 03:40:21 +0000 | [diff] [blame] | 55 | * This function does not change port 0x80 decoding. |
Patrick Georgi | 390a337 | 2011-10-07 14:43:27 +0200 | [diff] [blame] | 56 | * Console output through any port besides 0x2f8/0x3f8 is unsupported. |
Carl-Daniel Hailfinger | 42f03e5 | 2008-12-12 03:40:21 +0000 | [diff] [blame] | 57 | * If you use FWH ROMs, you have to setup IDSEL. |
Carl-Daniel Hailfinger | 42f03e5 | 2008-12-12 03:40:21 +0000 | [diff] [blame] | 58 | * Reviewed-by: Carl-Daniel Hailfinger |
| 59 | * Reviewed against AMD SB600 Register Reference Manual rev. 3.03, section 3.1 |
| 60 | * (LPC ISA Bridge) |
Michael Xie | 7586cef | 2008-09-22 13:11:39 +0000 | [diff] [blame] | 61 | ***************************************/ |
| 62 | static void sb600_lpc_init(void) |
| 63 | { |
| 64 | u8 reg8; |
| 65 | u32 reg32; |
| 66 | device_t dev; |
| 67 | |
Michael Xie | 7586cef | 2008-09-22 13:11:39 +0000 | [diff] [blame] | 68 | dev = pci_locate_device(PCI_ID(0x1002, 0x4385), 0); /* SMBUS controller */ |
Zheng Bao | d4e77df | 2010-03-17 03:10:39 +0000 | [diff] [blame] | 69 | /* NOTE: Set BootTimerDisable, otherwise it would keep rebooting!! |
| 70 | * This bit has no meaning if debug strap is not enabled. So if the |
| 71 | * board keeps rebooting and the code fails to reach here, we could |
| 72 | * disable the debug strap first. */ |
| 73 | reg32 = pci_read_config32(dev, 0x4C); |
| 74 | reg32 |= 1 << 31; |
| 75 | pci_write_config32(dev, 0x4C, reg32); |
| 76 | |
| 77 | /* Enable lpc controller */ |
Michael Xie | 7586cef | 2008-09-22 13:11:39 +0000 | [diff] [blame] | 78 | reg32 = pci_read_config32(dev, 0x64); |
Carl-Daniel Hailfinger | 42f03e5 | 2008-12-12 03:40:21 +0000 | [diff] [blame] | 79 | reg32 |= 1 << 20; |
Michael Xie | 7586cef | 2008-09-22 13:11:39 +0000 | [diff] [blame] | 80 | pci_write_config32(dev, 0x64, reg32); |
| 81 | |
| 82 | dev = pci_locate_device(PCI_ID(0x1002, 0x438d), 0); /* LPC Controller */ |
Patrick Georgi | 390a337 | 2011-10-07 14:43:27 +0200 | [diff] [blame] | 83 | /* Decode port 0x3f8-0x3ff (Serial 0), 0x2f8-0x2ff (Serial 1) */ |
Michael Xie | 7586cef | 2008-09-22 13:11:39 +0000 | [diff] [blame] | 84 | reg8 = pci_read_config8(dev, 0x44); |
Patrick Georgi | 390a337 | 2011-10-07 14:43:27 +0200 | [diff] [blame] | 85 | reg8 |= (1 << 6) | (1 << 7); |
Michael Xie | 7586cef | 2008-09-22 13:11:39 +0000 | [diff] [blame] | 86 | pci_write_config8(dev, 0x44, reg8); |
| 87 | |
Carl-Daniel Hailfinger | 42f03e5 | 2008-12-12 03:40:21 +0000 | [diff] [blame] | 88 | /* Decode port 0x60 & 0x64 (PS/2 keyboard) and port 0x62 & 0x66 (ACPI)*/ |
Michael Xie | 7586cef | 2008-09-22 13:11:39 +0000 | [diff] [blame] | 89 | reg8 = pci_read_config8(dev, 0x47); |
| 90 | reg8 |= (1 << 5) | (1 << 6); |
| 91 | pci_write_config8(dev, 0x47, reg8); |
| 92 | |
Uwe Hermann | e89d8a5 | 2010-11-26 22:39:40 +0000 | [diff] [blame] | 93 | /* Super I/O, RTC */ |
Michael Xie | 7586cef | 2008-09-22 13:11:39 +0000 | [diff] [blame] | 94 | reg8 = pci_read_config8(dev, 0x48); |
Carl-Daniel Hailfinger | 42f03e5 | 2008-12-12 03:40:21 +0000 | [diff] [blame] | 95 | /* Decode ports 0x2e-0x2f, 0x4e-0x4f (SuperI/O configuration) */ |
| 96 | reg8 |= (1 << 1) | (1 << 0); |
Carl-Daniel Hailfinger | 42f03e5 | 2008-12-12 03:40:21 +0000 | [diff] [blame] | 97 | /* Decode port 0x70-0x73 (RTC) */ |
Uwe Hermann | e89d8a5 | 2010-11-26 22:39:40 +0000 | [diff] [blame] | 98 | reg8 |= (1 << 6); |
Michael Xie | 7586cef | 2008-09-22 13:11:39 +0000 | [diff] [blame] | 99 | pci_write_config8(dev, 0x48, reg8); |
Michael Xie | 7586cef | 2008-09-22 13:11:39 +0000 | [diff] [blame] | 100 | } |
| 101 | |
| 102 | /* what is its usage? */ |
| 103 | static u32 get_sbdn(u32 bus) |
| 104 | { |
| 105 | device_t dev; |
| 106 | |
| 107 | /* Find the device. */ |
| 108 | dev = pci_locate_device_on_bus(PCI_ID(0x1002, 0x4385), bus); |
| 109 | return (dev >> 15) & 0x1f; |
| 110 | } |
| 111 | |
Stefan Reinauer | 3839a8e | 2009-07-14 19:10:10 +0000 | [diff] [blame] | 112 | static u8 dual_core(void) |
Michael Xie | 7586cef | 2008-09-22 13:11:39 +0000 | [diff] [blame] | 113 | { |
Zheng Bao | 7d4fd2c | 2009-07-10 03:42:13 +0000 | [diff] [blame] | 114 | return (pci_read_config32(PCI_DEV(0, 0x18, 3), 0xE8) & (0x3<<12)) != 0; |
Michael Xie | 7586cef | 2008-09-22 13:11:39 +0000 | [diff] [blame] | 115 | } |
| 116 | |
| 117 | /* |
Uwe Hermann | ff492b1 | 2010-09-24 23:37:25 +0000 | [diff] [blame] | 118 | * SB600 VFSMAF (VID/FID System Management Action Field) is 010b by default. |
| 119 | * RPR 2.3.3 C-state and VID/FID change for the K8 platform. |
Michael Xie | 7586cef | 2008-09-22 13:11:39 +0000 | [diff] [blame] | 120 | */ |
| 121 | static void enable_fid_change_on_sb(u32 sbbusn, u32 sbdn) |
| 122 | { |
| 123 | u8 byte; |
| 124 | byte = pmio_read(0x9a); |
| 125 | byte &= ~0x34; |
Uwe Hermann | ff492b1 | 2010-09-24 23:37:25 +0000 | [diff] [blame] | 126 | if (dual_core()) |
Michael Xie | 7586cef | 2008-09-22 13:11:39 +0000 | [diff] [blame] | 127 | byte |= 0x34; |
| 128 | else |
| 129 | byte |= 0x04; |
| 130 | pmio_write(0x9a, byte); |
| 131 | |
| 132 | byte = pmio_read(0x8f); |
| 133 | byte &= ~0x30; |
| 134 | byte |= 0x20; |
| 135 | pmio_write(0x8f, byte); |
| 136 | |
| 137 | pmio_write(0x8b, 0x01); |
| 138 | pmio_write(0x8a, 0x90); |
| 139 | |
| 140 | if(get_sb600_revision() > 0x13) |
| 141 | pmio_write(0x88, 0x10); |
| 142 | else |
| 143 | pmio_write(0x88, 0x06); |
| 144 | |
| 145 | byte = pmio_read(0x7c); |
| 146 | byte &= ~0x01; |
| 147 | byte |= 0x01; |
| 148 | pmio_write(0x7c, byte); |
| 149 | |
Uwe Hermann | ff492b1 | 2010-09-24 23:37:25 +0000 | [diff] [blame] | 150 | /* Must be 0 for K8 platform. */ |
Michael Xie | 7586cef | 2008-09-22 13:11:39 +0000 | [diff] [blame] | 151 | byte = pmio_read(0x68); |
| 152 | byte &= ~0x01; |
| 153 | pmio_write(0x68, byte); |
Uwe Hermann | ff492b1 | 2010-09-24 23:37:25 +0000 | [diff] [blame] | 154 | /* Must be 0 for K8 platform. */ |
Michael Xie | 7586cef | 2008-09-22 13:11:39 +0000 | [diff] [blame] | 155 | byte = pmio_read(0x8d); |
| 156 | byte &= ~(1<<6); |
| 157 | pmio_write(0x8d, byte); |
| 158 | |
| 159 | byte = pmio_read(0x61); |
| 160 | byte &= ~0x04; |
| 161 | pmio_write(0x61, byte); |
| 162 | |
| 163 | byte = pmio_read(0x42); |
| 164 | byte &= ~0x04; |
| 165 | pmio_write(0x42, byte); |
| 166 | |
Uwe Hermann | ff492b1 | 2010-09-24 23:37:25 +0000 | [diff] [blame] | 167 | if (get_sb600_revision() == 0x14) { |
Michael Xie | 7586cef | 2008-09-22 13:11:39 +0000 | [diff] [blame] | 168 | pmio_write(0x89, 0x10); |
| 169 | |
| 170 | byte = pmio_read(0x52); |
| 171 | byte |= 0x80; |
| 172 | pmio_write(0x52, byte); |
| 173 | } |
| 174 | } |
| 175 | |
Stefan Reinauer | 94c27b3 | 2010-04-16 01:14:50 +0000 | [diff] [blame] | 176 | void hard_reset(void) |
Michael Xie | 7586cef | 2008-09-22 13:11:39 +0000 | [diff] [blame] | 177 | { |
| 178 | set_bios_reset(); |
| 179 | |
| 180 | /* full reset */ |
| 181 | outb(0x0a, 0x0cf9); |
| 182 | outb(0x0e, 0x0cf9); |
| 183 | } |
| 184 | |
Stefan Reinauer | 94c27b3 | 2010-04-16 01:14:50 +0000 | [diff] [blame] | 185 | void soft_reset(void) |
Michael Xie | 7586cef | 2008-09-22 13:11:39 +0000 | [diff] [blame] | 186 | { |
| 187 | set_bios_reset(); |
| 188 | /* link reset */ |
| 189 | outb(0x06, 0x0cf9); |
| 190 | } |
| 191 | |
Stefan Reinauer | c8873ce | 2010-04-30 19:21:01 +0000 | [diff] [blame] | 192 | void sb600_pci_port80(void) |
Michael Xie | 7586cef | 2008-09-22 13:11:39 +0000 | [diff] [blame] | 193 | { |
| 194 | u8 byte; |
| 195 | device_t dev; |
| 196 | |
| 197 | /* P2P Bridge */ |
| 198 | dev = pci_locate_device(PCI_ID(0x1002, 0x4384), 0); |
| 199 | |
Carl-Daniel Hailfinger | 42f03e5 | 2008-12-12 03:40:21 +0000 | [diff] [blame] | 200 | /* Chip Control: Enable subtractive decoding */ |
Michael Xie | 7586cef | 2008-09-22 13:11:39 +0000 | [diff] [blame] | 201 | byte = pci_read_config8(dev, 0x40); |
| 202 | byte |= 1 << 5; |
| 203 | pci_write_config8(dev, 0x40, byte); |
| 204 | |
Carl-Daniel Hailfinger | 42f03e5 | 2008-12-12 03:40:21 +0000 | [diff] [blame] | 205 | /* Misc Control: Enable subtractive decoding if 0x40 bit 5 is set */ |
Michael Xie | 7586cef | 2008-09-22 13:11:39 +0000 | [diff] [blame] | 206 | byte = pci_read_config8(dev, 0x4B); |
| 207 | byte |= 1 << 7; |
| 208 | pci_write_config8(dev, 0x4B, byte); |
| 209 | |
Carl-Daniel Hailfinger | 42f03e5 | 2008-12-12 03:40:21 +0000 | [diff] [blame] | 210 | /* The same IO Base and IO Limit here is meaningful because we set the |
| 211 | * bridge to be subtractive. During early setup stage, we have to make |
| 212 | * sure that data can go through port 0x80. |
| 213 | */ |
| 214 | /* IO Base: 0xf000 */ |
Michael Xie | 7586cef | 2008-09-22 13:11:39 +0000 | [diff] [blame] | 215 | byte = pci_read_config8(dev, 0x1C); |
| 216 | byte |= 0xF << 4; |
| 217 | pci_write_config8(dev, 0x1C, byte); |
| 218 | |
Carl-Daniel Hailfinger | 42f03e5 | 2008-12-12 03:40:21 +0000 | [diff] [blame] | 219 | /* IO Limit: 0xf000 */ |
Michael Xie | 7586cef | 2008-09-22 13:11:39 +0000 | [diff] [blame] | 220 | byte = pci_read_config8(dev, 0x1D); |
| 221 | byte |= 0xF << 4; |
| 222 | pci_write_config8(dev, 0x1D, byte); |
| 223 | |
Carl-Daniel Hailfinger | 42f03e5 | 2008-12-12 03:40:21 +0000 | [diff] [blame] | 224 | /* PCI Command: Enable IO response */ |
Michael Xie | 7586cef | 2008-09-22 13:11:39 +0000 | [diff] [blame] | 225 | byte = pci_read_config8(dev, 0x04); |
| 226 | byte |= 1 << 0; |
| 227 | pci_write_config8(dev, 0x04, byte); |
| 228 | |
Carl-Daniel Hailfinger | 42f03e5 | 2008-12-12 03:40:21 +0000 | [diff] [blame] | 229 | /* LPC controller */ |
Michael Xie | 7586cef | 2008-09-22 13:11:39 +0000 | [diff] [blame] | 230 | dev = pci_locate_device(PCI_ID(0x1002, 0x438D), 0); |
| 231 | |
| 232 | byte = pci_read_config8(dev, 0x4A); |
| 233 | byte &= ~(1 << 5); /* disable lpc port 80 */ |
| 234 | pci_write_config8(dev, 0x4A, byte); |
| 235 | } |
| 236 | |
Stefan Reinauer | c8873ce | 2010-04-30 19:21:01 +0000 | [diff] [blame] | 237 | void sb600_lpc_port80(void) |
Michael Xie | 7586cef | 2008-09-22 13:11:39 +0000 | [diff] [blame] | 238 | { |
| 239 | u8 byte; |
| 240 | device_t dev; |
| 241 | u32 reg32; |
| 242 | |
Carl-Daniel Hailfinger | 42f03e5 | 2008-12-12 03:40:21 +0000 | [diff] [blame] | 243 | /* Enable LPC controller */ |
Michael Xie | 7586cef | 2008-09-22 13:11:39 +0000 | [diff] [blame] | 244 | dev = pci_locate_device(PCI_ID(0x1002, 0x4385), 0); |
| 245 | reg32 = pci_read_config32(dev, 0x64); |
| 246 | reg32 |= 0x00100000; /* lpcEnable */ |
| 247 | pci_write_config32(dev, 0x64, reg32); |
| 248 | |
Carl-Daniel Hailfinger | 42f03e5 | 2008-12-12 03:40:21 +0000 | [diff] [blame] | 249 | /* Enable port 80 LPC decode in pci function 3 configuration space. */ |
Michael Xie | 7586cef | 2008-09-22 13:11:39 +0000 | [diff] [blame] | 250 | dev = pci_locate_device(PCI_ID(0x1002, 0x438d), 0); |
| 251 | byte = pci_read_config8(dev, 0x4a); |
| 252 | byte |= 1 << 5; /* enable port 80 */ |
| 253 | pci_write_config8(dev, 0x4a, byte); |
| 254 | } |
| 255 | |
Michael Xie | 7586cef | 2008-09-22 13:11:39 +0000 | [diff] [blame] | 256 | /* sbDevicesPorInitTable */ |
Stefan Reinauer | 3839a8e | 2009-07-14 19:10:10 +0000 | [diff] [blame] | 257 | static void sb600_devices_por_init(void) |
Michael Xie | 7586cef | 2008-09-22 13:11:39 +0000 | [diff] [blame] | 258 | { |
| 259 | device_t dev; |
| 260 | u8 byte; |
| 261 | |
Stefan Reinauer | c02b4fc | 2010-03-22 11:42:32 +0000 | [diff] [blame] | 262 | printk(BIOS_INFO, "sb600_devices_por_init()\n"); |
Michael Xie | 7586cef | 2008-09-22 13:11:39 +0000 | [diff] [blame] | 263 | /* SMBus Device, BDF:0-20-0 */ |
Stefan Reinauer | c02b4fc | 2010-03-22 11:42:32 +0000 | [diff] [blame] | 264 | printk(BIOS_INFO, "sb600_devices_por_init(): SMBus Device, BDF:0-20-0\n"); |
Michael Xie | 7586cef | 2008-09-22 13:11:39 +0000 | [diff] [blame] | 265 | dev = pci_locate_device(PCI_ID(0x1002, 0x4385), 0); |
| 266 | |
| 267 | if (dev == PCI_DEV_INVALID) { |
Stefan Reinauer | 64ed2b7 | 2010-03-31 14:47:43 +0000 | [diff] [blame] | 268 | die("SMBUS controller not found\n"); |
Joe Bao | 164463c | 2008-12-01 19:37:21 +0000 | [diff] [blame] | 269 | /* NOT REACHED */ |
Michael Xie | 7586cef | 2008-09-22 13:11:39 +0000 | [diff] [blame] | 270 | } |
Stefan Reinauer | 64ed2b7 | 2010-03-31 14:47:43 +0000 | [diff] [blame] | 271 | printk(BIOS_INFO, "SMBus controller enabled, sb revision is 0x%x\n", |
Michael Xie | 7586cef | 2008-09-22 13:11:39 +0000 | [diff] [blame] | 272 | get_sb600_revision()); |
| 273 | |
| 274 | /* sbPorAtStartOfTblCfg */ |
| 275 | /* Set A-Link bridge access address. This address is set at device 14h, function 0, register 0xf0. |
Martin Roth | dcf253c | 2014-12-16 20:51:31 -0700 | [diff] [blame] | 276 | * This is an I/O address. The I/O address must be on 16-byte boundary. */ |
Michael Xie | 7586cef | 2008-09-22 13:11:39 +0000 | [diff] [blame] | 277 | pci_write_config32(dev, 0xf0, AB_INDX); |
| 278 | |
| 279 | /* To enable AB/BIF DMA access, a specific register inside the BIF register space needs to be configured first. */ |
| 280 | /*Enables the SB600 to send transactions upstream over A-Link Express interface. */ |
| 281 | axcfg_reg(0x04, 1 << 2, 1 << 2); |
| 282 | axindxc_reg(0x21, 0xff, 0); |
| 283 | |
| 284 | /* 2.3.5:Enabling Non-Posted Memory Write for the K8 Platform */ |
| 285 | axindxc_reg(0x10, 1 << 9, 1 << 9); |
| 286 | /* END of sbPorAtStartOfTblCfg */ |
| 287 | |
| 288 | /* sbDevicesPorInitTables */ |
| 289 | /* set smbus iobase */ |
| 290 | pci_write_config32(dev, 0x10, SMBUS_IO_BASE | 1); |
| 291 | |
| 292 | /* enable smbus controller interface */ |
| 293 | byte = pci_read_config8(dev, 0xd2); |
| 294 | byte |= (1 << 0); |
| 295 | pci_write_config8(dev, 0xd2, byte); |
| 296 | |
| 297 | /* set smbus 1, ASF 2.0 (Alert Standard Format), iobase */ |
| 298 | pci_write_config16(dev, 0x58, SMBUS_IO_BASE | 0x11); |
| 299 | |
Martin Roth | dcf253c | 2014-12-16 20:51:31 -0700 | [diff] [blame] | 300 | /* TODO: I don't know the usage of followed two lines. I copied them from CIM. */ |
Michael Xie | 7586cef | 2008-09-22 13:11:39 +0000 | [diff] [blame] | 301 | pci_write_config8(dev, 0x0a, 0x1); |
| 302 | pci_write_config8(dev, 0x0b, 0x6); |
| 303 | |
| 304 | /* KB2RstEnable */ |
| 305 | pci_write_config8(dev, 0x40, 0xd4); |
| 306 | |
| 307 | /* Enable ISA Address 0-960K decoding */ |
| 308 | pci_write_config8(dev, 0x48, 0x0f); |
| 309 | |
| 310 | /* Enable ISA Address 0xC0000-0xDFFFF decode */ |
| 311 | pci_write_config8(dev, 0x49, 0xff); |
| 312 | |
| 313 | /* Enable decode cycles to IO C50, C51, C52 GPM controls. */ |
| 314 | byte = pci_read_config8(dev, 0x41); |
| 315 | byte &= 0x80; |
| 316 | byte |= 0x33; |
| 317 | pci_write_config8(dev, 0x41, byte); |
| 318 | |
| 319 | /* Legacy DMA Prefetch Enhancement, CIM masked it. */ |
| 320 | /* pci_write_config8(dev, 0x43, 0x1); */ |
| 321 | |
| 322 | /* Disabling Legacy USB Fast SMI# */ |
| 323 | byte = pci_read_config8(dev, 0x62); |
| 324 | byte |= 0x24; |
| 325 | pci_write_config8(dev, 0x62, byte); |
| 326 | |
| 327 | /* Features Enable */ |
Joe Bao | 164463c | 2008-12-01 19:37:21 +0000 | [diff] [blame] | 328 | pci_write_config32(dev, 0x64, 0x829E7DBF); /* bit10: Enables the HPET interrupt. */ |
Michael Xie | 7586cef | 2008-09-22 13:11:39 +0000 | [diff] [blame] | 329 | |
| 330 | /* SerialIrq Control */ |
| 331 | pci_write_config8(dev, 0x69, 0x90); |
| 332 | |
| 333 | /* Test Mode, PCIB_SReset_En Mask is set. */ |
| 334 | pci_write_config8(dev, 0x6c, 0x20); |
| 335 | |
| 336 | /* IO Address Enable, CIM set 0x78 only and masked 0x79. */ |
| 337 | /*pci_write_config8(dev, 0x79, 0x4F); */ |
| 338 | pci_write_config8(dev, 0x78, 0xFF); |
| 339 | |
| 340 | /* This register is not used on sb600. It came from older chipset. */ |
| 341 | /*pci_write_config8(dev, 0x95, 0xFF); */ |
| 342 | |
| 343 | /* Set smbus iospace enable, I don't know why write 0x04 into reg5 that is reserved */ |
| 344 | pci_write_config16(dev, 0x4, 0x0407); |
| 345 | |
| 346 | /* clear any lingering errors, so the transaction will run */ |
| 347 | outb(inb(SMBUS_IO_BASE + SMBHSTSTAT), SMBUS_IO_BASE + SMBHSTSTAT); |
| 348 | |
| 349 | /* IDE Device, BDF:0-20-1 */ |
Stefan Reinauer | c02b4fc | 2010-03-22 11:42:32 +0000 | [diff] [blame] | 350 | printk(BIOS_INFO, "sb600_devices_por_init(): IDE Device, BDF:0-20-1\n"); |
Michael Xie | 7586cef | 2008-09-22 13:11:39 +0000 | [diff] [blame] | 351 | dev = pci_locate_device(PCI_ID(0x1002, 0x438C), 0); |
| 352 | /* Disable prefetch */ |
| 353 | byte = pci_read_config8(dev, 0x63); |
| 354 | byte |= 0x1; |
| 355 | pci_write_config8(dev, 0x63, byte); |
| 356 | |
| 357 | /* LPC Device, BDF:0-20-3 */ |
Stefan Reinauer | c02b4fc | 2010-03-22 11:42:32 +0000 | [diff] [blame] | 358 | printk(BIOS_INFO, "sb600_devices_por_init(): LPC Device, BDF:0-20-3\n"); |
Michael Xie | 7586cef | 2008-09-22 13:11:39 +0000 | [diff] [blame] | 359 | dev = pci_locate_device(PCI_ID(0x1002, 0x438D), 0); |
| 360 | /* DMA enable */ |
| 361 | pci_write_config8(dev, 0x40, 0x04); |
Rudolf Marek | 74ad66c | 2011-02-12 16:24:48 +0000 | [diff] [blame] | 362 | /* LPC Sync Timeout */ |
Michael Xie | 7586cef | 2008-09-22 13:11:39 +0000 | [diff] [blame] | 363 | pci_write_config8(dev, 0x49, 0xFF); |
Michael Xie | 7586cef | 2008-09-22 13:11:39 +0000 | [diff] [blame] | 364 | |
Michael Xie | 7586cef | 2008-09-22 13:11:39 +0000 | [diff] [blame] | 365 | /* Enable Tpm12_en and Tpm_legacy. I don't know what is its usage and copied from CIM. */ |
| 366 | pci_write_config8(dev, 0x7C, 0x05); |
| 367 | |
Joe Bao | 164463c | 2008-12-01 19:37:21 +0000 | [diff] [blame] | 368 | /* P2P Bridge, BDF:0-20-4, the configuration of the registers in this dev are copied from CIM, |
Michael Xie | 7586cef | 2008-09-22 13:11:39 +0000 | [diff] [blame] | 369 | * TODO: I don't know what are their mean? */ |
Stefan Reinauer | c02b4fc | 2010-03-22 11:42:32 +0000 | [diff] [blame] | 370 | printk(BIOS_INFO, "sb600_devices_por_init(): P2P Bridge, BDF:0-20-4\n"); |
Michael Xie | 7586cef | 2008-09-22 13:11:39 +0000 | [diff] [blame] | 371 | dev = pci_locate_device(PCI_ID(0x1002, 0x4384), 0); |
| 372 | /* I don't know why CIM tried to write into a read-only reg! */ |
| 373 | /*pci_write_config8(dev, 0x0c, 0x20) */ ; |
| 374 | |
| 375 | /* Arbiter enable. */ |
| 376 | pci_write_config8(dev, 0x43, 0xff); |
| 377 | |
Martin Roth | dcf253c | 2014-12-16 20:51:31 -0700 | [diff] [blame] | 378 | /* Set PCDMA request into height priority list. */ |
Michael Xie | 7586cef | 2008-09-22 13:11:39 +0000 | [diff] [blame] | 379 | /* pci_write_config8(dev, 0x49, 0x1) */ ; |
| 380 | |
| 381 | pci_write_config8(dev, 0x40, 0x26); |
| 382 | |
Joe Bao | 164463c | 2008-12-01 19:37:21 +0000 | [diff] [blame] | 383 | /* I don't know why CIM set reg0x1c as 0x11. |
Michael Xie | 7586cef | 2008-09-22 13:11:39 +0000 | [diff] [blame] | 384 | * System will block at sdram_initialize() if I set it before call sdram_initialize(). |
| 385 | * If it is necessary to set reg0x1c as 0x11, please call this function after sdram_initialize(). |
| 386 | * pci_write_config8(dev, 0x1c, 0x11); |
| 387 | * pci_write_config8(dev, 0x1d, 0x11);*/ |
| 388 | |
| 389 | /*CIM set this register; but I didn't find its description in RPR. |
| 390 | On DBM690T platform, I didn't find different between set and skip this register. |
Patrick Georgi | 62b3513 | 2009-08-26 18:14:30 +0000 | [diff] [blame] | 391 | But on Filbert platform, the DEBUG message from serial port on Peanut board can't be displayed |
Michael Xie | 7586cef | 2008-09-22 13:11:39 +0000 | [diff] [blame] | 392 | after the bit0 of this register is set. |
| 393 | pci_write_config8(dev, 0x04, 0x21); |
| 394 | */ |
| 395 | pci_write_config8(dev, 0x0d, 0x40); |
| 396 | pci_write_config8(dev, 0x1b, 0x40); |
| 397 | /* Enable PCIB_DUAL_EN_UP will fix potential problem with PCI cards. */ |
| 398 | pci_write_config8(dev, 0x50, 0x01); |
| 399 | |
| 400 | /* SATA Device, BDF:0-18-0, Non-Raid-5 SATA controller */ |
Stefan Reinauer | c02b4fc | 2010-03-22 11:42:32 +0000 | [diff] [blame] | 401 | printk(BIOS_INFO, "sb600_devices_por_init(): SATA Device, BDF:0-18-0\n"); |
Michael Xie | 7586cef | 2008-09-22 13:11:39 +0000 | [diff] [blame] | 402 | dev = pci_locate_device(PCI_ID(0x1002, 0x4380), 0); |
| 403 | |
| 404 | /*PHY Global Control, we are using A14. |
| 405 | * default: 0x2c40 for ASIC revision A12 and below |
| 406 | * 0x2c00 for ASIC revision A13 and above.*/ |
| 407 | pci_write_config16(dev, 0x86, 0x2C00); |
| 408 | |
| 409 | /* PHY Port0-3 Control */ |
| 410 | pci_write_config32(dev, 0x88, 0xB400DA); |
| 411 | pci_write_config32(dev, 0x8c, 0xB400DA); |
| 412 | pci_write_config32(dev, 0x90, 0xB400DA); |
| 413 | pci_write_config32(dev, 0x94, 0xB400DA); |
| 414 | |
| 415 | /* Port0-3 BIST Control/Status */ |
| 416 | pci_write_config8(dev, 0xa5, 0xB8); |
| 417 | pci_write_config8(dev, 0xad, 0xB8); |
| 418 | pci_write_config8(dev, 0xb5, 0xB8); |
| 419 | pci_write_config8(dev, 0xbd, 0xB8); |
| 420 | } |
| 421 | |
| 422 | /* sbPmioPorInitTable, Pre-initializing PMIO register space |
| 423 | * The power management (PM) block is resident in the PCI/LPC/ISA bridge. |
| 424 | * The PM regs are accessed via IO mapped regs 0xcd6 and 0xcd7. |
| 425 | * The index address is first programmed into IO reg 0xcd6. |
| 426 | * Read or write values are accessed through IO reg 0xcd7. |
| 427 | */ |
Stefan Reinauer | 3839a8e | 2009-07-14 19:10:10 +0000 | [diff] [blame] | 428 | static void sb600_pmio_por_init(void) |
Michael Xie | 7586cef | 2008-09-22 13:11:39 +0000 | [diff] [blame] | 429 | { |
| 430 | u8 byte; |
| 431 | |
Stefan Reinauer | c02b4fc | 2010-03-22 11:42:32 +0000 | [diff] [blame] | 432 | printk(BIOS_INFO, "sb600_pmio_por_init()\n"); |
Michael Xie | 7586cef | 2008-09-22 13:11:39 +0000 | [diff] [blame] | 433 | /* K8KbRstEn, KB_RST# control for K8 system. */ |
| 434 | byte = pmio_read(0x66); |
| 435 | byte |= 0x20; |
| 436 | pmio_write(0x66, byte); |
| 437 | |
| 438 | /* RPR2.3.4 S3/S4/S5 Function for the K8 Platform. */ |
| 439 | byte = pmio_read(0x52); |
| 440 | byte &= 0xc0; |
| 441 | byte |= 0x08; |
| 442 | pmio_write(0x52, byte); |
| 443 | |
| 444 | /* C state enable and SLP enable in C states. */ |
| 445 | byte = pmio_read(0x67); |
| 446 | byte |= 0x6; |
| 447 | pmio_write(0x67, byte); |
| 448 | |
| 449 | /* CIM sets 0x0e, but bit2 is for P4 system. */ |
| 450 | byte = pmio_read(0x68); |
| 451 | byte &= 0xf0; |
| 452 | byte |= 0x0c; |
| 453 | pmio_write(0x68, byte); |
| 454 | |
| 455 | /* Watch Dog Timer Control |
| 456 | * Set watchdog time base to 0xfec000f0 to avoid SCSI card boot failure. |
| 457 | * But I don't find WDT is enabled in SMBUS 0x41 bit3 in CIM. |
| 458 | */ |
| 459 | pmio_write(0x6c, 0xf0); |
| 460 | pmio_write(0x6d, 0x00); |
| 461 | pmio_write(0x6e, 0xc0); |
| 462 | pmio_write(0x6f, 0xfe); |
| 463 | |
| 464 | /* rpr2.14: Enables HPET periodical mode */ |
| 465 | byte = pmio_read(0x9a); |
| 466 | byte |= 1 << 7; |
| 467 | pmio_write(0x9a, byte); |
| 468 | byte = pmio_read(0x9f); |
| 469 | byte |= 1 << 5; |
| 470 | pmio_write(0x9f, byte); |
| 471 | byte = pmio_read(0x9e); |
| 472 | byte |= (1 << 6) | (1 << 7); |
| 473 | pmio_write(0x9e, byte); |
| 474 | |
| 475 | /* rpr2.14: Hides SM bus controller Bar1 where stores HPET MMIO base address */ |
Joe Bao | 164463c | 2008-12-01 19:37:21 +0000 | [diff] [blame] | 476 | /* We have to clear this bit here, otherwise the kernel hangs. */ |
Michael Xie | 7586cef | 2008-09-22 13:11:39 +0000 | [diff] [blame] | 477 | byte = pmio_read(0x55); |
| 478 | byte |= 1 << 7; |
Joe Bao | 164463c | 2008-12-01 19:37:21 +0000 | [diff] [blame] | 479 | byte |= 1 << 1; |
Michael Xie | 7586cef | 2008-09-22 13:11:39 +0000 | [diff] [blame] | 480 | pmio_write(0x55, byte); |
| 481 | |
Martin Roth | dcf253c | 2014-12-16 20:51:31 -0700 | [diff] [blame] | 482 | /* rpr2.14: Make HPET MMIO decoding controlled by the memory enable bit in command register of LPC ISA bridge */ |
Michael Xie | 7586cef | 2008-09-22 13:11:39 +0000 | [diff] [blame] | 483 | byte = pmio_read(0x52); |
| 484 | byte |= 1 << 6; |
| 485 | pmio_write(0x52, byte); |
| 486 | |
| 487 | /* rpr2.22: PLL Reset */ |
| 488 | byte = pmio_read(0x86); |
| 489 | byte |= 1 << 7; |
| 490 | pmio_write(0x86, byte); |
| 491 | |
| 492 | /* rpr2.3.3 */ |
| 493 | /* This provides 16us delay before the assertion of LDTSTP# when C3 is entered. |
| 494 | * The delay will allow USB DMA to go on in a continuous manner |
| 495 | */ |
| 496 | pmio_write(0x89, 0x10); |
| 497 | /* Set this bit to allow pop-up request being latched during the minimum LDTSTP# assertion time */ |
| 498 | byte = pmio_read(0x52); |
| 499 | byte |= 1 << 7; |
| 500 | pmio_write(0x52, byte); |
| 501 | |
| 502 | /* rpr2.15: ASF Remote Control Action */ |
| 503 | byte = pmio_read(0x9f); |
| 504 | byte |= 1 << 6; |
| 505 | pmio_write(0x9f, byte); |
| 506 | |
| 507 | /* rpr2.19: Enabling Spread Spectrum */ |
| 508 | byte = pmio_read(0x42); |
| 509 | byte |= 1 << 7; |
| 510 | pmio_write(0x42, byte); |
| 511 | } |
| 512 | |
| 513 | /* |
| 514 | * Compliant with CIM_48's sbPciCfg. |
| 515 | * Add any south bridge setting. |
| 516 | */ |
Stefan Reinauer | 3839a8e | 2009-07-14 19:10:10 +0000 | [diff] [blame] | 517 | static void sb600_pci_cfg(void) |
Michael Xie | 7586cef | 2008-09-22 13:11:39 +0000 | [diff] [blame] | 518 | { |
| 519 | device_t dev; |
| 520 | u8 byte; |
| 521 | |
| 522 | /* SMBus Device, BDF:0-20-0 */ |
| 523 | dev = pci_locate_device(PCI_ID(0x1002, 0x4385), 0); |
Martin Roth | dcf253c | 2014-12-16 20:51:31 -0700 | [diff] [blame] | 524 | /* Enable the hidden revision ID, available after A13. */ |
Michael Xie | 7586cef | 2008-09-22 13:11:39 +0000 | [diff] [blame] | 525 | byte = pci_read_config8(dev, 0x70); |
| 526 | byte |= (1 << 8); |
| 527 | pci_write_config8(dev, 0x70, byte); |
| 528 | /* rpr2.20 Disable Timer IRQ Enhancement for proper operation of the 8254 timer, 0xae[5]. */ |
| 529 | byte = pci_read_config8(dev, 0xae); |
| 530 | byte |= (1 << 5); |
| 531 | pci_write_config8(dev, 0xae, byte); |
| 532 | |
| 533 | /* Enable watchdog decode timer */ |
| 534 | byte = pci_read_config8(dev, 0x41); |
| 535 | byte |= (1 << 3); |
| 536 | pci_write_config8(dev, 0x41, byte); |
| 537 | |
Joe Bao | 164463c | 2008-12-01 19:37:21 +0000 | [diff] [blame] | 538 | /* Set to 1 to reset USB on the software (such as IO-64 or IO-CF9 cycles) |
Michael Xie | 7586cef | 2008-09-22 13:11:39 +0000 | [diff] [blame] | 539 | * generated PCIRST#. */ |
| 540 | byte = pmio_read(0x65); |
| 541 | byte |= (1 << 4); |
| 542 | pmio_write(0x65, byte); |
| 543 | /*For A13 and above. */ |
| 544 | if (get_sb600_revision() > 0x12) { |
| 545 | /* rpr2.16 C-State Reset, PMIO 0x9f[7]. */ |
| 546 | byte = pmio_read(0x9f); |
| 547 | byte |= (1 << 7); |
| 548 | pmio_write(0x9f, byte); |
| 549 | /* rpr2.17 PCI Clock Period will increase to 30.8ns. 0x53[7]. */ |
| 550 | byte = pmio_read(0x53); |
| 551 | byte |= (1 << 7); |
| 552 | pmio_write(0x53, byte); |
| 553 | } |
| 554 | |
| 555 | /* IDE Device, BDF:0-20-1 */ |
| 556 | dev = pci_locate_device(PCI_ID(0x1002, 0x438C), 0); |
| 557 | /* Enable IDE Explicit prefetch, 0x63[0] clear */ |
| 558 | byte = pci_read_config8(dev, 0x63); |
| 559 | byte &= 0xfe; |
| 560 | pci_write_config8(dev, 0x63, byte); |
| 561 | |
| 562 | /* LPC Device, BDF:0-20-3 */ |
| 563 | dev = pci_locate_device(PCI_ID(0x1002, 0x438D), 0); |
| 564 | /* rpr7.2 Enabling LPC DMA function. */ |
| 565 | byte = pci_read_config8(dev, 0x40); |
| 566 | byte |= (1 << 2); |
| 567 | pci_write_config8(dev, 0x40, byte); |
| 568 | /* rpr7.3 Disabling LPC TimeOut. 0x48[7] clear. */ |
| 569 | byte = pci_read_config8(dev, 0x48); |
| 570 | byte &= 0x7f; |
| 571 | pci_write_config8(dev, 0x48, byte); |
| 572 | /* rpr7.5 Disabling LPC MSI Capability, 0x78[1] clear. */ |
| 573 | byte = pci_read_config8(dev, 0x78); |
| 574 | byte &= 0xfd; |
| 575 | pci_write_config8(dev, 0x78, byte); |
| 576 | |
| 577 | /* SATA Device, BDF:0-18-0, Non-Raid-5 SATA controller */ |
| 578 | dev = pci_locate_device(PCI_ID(0x1002, 0x4380), 0); |
| 579 | /* rpr6.8 Disabling SATA MSI Capability, for A13 and above, 0x42[7]. */ |
| 580 | if (0x12 < get_sb600_revision()) { |
| 581 | u32 reg32; |
| 582 | reg32 = pci_read_config32(dev, 0x40); |
| 583 | reg32 |= (1 << 23); |
| 584 | pci_write_config32(dev, 0x40, reg32); |
| 585 | } |
| 586 | |
| 587 | /* EHCI Device, BDF:0-19-5, ehci usb controller */ |
| 588 | dev = pci_locate_device(PCI_ID(0x1002, 0x4386), 0); |
| 589 | /* rpr5.10 Disabling USB EHCI MSI Capability. 0x50[6]. */ |
| 590 | byte = pci_read_config8(dev, 0x50); |
| 591 | byte |= (1 << 6); |
| 592 | pci_write_config8(dev, 0x50, byte); |
| 593 | |
| 594 | /* OHCI0 Device, BDF:0-19-0, ohci usb controller #0 */ |
| 595 | dev = pci_locate_device(PCI_ID(0x1002, 0x4387), 0); |
| 596 | /* rpr5.11 Disabling USB OHCI MSI Capability. 0x40[12:8]=0x1f. */ |
| 597 | byte = pci_read_config8(dev, 0x41); |
| 598 | byte |= 0x1f; |
| 599 | pci_write_config8(dev, 0x41, byte); |
| 600 | |
| 601 | } |
| 602 | |
| 603 | /* |
| 604 | * Compliant with CIM_48's ATSBPowerOnResetInitJSP |
| 605 | */ |
Stefan Reinauer | 3839a8e | 2009-07-14 19:10:10 +0000 | [diff] [blame] | 606 | static void sb600_por_init(void) |
Michael Xie | 7586cef | 2008-09-22 13:11:39 +0000 | [diff] [blame] | 607 | { |
| 608 | /* sbDevicesPorInitTable + sbK8PorInitTable */ |
| 609 | sb600_devices_por_init(); |
| 610 | |
| 611 | /* sbPmioPorInitTable + sbK8PmioPorInitTable */ |
| 612 | sb600_pmio_por_init(); |
| 613 | } |
| 614 | |
| 615 | /* |
| 616 | * Compliant with CIM_48's AtiSbBeforePciInit |
| 617 | * It should be called during early POST after memory detection and BIOS shadowing but before PCI bus enumeration. |
| 618 | */ |
Stefan Reinauer | 3839a8e | 2009-07-14 19:10:10 +0000 | [diff] [blame] | 619 | static void sb600_before_pci_init(void) |
Michael Xie | 7586cef | 2008-09-22 13:11:39 +0000 | [diff] [blame] | 620 | { |
| 621 | sb600_pci_cfg(); |
| 622 | } |
| 623 | |
| 624 | /* |
| 625 | * This function should be called after enable_sb600_smbus(). |
| 626 | */ |
| 627 | static void sb600_early_setup(void) |
| 628 | { |
Stefan Reinauer | c02b4fc | 2010-03-22 11:42:32 +0000 | [diff] [blame] | 629 | printk(BIOS_INFO, "sb600_early_setup()\n"); |
Michael Xie | 7586cef | 2008-09-22 13:11:39 +0000 | [diff] [blame] | 630 | sb600_por_init(); |
| 631 | } |
| 632 | |
| 633 | static int smbus_read_byte(u32 device, u32 address) |
| 634 | { |
| 635 | return do_smbus_read_byte(SMBUS_IO_BASE, device, address); |
| 636 | } |