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review.coreboot.org / coreboot / 9631016660423d0585a1 / . / src / southbridge / amd / rs690 / rs690.h
blob: c0f13ac06ff712ac61052477a2fa47859a6975f2 [file] [log] [blame]
Michael Xie06755e42008-09-22 13:07:20 +0000[diff] [blame]1/*
2 * This file is part of the coreboot project.
3 *
4 * Copyright (C) 2008 Advanced Micro Devices, Inc.
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; version 2 of the License.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
Michael Xie06755e42008-09-22 13:07:20 +0000[diff] [blame]14 */
15
16#ifndef __RS690_H__
17#define __RS690_H__
18
19#include <stdint.h>
Uwe Hermannb7d781d2008-10-13 21:41:24 +0000[diff] [blame]20#include <device/pci_ids.h>
Michael Xie06755e42008-09-22 13:07:20 +0000[diff] [blame]21#include "chip.h"
22
Michael Xie06755e42008-09-22 13:07:20 +0000[diff] [blame]23#define NBMISC_INDEX 0x60
24#define NBHTIU_INDEX 0xA8
25#define NBMC_INDEX 0xE8
26#define NBPCIE_INDEX 0xE0
27#define EXT_CONF_BASE_ADDRESS 0xE0000000
28#define TEMP_MMIO_BASE_ADDRESS 0xC0000000
29
30typedef struct __PCIE_CFG__ {
31 u16 Config;
32 u8 ResetReleaseDelay;
33 u8 Gfx0Width;
34 u8 Gfx1Width;
35 u8 GfxPayload;
36 u8 GppPayload;
37 u8 PortDetect;
38 u8 PortHp; /* hot plug */
39 u16 DbgConfig;
40 u32 DbgConfig2;
41 u8 GfxLx;
42 u8 GppLx;
43 u8 NBSBLx;
44 u8 PortSlotInit;
45 u8 Gfx0Pwr;
46 u8 Gfx1Pwr;
47 u8 GppPwr;
48} PCIE_CFG;
49
50/* PCIE config flags */
51#define PCIE_DUALSLOT_CONFIG (1 << 0)
52#define PCIE_OVERCLOCK_ENABLE (1 << 1)
53#define PCIE_GPP_CLK_GATING (1 << 2)
54#define PCIE_ENABLE_STATIC_DEV_REMAP (1 << 3)
55#define PCIE_OFF_UNUSED_GFX_LANES (1 << 4)
56#define PCIE_OFF_UNUSED_GPP_LANES (1 << 5)
57#define PCIE_DISABLE_HIDE_UNUSED_PORTS (1 << 7)
58#define PCIE_GFX_CLK_GATING (1 << 11)
59#define PCIE_GFX_COMPLIANCE (1 << 14)
60#define PCIE_GPP_COMPLIANCE (1 << 15)
61
62typedef enum _NB_REVISION_ {
63 REV_RS690_A11 = 5,
64 REV_RS690_A12 = 6,
65 REV_RS690_A21 = 7,
66} NB_REVISION;
67
68/* -------------------- ----------------------
69* NBMISCIND
70 ------------------- -----------------------*/
71#define PCIE_LINK_CFG 0x8
72#define PCIE_NBCFG_REG7 0x37
73#define STRAPS_OUTPUT_MUX_7 0x67
74#define STRAPS_OUTPUT_MUX_A 0x6a
75
76/* -------------------- ----------------------
77* PCIEIND
78 ------------------- -----------------------*/
79#define PCIE_CI_CNTL 0x20
80#define PCIE_LC_LINK_WIDTH 0xa2
81#define PCIE_LC_STATE0 0xa5
82#define PCIE_VC0_RESOURCE_STATUS 0x11a /* 16bit read only */
83
84#define PCIE_CORE_INDEX_GFX (0 << 16) /* see 5.2.2 */
85#define PCIE_CORE_INDEX_GPPSB (1 << 16)
86
87/* contents of PCIE_NBCFG_REG7 */
88#define RECONFIG_GPPSB_EN (1 << 12)
89#define RECONFIG_GPPSB_GPPSB (1 << 14)
90#define RECONFIG_GPPSB_LINK_CONFIG (1 << 15)
91#define RECONFIG_GPPSB_ATOMIC_RESET (1 << 17)
92
93/* contents of PCIE_VC0_RESOURCE_STATUS */
94#define VC_NEGOTIATION_PENDING (1 << 1)
95
96#define LC_STATE_RECONFIG_GPPSB 0x10
97
98/* ------------------------------------------------
99* Global variable
100* ------------------------------------------------- */
101extern PCIE_CFG AtiPcieCfg;
102
Martin Rotha9e3a752014-12-16 20:52:23 -0700[diff] [blame]103/* ----------------- export functions ----------------- */
Michael Xie06755e42008-09-22 13:07:20 +0000[diff] [blame]104u32 nbmisc_read_index(device_t nb_dev, u32 index);
105void nbmisc_write_index(device_t nb_dev, u32 index, u32 data);
106u32 nbpcie_p_read_index(device_t dev, u32 index);
107void nbpcie_p_write_index(device_t dev, u32 index, u32 data);
108u32 nbpcie_ind_read_index(device_t nb_dev, u32 index);
109void nbpcie_ind_write_index(device_t nb_dev, u32 index, u32 data);
110u32 htiu_read_index(device_t nb_dev, u32 index);
111void htiu_write_index(device_t nb_dev, u32 index, u32 data);
112u32 nbmc_read_index(device_t nb_dev, u32 index);
113void nbmc_write_index(device_t nb_dev, u32 index, u32 data);
114
115u32 pci_ext_read_config32(device_t nb_dev, device_t dev, u32 reg);
116void pci_ext_write_config32(device_t nb_dev, device_t dev, u32 reg, u32 mask, u32 val);
117
118void set_nbcfg_enable_bits(device_t nb_dev, u32 reg_pos, u32 mask, u32 val);
119void set_nbcfg_enable_bits_8(device_t nb_dev, u32 reg_pos, u8 mask, u8 val);
120void set_nbmc_enable_bits(device_t nb_dev, u32 reg_pos, u32 mask, u32 val);
121void set_htiu_enable_bits(device_t nb_dev, u32 reg_pos, u32 mask, u32 val);
122void set_nbmisc_enable_bits(device_t nb_dev, u32 reg_pos, u32 mask, u32 val);
123void set_pcie_enable_bits(device_t dev, u32 reg_pos, u32 mask, u32 val);
124void rs690_set_tom(device_t nb_dev);
125
126void ProgK8TempMmioBase(u8 in_out, u32 pcie_base_add, u32 mmio_base_add);
127void enable_pcie_bar3(device_t nb_dev);
128void disable_pcie_bar3(device_t nb_dev);
129
130void rs690_enable(device_t dev);
131void rs690_gpp_sb_init(device_t nb_dev, device_t dev, u32 port);
132void rs690_gfx_init(device_t nb_dev, device_t dev, u32 port);
133void avoid_lpc_dma_deadlock(device_t nb_dev, device_t sb_dev);
134void config_gpp_core(device_t nb_dev, device_t sb_dev);
135void PcieReleasePortTraining(device_t nb_dev, device_t dev, u32 port);
136u8 PcieTrainPort(device_t nb_dev, device_t dev, u32 port);
137#endif /* RS690_H */