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review.coreboot.org / coreboot / 9631016660423d0585a1 / . / src / southbridge / amd / cs5535 / cs5535.c
blob: 70b8386dfa62f13623124abdfae8b179d7a0488d [file] [log] [blame]
Ronald G. Minnich2bb216a2006-01-27 23:46:30 +0000[diff] [blame]1
2#include <arch/io.h>
Uwe Hermann74d1a6e2010-10-12 17:34:08 +0000[diff] [blame]3#include <arch/ioapic.h>
Ronald G. Minnich2bb216a2006-01-27 23:46:30 +0000[diff] [blame]4#include <device/device.h>
5#include <device/pci.h>
6#include <device/pci_ops.h>
7#include <device/pci_ids.h>
8#include <console/console.h>
9#include "cs5535.h"
10
11static void nvram_on(struct device *dev)
12{
13#if 0
14 volatile char *flash = (volatile unsigned char *)0xFFFc0000;
15 unsigned char id1, id2;
16#endif
17 unsigned char reg;
18
19 /* Enable writes to flash at top of memory */
20 pci_write_config8(dev, 0x52, 0xee);
21
22 /* Set positive decode on ROM */
Martin Roth55e31a92014-12-16 20:53:49 -0700[diff] [blame]23 /* Also, there is no apparent reason to turn off the device on the */
Ronald G. Minnich2bb216a2006-01-27 23:46:30 +0000[diff] [blame]24 /* IDE devices */
Stefan Reinauer14e22772010-04-27 06:56:47 +0000[diff] [blame]25
Ronald G. Minnich2bb216a2006-01-27 23:46:30 +0000[diff] [blame]26 reg = pci_read_config8(dev, 0x5b);
27 reg |= 1 << 5; /* ROM Decode */
28 reg |= 1 << 3; /* Primary IDE decode */
29 reg |= 1 << 4; /* Secondary IDE decode */
30
31 pci_write_config8(dev, 0x5b, reg);
32
33#if 0 // just to test if the flash is accessible!
34 *(flash + 0x555) = 0xaa;
35 *(flash + 0x2aa) = 0x55;
36 *(flash + 0x555) = 0x90;
37
38 id1 = *(volatile unsigned char *) flash;
39 id2 = *(volatile unsigned char *) (flash + 1);
40
41 *flash = 0xf0;
42
Stefan Reinauerc02b4fc2010-03-22 11:42:32 +0000[diff] [blame]43 printk(BIOS_DEBUG, "Flash device: MFGID %02x, DEVID %02x\n", id1, id2);
Ronald G. Minnich2bb216a2006-01-27 23:46:30 +0000[diff] [blame]44#endif
45}
46
Stefan Reinauer14e22772010-04-27 06:56:47 +0000[diff] [blame]47
Ronald G. Minnich2bb216a2006-01-27 23:46:30 +0000[diff] [blame]48static void southbridge_init(struct device *dev)
49{
Stefan Reinauerc02b4fc2010-03-22 11:42:32 +0000[diff] [blame]50 printk(BIOS_SPEW, "cs5535: %s\n", __func__);
Ronald G. Minnich2bb216a2006-01-27 23:46:30 +0000[diff] [blame]51 nvram_on(dev);
52}
53
54/*
55static void dump_south(struct device *dev)
56{
57 int i, j;
58
59 for(i=0; i<256; i+=16) {
Stefan Reinauerc02b4fc2010-03-22 11:42:32 +0000[diff] [blame]60 printk(BIOS_DEBUG, "0x%02x: ", i);
Ronald G. Minnich2bb216a2006-01-27 23:46:30 +0000[diff] [blame]61 for(j=0; j<16; j++)
Stefan Reinauerc02b4fc2010-03-22 11:42:32 +0000[diff] [blame]62 printk(BIOS_DEBUG, "%02x ", pci_read_config8(dev, i+j));
63 printk(BIOS_DEBUG, "\n");
Ronald G. Minnich2bb216a2006-01-27 23:46:30 +0000[diff] [blame]64 }
65}
66*/
67
68static void southbridge_enable(struct device *dev)
69{
Stefan Reinauerc02b4fc2010-03-22 11:42:32 +0000[diff] [blame]70 printk(BIOS_SPEW, "%s: dev is %p\n", __func__, dev);
Ronald G. Minnich2bb216a2006-01-27 23:46:30 +0000[diff] [blame]71}
72
Myles Watson29cc9ed2009-07-02 18:56:24 +0000[diff] [blame]73static void cs5535_read_resources(device_t dev)
74{
Myles Watson81af48e2010-06-07 15:39:04 +0000[diff] [blame]75 struct resource *res;
Myles Watson29cc9ed2009-07-02 18:56:24 +0000[diff] [blame]76
77 pci_dev_read_resources(dev);
78
79 res = new_resource(dev, 1);
80 res->base = 0x0UL;
Myles Watson81af48e2010-06-07 15:39:04 +0000[diff] [blame]81 res->size = 0x1000UL;
Myles Watson29cc9ed2009-07-02 18:56:24 +0000[diff] [blame]82 res->limit = 0xffffUL;
83 res->flags = IORESOURCE_IO | IORESOURCE_ASSIGNED | IORESOURCE_FIXED;
84
85 res = new_resource(dev, 3); /* IOAPIC */
Uwe Hermann74d1a6e2010-10-12 17:34:08 +0000[diff] [blame]86 res->base = IO_APIC_ADDR;
Myles Watson29cc9ed2009-07-02 18:56:24 +0000[diff] [blame]87 res->size = 0x00001000;
88 res->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED | IORESOURCE_FIXED;
89}
90
Ronald G. Minnich2bb216a2006-01-27 23:46:30 +0000[diff] [blame]91static struct device_operations southbridge_ops = {
Myles Watson29cc9ed2009-07-02 18:56:24 +0000[diff] [blame]92 .read_resources = cs5535_read_resources,
Ronald G. Minnich2bb216a2006-01-27 23:46:30 +0000[diff] [blame]93 .set_resources = pci_dev_set_resources,
Myles Watson7eac4452010-06-17 16:16:56 +0000[diff] [blame]94 .enable_resources = pci_dev_enable_resources,
Ronald G. Minnich2bb216a2006-01-27 23:46:30 +0000[diff] [blame]95 .init = southbridge_init,
96 .enable = southbridge_enable,
Ronald G. Minnich2bb216a2006-01-27 23:46:30 +0000[diff] [blame]97};
98
Stefan Reinauerf1cf1f72007-10-24 09:08:58 +0000[diff] [blame]99static const struct pci_driver cs5535_pci_driver __pci_driver = {
Ronald G. Minnich2bb216a2006-01-27 23:46:30 +0000[diff] [blame]100 .ops = &southbridge_ops,
Ronald G. Minnich0f1e9ea2006-01-28 20:05:37 +0000[diff] [blame]101 .vendor = PCI_VENDOR_ID_NS,
102 .device = PCI_DEVICE_ID_NS_CS5535
Ronald G. Minnich2bb216a2006-01-27 23:46:30 +0000[diff] [blame]103};
Patrick Georgiebb43d62009-10-08 20:17:14 +0000[diff] [blame]104
105struct chip_operations southbridge_amd_cs5535_ops = {
106 CHIP_NAME("AMD Geode CS5535 Southbridge")
107 /* This is only called when this device is listed in the
108 * static device tree.
109 */
110 .enable_dev = southbridge_enable,
111};