Ronald G. Minnich | c0d5eb2 | 2013-08-01 11:38:05 -0700 | [diff] [blame] | 1 | /* |
| 2 | * Copyright (C) 2012 Samsung Electronics |
| 3 | * |
| 4 | * Author: Donghwa Lee <dh09.lee@samsung.com> |
| 5 | * |
| 6 | * This program is free software; you can redistribute it and/or |
| 7 | * modify it under the terms of the GNU General Public License as |
| 8 | * published by the Free Software Foundation; either version 2 of |
| 9 | * the License, or (at your option) any later version. |
| 10 | * |
| 11 | * This program is distributed in the hope that it will be useful, |
| 12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 14 | * GNU General Public License for more details. |
Ronald G. Minnich | c0d5eb2 | 2013-08-01 11:38:05 -0700 | [diff] [blame] | 15 | */ |
| 16 | |
| 17 | #include <arch/io.h> |
Julius Werner | 80af442 | 2014-10-20 13:18:56 -0700 | [diff] [blame] | 18 | #include <console/console.h> |
| 19 | #include <delay.h> |
| 20 | #include <lib.h> |
| 21 | #include <soc/dp.h> |
| 22 | #include <soc/fimd.h> |
| 23 | #include <soc/i2c.h> |
| 24 | #include <soc/power.h> |
| 25 | #include <soc/sysreg.h> |
Ronald G. Minnich | c0d5eb2 | 2013-08-01 11:38:05 -0700 | [diff] [blame] | 26 | #include <stdlib.h> |
| 27 | #include <string.h> |
| 28 | #include <timer.h> |
Ronald G. Minnich | c0d5eb2 | 2013-08-01 11:38:05 -0700 | [diff] [blame] | 29 | |
| 30 | /* |
| 31 | * Here is the rough outline of how we bring up the display: |
| 32 | * 1. Upon power-on Sink generates a hot plug detection pulse thru HPD |
| 33 | * 2. Source determines video mode by reading DPCD receiver capability field |
| 34 | * (DPCD 00000h to 0000Dh) including eDP CP capability register (DPCD |
| 35 | * 0000Dh). |
| 36 | * 3. Sink replies DPCD receiver capability field. |
| 37 | * 4. Source starts EDID read thru I2C-over-AUX. |
| 38 | * 5. Sink replies EDID thru I2C-over-AUX. |
| 39 | * 6. Source determines link configuration, such as MAX_LINK_RATE and |
| 40 | * MAX_LANE_COUNT. Source also determines which type of eDP Authentication |
| 41 | * method to use and writes DPCD link configuration field (DPCD 00100h to |
| 42 | * 0010Ah) including eDP configuration set (DPCD 0010Ah). |
| 43 | * 7. Source starts link training. Sink does clock recovery and equalization. |
| 44 | * 8. Source reads DPCD link status field (DPCD 00200h to 0020Bh). |
| 45 | * 9. Sink replies DPCD link status field. If main link is not stable, Source |
| 46 | * repeats Step 7. |
| 47 | * 10. Source sends MSA (Main Stream Attribute) data. Sink extracts video |
| 48 | * parameters and recovers stream clock. |
| 49 | * 11. Source sends video data. |
| 50 | */ |
| 51 | |
| 52 | |
| 53 | static int exynos_dp_init_dp(void) |
| 54 | { |
| 55 | int ret; |
| 56 | exynos_dp_reset(); |
| 57 | |
| 58 | /* SW defined function Normal operation */ |
| 59 | exynos_dp_enable_sw_func(DP_ENABLE); |
| 60 | |
| 61 | ret = exynos_dp_init_analog_func(); |
| 62 | if (ret != EXYNOS_DP_SUCCESS) |
| 63 | return ret; |
| 64 | |
| 65 | exynos_dp_init_hpd(); |
| 66 | exynos_dp_init_aux(); |
| 67 | |
| 68 | return ret; |
| 69 | } |
| 70 | |
| 71 | static unsigned char exynos_dp_calc_edid_check_sum(unsigned char *edid_data) |
| 72 | { |
| 73 | int i; |
| 74 | unsigned char sum = 0; |
| 75 | |
| 76 | for (i = 0; i < EDID_BLOCK_LENGTH; i++) |
| 77 | sum = sum + edid_data[i]; |
| 78 | |
| 79 | return sum; |
| 80 | } |
| 81 | |
| 82 | static unsigned int exynos_dp_read_edid(void) |
| 83 | { |
| 84 | unsigned char edid[EDID_BLOCK_LENGTH * 2]; |
| 85 | unsigned int extend_block = 0; |
| 86 | unsigned char sum; |
| 87 | unsigned char test_vector; |
| 88 | int retval = 0; |
| 89 | |
| 90 | /* |
| 91 | * EDID device address is 0x50. |
| 92 | * However, if necessary, you must have set upper address |
| 93 | * into E-EDID in I2C device, 0x30. |
| 94 | */ |
| 95 | |
| 96 | /* Read Extension Flag, Number of 128-byte EDID extension blocks */ |
| 97 | if (exynos_dp_read_byte_from_i2c |
| 98 | (I2C_EDID_DEVICE_ADDR, EDID_EXTENSION_FLAG, &extend_block)) |
| 99 | return -1; |
| 100 | |
| 101 | if (extend_block > 0) { |
| 102 | /* Read EDID data */ |
| 103 | retval = exynos_dp_read_bytes_from_i2c(I2C_EDID_DEVICE_ADDR, |
| 104 | EDID_HEADER_PATTERN, |
| 105 | EDID_BLOCK_LENGTH, |
| 106 | &edid[EDID_HEADER_PATTERN]); |
| 107 | |
| 108 | if (retval != 0) { |
| 109 | printk(BIOS_ERR, "DP EDID Read failed!\n"); |
| 110 | return -1; |
| 111 | } |
| 112 | sum = exynos_dp_calc_edid_check_sum(edid); |
| 113 | if (sum != 0) { |
| 114 | printk(BIOS_ERR, "DP EDID bad checksum!\n"); |
| 115 | return -1; |
| 116 | } |
| 117 | /* Read additional EDID data */ |
| 118 | retval = exynos_dp_read_bytes_from_i2c(I2C_EDID_DEVICE_ADDR, |
| 119 | EDID_BLOCK_LENGTH, |
| 120 | EDID_BLOCK_LENGTH, |
| 121 | &edid[EDID_BLOCK_LENGTH]); |
| 122 | if (retval != 0) { |
| 123 | printk(BIOS_ERR, "DP EDID Read failed!\n"); |
| 124 | return -1; |
| 125 | } |
| 126 | sum = exynos_dp_calc_edid_check_sum(&edid[EDID_BLOCK_LENGTH]); |
| 127 | if (sum != 0) { |
| 128 | printk(BIOS_ERR, "DP EDID bad checksum!\n"); |
| 129 | return -1; |
| 130 | } |
| 131 | exynos_dp_read_byte_from_dpcd(DPCD_TEST_REQUEST, |
| 132 | &test_vector); |
| 133 | if (test_vector & DPCD_TEST_EDID_READ) { |
| 134 | exynos_dp_write_byte_to_dpcd(DPCD_TEST_EDID_CHECKSUM, |
| 135 | edid[EDID_BLOCK_LENGTH + EDID_CHECKSUM]); |
| 136 | exynos_dp_write_byte_to_dpcd(DPCD_TEST_RESPONSE, |
| 137 | DPCD_TEST_EDID_CHECKSUM_WRITE); |
| 138 | } |
| 139 | } else { |
| 140 | /* Read EDID data */ |
| 141 | retval = exynos_dp_read_bytes_from_i2c(I2C_EDID_DEVICE_ADDR, |
| 142 | EDID_HEADER_PATTERN, |
| 143 | EDID_BLOCK_LENGTH, |
| 144 | &edid[EDID_HEADER_PATTERN]); |
| 145 | |
| 146 | if (retval != 0) { |
| 147 | printk(BIOS_ERR, "DP EDID Read failed!\n"); |
| 148 | return -1; |
| 149 | } |
| 150 | sum = exynos_dp_calc_edid_check_sum(edid); |
| 151 | if (sum != 0) { |
| 152 | printk(BIOS_ERR, "DP EDID bad checksum!\n"); |
| 153 | return -1; |
| 154 | } |
| 155 | |
| 156 | exynos_dp_read_byte_from_dpcd(DPCD_TEST_REQUEST, |
| 157 | &test_vector); |
| 158 | if (test_vector & DPCD_TEST_EDID_READ) { |
| 159 | exynos_dp_write_byte_to_dpcd(DPCD_TEST_EDID_CHECKSUM, |
| 160 | edid[EDID_CHECKSUM]); |
| 161 | exynos_dp_write_byte_to_dpcd(DPCD_TEST_RESPONSE, |
| 162 | DPCD_TEST_EDID_CHECKSUM_WRITE); |
| 163 | } |
| 164 | |
| 165 | } |
| 166 | |
| 167 | return 0; |
| 168 | } |
| 169 | |
| 170 | static unsigned int exynos_dp_handle_edid(struct edp_device_info *edp_info) |
| 171 | { |
| 172 | unsigned char buf[12]; |
| 173 | unsigned int ret; |
| 174 | unsigned char temp; |
| 175 | unsigned char retry_cnt; |
| 176 | unsigned char dpcd_rev[16]; |
| 177 | unsigned char lane_bw[16]; |
| 178 | unsigned char lane_cnt[16]; |
| 179 | |
| 180 | memset(dpcd_rev, 0, sizeof(dpcd_rev)); |
| 181 | memset(lane_bw, 0, sizeof(lane_bw)); |
| 182 | memset(lane_cnt, 0, sizeof(lane_cnt)); |
| 183 | memset(buf, 0, sizeof(buf)); |
| 184 | |
| 185 | retry_cnt = 5; |
| 186 | while (retry_cnt) { |
| 187 | /* Read DPCD 0x0000-0x000b */ |
| 188 | ret = exynos_dp_read_bytes_from_dpcd(DPCD_DPCD_REV, 12, |
| 189 | buf); |
| 190 | if (ret != EXYNOS_DP_SUCCESS) { |
| 191 | if (retry_cnt == 0) { |
| 192 | printk(BIOS_ERR, "DP read_byte_from_dpcd() failed\n"); |
| 193 | return ret; |
| 194 | } |
| 195 | retry_cnt--; |
| 196 | } else |
| 197 | break; |
| 198 | } |
| 199 | /* */ |
| 200 | temp = buf[DPCD_DPCD_REV]; |
| 201 | if (temp == DP_DPCD_REV_10 || temp == DP_DPCD_REV_11) |
| 202 | edp_info->dpcd_rev = temp; |
| 203 | else { |
| 204 | printk(BIOS_ERR, "DP Wrong DPCD Rev : %x\n", temp); |
| 205 | return -1; |
| 206 | } |
| 207 | temp = buf[DPCD_MAX_LINK_RATE]; |
| 208 | if (temp == DP_LANE_BW_1_62 || temp == DP_LANE_BW_2_70) |
| 209 | edp_info->lane_bw = temp; |
| 210 | else { |
| 211 | printk(BIOS_ERR, "DP Wrong MAX LINK RATE : %x\n", temp); |
| 212 | return -1; |
| 213 | } |
Martin Roth | 1fc2ba5 | 2014-12-07 14:59:11 -0700 | [diff] [blame] | 214 | /*Refer VESA Display Port Standard Ver1.1a Page 120 */ |
Ronald G. Minnich | c0d5eb2 | 2013-08-01 11:38:05 -0700 | [diff] [blame] | 215 | if (edp_info->dpcd_rev == DP_DPCD_REV_11) { |
| 216 | temp = buf[DPCD_MAX_LANE_COUNT] & 0x1f; |
| 217 | if (buf[DPCD_MAX_LANE_COUNT] & 0x80) |
| 218 | edp_info->dpcd_efc = 1; |
| 219 | else |
| 220 | edp_info->dpcd_efc = 0; |
| 221 | } else { |
| 222 | temp = buf[DPCD_MAX_LANE_COUNT]; |
| 223 | edp_info->dpcd_efc = 0; |
| 224 | } |
| 225 | |
| 226 | if (temp == DP_LANE_CNT_1 || temp == DP_LANE_CNT_2 || |
| 227 | temp == DP_LANE_CNT_4) { |
| 228 | edp_info->lane_cnt = temp; |
| 229 | } else { |
| 230 | printk(BIOS_ERR, "DP Wrong MAX LANE COUNT : %x\n", temp); |
| 231 | return -1; |
| 232 | } |
| 233 | |
Ronald G. Minnich | 71e1c83 | 2013-08-27 14:06:19 -0700 | [diff] [blame] | 234 | if (edp_info->raw_edid){ |
| 235 | ret = EXYNOS_DP_SUCCESS; |
| 236 | printk(BIOS_SPEW, "EDID compiled in, skipping read\n"); |
| 237 | } else { |
| 238 | ret = exynos_dp_read_edid(); |
| 239 | if (ret != EXYNOS_DP_SUCCESS) { |
| 240 | printk(BIOS_ERR, "DP exynos_dp_read_edid() failed\n"); |
| 241 | return -1; |
| 242 | } |
Ronald G. Minnich | c0d5eb2 | 2013-08-01 11:38:05 -0700 | [diff] [blame] | 243 | } |
| 244 | |
| 245 | return ret; |
| 246 | } |
| 247 | |
| 248 | static void exynos_dp_init_training(void) |
| 249 | { |
| 250 | /* |
| 251 | * MACRO_RST must be applied after the PLL_LOCK to avoid |
| 252 | * the DP inter pair skew issue for at least 10 us |
| 253 | */ |
| 254 | exynos_dp_reset_macro(); |
| 255 | |
| 256 | /* All DP analog module power up */ |
| 257 | exynos_dp_set_analog_power_down(POWER_ALL, 0); |
| 258 | } |
| 259 | |
| 260 | static unsigned int exynos_dp_link_start(struct edp_device_info *edp_info) |
| 261 | { |
| 262 | unsigned char buf[5]; |
| 263 | unsigned int ret; |
| 264 | |
| 265 | edp_info->lt_info.lt_status = DP_LT_CR; |
| 266 | edp_info->lt_info.ep_loop = 0; |
| 267 | edp_info->lt_info.cr_loop[0] = 0; |
| 268 | edp_info->lt_info.cr_loop[1] = 0; |
| 269 | edp_info->lt_info.cr_loop[2] = 0; |
| 270 | edp_info->lt_info.cr_loop[3] = 0; |
| 271 | |
| 272 | /* Set sink to D0 (Sink Not Ready) mode. */ |
| 273 | ret = exynos_dp_write_byte_to_dpcd(DPCD_SINK_POWER_STATE, |
| 274 | DPCD_SET_POWER_STATE_D0); |
| 275 | if (ret != EXYNOS_DP_SUCCESS) { |
| 276 | printk(BIOS_ERR, "DP write_dpcd_byte failed\n"); |
| 277 | return ret; |
| 278 | } |
| 279 | |
| 280 | /* Set link rate and count as you want to establish*/ |
| 281 | exynos_dp_set_link_bandwidth(edp_info->lane_bw); |
| 282 | exynos_dp_set_lane_count(edp_info->lane_cnt); |
| 283 | |
| 284 | /* Setup RX configuration */ |
| 285 | buf[0] = edp_info->lane_bw; |
| 286 | buf[1] = edp_info->lane_cnt; |
| 287 | |
| 288 | ret = exynos_dp_write_bytes_to_dpcd(DPCD_LINK_BW_SET, 2, |
| 289 | buf); |
| 290 | if (ret != EXYNOS_DP_SUCCESS) { |
| 291 | printk(BIOS_ERR, "DP write_dpcd_byte failed\n"); |
| 292 | return ret; |
| 293 | } |
| 294 | |
| 295 | exynos_dp_set_lane_pre_emphasis(PRE_EMPHASIS_LEVEL_0, |
| 296 | edp_info->lane_cnt); |
| 297 | |
| 298 | /* Set training pattern 1 */ |
| 299 | exynos_dp_set_training_pattern(TRAINING_PTN1); |
| 300 | |
| 301 | /* Set RX training pattern */ |
| 302 | buf[0] = DPCD_SCRAMBLING_DISABLED | DPCD_TRAINING_PATTERN_1; |
| 303 | |
| 304 | buf[1] = DPCD_PRE_EMPHASIS_SET_PATTERN_2_LEVEL_0 | |
| 305 | DPCD_VOLTAGE_SWING_SET_PATTERN_1_LEVEL_0; |
| 306 | buf[2] = DPCD_PRE_EMPHASIS_SET_PATTERN_2_LEVEL_0 | |
| 307 | DPCD_VOLTAGE_SWING_SET_PATTERN_1_LEVEL_0; |
| 308 | buf[3] = DPCD_PRE_EMPHASIS_SET_PATTERN_2_LEVEL_0 | |
| 309 | DPCD_VOLTAGE_SWING_SET_PATTERN_1_LEVEL_0; |
| 310 | buf[4] = DPCD_PRE_EMPHASIS_SET_PATTERN_2_LEVEL_0 | |
| 311 | DPCD_VOLTAGE_SWING_SET_PATTERN_1_LEVEL_0; |
| 312 | |
| 313 | ret = exynos_dp_write_bytes_to_dpcd(DPCD_TRAINING_PATTERN_SET, |
| 314 | 5, buf); |
| 315 | if (ret != EXYNOS_DP_SUCCESS) { |
| 316 | printk(BIOS_ERR, "DP write_dpcd_byte failed\n"); |
| 317 | return ret; |
| 318 | } |
| 319 | return ret; |
| 320 | } |
| 321 | |
| 322 | static unsigned int exynos_dp_training_pattern_dis(void) |
| 323 | { |
| 324 | unsigned int ret; |
| 325 | |
| 326 | exynos_dp_set_training_pattern(DP_NONE); |
| 327 | |
| 328 | ret = exynos_dp_write_byte_to_dpcd(DPCD_TRAINING_PATTERN_SET, |
| 329 | DPCD_TRAINING_PATTERN_DISABLED); |
| 330 | if (ret != EXYNOS_DP_SUCCESS) { |
| 331 | printk(BIOS_ERR, "DP requst_link_traninig_req failed\n"); |
| 332 | return -1; |
| 333 | } |
| 334 | |
| 335 | return ret; |
| 336 | } |
| 337 | |
| 338 | static unsigned int exynos_dp_enable_rx_to_enhanced_mode(unsigned char enable) |
| 339 | { |
| 340 | unsigned char data; |
| 341 | unsigned int ret; |
| 342 | |
| 343 | ret = exynos_dp_read_byte_from_dpcd(DPCD_LANE_COUNT_SET, |
| 344 | &data); |
| 345 | if (ret != EXYNOS_DP_SUCCESS) { |
| 346 | printk(BIOS_ERR, "DP read_from_dpcd failed\n"); |
| 347 | return -1; |
| 348 | } |
| 349 | |
| 350 | if (enable) |
| 351 | data = DPCD_ENHANCED_FRAME_EN | DPCD_LN_COUNT_SET(data); |
| 352 | else |
| 353 | data = DPCD_LN_COUNT_SET(data); |
| 354 | |
| 355 | ret = exynos_dp_write_byte_to_dpcd(DPCD_LANE_COUNT_SET, |
| 356 | data); |
| 357 | if (ret != EXYNOS_DP_SUCCESS) { |
| 358 | printk(BIOS_ERR, "DP write_to_dpcd failed\n"); |
| 359 | return -1; |
| 360 | |
| 361 | } |
| 362 | |
| 363 | return ret; |
| 364 | } |
| 365 | |
| 366 | static unsigned int exynos_dp_set_enhanced_mode(unsigned char enhance_mode) |
| 367 | { |
| 368 | unsigned int ret; |
| 369 | |
| 370 | ret = exynos_dp_enable_rx_to_enhanced_mode(enhance_mode); |
| 371 | if (ret != EXYNOS_DP_SUCCESS) { |
| 372 | printk(BIOS_ERR, "DP rx_enhance_mode failed\n"); |
| 373 | return -1; |
| 374 | } |
| 375 | |
| 376 | exynos_dp_enable_enhanced_mode(enhance_mode); |
| 377 | |
| 378 | return ret; |
| 379 | } |
| 380 | |
| 381 | static int exynos_dp_read_dpcd_lane_stat(struct edp_device_info *edp_info, |
| 382 | unsigned char *status) |
| 383 | { |
| 384 | unsigned int ret, i; |
| 385 | unsigned char buf[2]; |
| 386 | unsigned char lane_stat[DP_LANE_CNT_4] = {0,}; |
| 387 | const unsigned char shift_val[] = {0, 4, 0, 4}; |
| 388 | |
| 389 | ret = exynos_dp_read_bytes_from_dpcd(DPCD_LANE0_1_STATUS, 2, buf); |
| 390 | if (ret != EXYNOS_DP_SUCCESS) { |
| 391 | printk(BIOS_ERR, "DP read lane status failed\n"); |
| 392 | return ret; |
| 393 | } |
| 394 | |
| 395 | for (i = 0; i < edp_info->lane_cnt; i++) { |
| 396 | lane_stat[i] = (buf[(i / 2)] >> shift_val[i]) & 0x0f; |
| 397 | if (lane_stat[0] != lane_stat[i]) { |
| 398 | printk(BIOS_ERR, "Wrong lane status\n"); |
| 399 | return -1; |
| 400 | } |
| 401 | } |
| 402 | |
| 403 | *status = lane_stat[0]; |
| 404 | |
| 405 | return ret; |
| 406 | } |
| 407 | |
| 408 | static unsigned int exynos_dp_read_dpcd_adj_req(unsigned char lane_num, |
| 409 | unsigned char *sw, unsigned char *em) |
| 410 | { |
| 411 | const unsigned char shift_val[] = {0, 4, 0, 4}; |
| 412 | unsigned int ret; |
| 413 | unsigned char buf; |
| 414 | unsigned int dpcd_addr; |
| 415 | |
Martin Roth | 1fc2ba5 | 2014-12-07 14:59:11 -0700 | [diff] [blame] | 416 | /*lane_num value is used as array index, so this range 0 ~ 3 */ |
Ronald G. Minnich | c0d5eb2 | 2013-08-01 11:38:05 -0700 | [diff] [blame] | 417 | dpcd_addr = DPCD_ADJUST_REQUEST_LANE0_1 + (lane_num / 2); |
| 418 | |
| 419 | ret = exynos_dp_read_byte_from_dpcd(dpcd_addr, &buf); |
| 420 | if (ret != EXYNOS_DP_SUCCESS) { |
| 421 | printk(BIOS_ERR, "DP read adjust request failed\n"); |
| 422 | return -1; |
| 423 | } |
| 424 | |
| 425 | *sw = ((buf >> shift_val[lane_num]) & 0x03); |
| 426 | *em = ((buf >> shift_val[lane_num]) & 0x0c) >> 2; |
| 427 | |
| 428 | return ret; |
| 429 | } |
| 430 | |
| 431 | static int exynos_dp_equalizer_err_link(struct edp_device_info *edp_info) |
| 432 | { |
| 433 | int ret; |
| 434 | |
| 435 | ret = exynos_dp_training_pattern_dis(); |
| 436 | if (ret != EXYNOS_DP_SUCCESS) { |
| 437 | printk(BIOS_ERR, "DP training_patter_disable() failed\n"); |
| 438 | edp_info->lt_info.lt_status = DP_LT_FAIL; |
| 439 | } |
| 440 | |
| 441 | ret = exynos_dp_set_enhanced_mode(edp_info->dpcd_efc); |
| 442 | if (ret != EXYNOS_DP_SUCCESS) { |
| 443 | printk(BIOS_ERR, "DP set_enhanced_mode() failed\n"); |
| 444 | edp_info->lt_info.lt_status = DP_LT_FAIL; |
| 445 | } |
| 446 | |
| 447 | return ret; |
| 448 | } |
| 449 | |
| 450 | static int exynos_dp_reduce_link_rate(struct edp_device_info *edp_info) |
| 451 | { |
| 452 | int ret; |
| 453 | |
| 454 | if (edp_info->lane_bw == DP_LANE_BW_2_70) { |
| 455 | edp_info->lane_bw = DP_LANE_BW_1_62; |
| 456 | printk(BIOS_ERR, "DP Change lane bw to 1.62Gbps\n"); |
| 457 | edp_info->lt_info.lt_status = DP_LT_START; |
| 458 | ret = EXYNOS_DP_SUCCESS; |
| 459 | } else { |
| 460 | ret = exynos_dp_training_pattern_dis(); |
| 461 | if (ret != EXYNOS_DP_SUCCESS) |
| 462 | printk(BIOS_ERR, "DP training_patter_disable() failed\n"); |
| 463 | |
| 464 | ret = exynos_dp_set_enhanced_mode(edp_info->dpcd_efc); |
| 465 | if (ret != EXYNOS_DP_SUCCESS) |
| 466 | printk(BIOS_ERR, "DP set_enhanced_mode() failed\n"); |
| 467 | |
| 468 | edp_info->lt_info.lt_status = DP_LT_FAIL; |
| 469 | } |
| 470 | |
| 471 | return ret; |
| 472 | } |
| 473 | |
| 474 | static unsigned int exynos_dp_process_clock_recovery(struct edp_device_info |
| 475 | *edp_info) |
| 476 | { |
| 477 | unsigned int ret; |
| 478 | unsigned char lane_stat; |
| 479 | unsigned char lt_ctl_val[DP_LANE_CNT_4] = {0, }; |
| 480 | unsigned int i; |
| 481 | unsigned char adj_req_sw; |
| 482 | unsigned char adj_req_em; |
| 483 | unsigned char buf[5]; |
| 484 | |
| 485 | mdelay(1); |
| 486 | |
| 487 | ret = exynos_dp_read_dpcd_lane_stat(edp_info, &lane_stat); |
| 488 | if (ret != EXYNOS_DP_SUCCESS) { |
| 489 | printk(BIOS_ERR, "DP read lane status failed\n"); |
| 490 | edp_info->lt_info.lt_status = DP_LT_FAIL; |
| 491 | return ret; |
| 492 | } |
| 493 | |
| 494 | if (lane_stat & DP_LANE_STAT_CR_DONE) { |
| 495 | printk(BIOS_DEBUG,"DP clock Recovery training succeed\n"); |
| 496 | exynos_dp_set_training_pattern(TRAINING_PTN2); |
| 497 | |
| 498 | for (i = 0; i < edp_info->lane_cnt; i++) { |
| 499 | ret = exynos_dp_read_dpcd_adj_req(i, &adj_req_sw, |
| 500 | &adj_req_em); |
| 501 | if (ret != EXYNOS_DP_SUCCESS) { |
| 502 | edp_info->lt_info.lt_status = DP_LT_FAIL; |
| 503 | return ret; |
| 504 | } |
| 505 | |
| 506 | lt_ctl_val[i] = 0; |
| 507 | lt_ctl_val[i] = adj_req_em << 3 | adj_req_sw; |
| 508 | |
| 509 | if ((adj_req_sw == VOLTAGE_LEVEL_3) |
| 510 | || (adj_req_em == PRE_EMPHASIS_LEVEL_3)) { |
| 511 | lt_ctl_val[i] |= MAX_DRIVE_CURRENT_REACH_3 | |
| 512 | MAX_PRE_EMPHASIS_REACH_3; |
| 513 | } |
| 514 | exynos_dp_set_lanex_pre_emphasis(lt_ctl_val[i], i); |
| 515 | } |
| 516 | |
| 517 | buf[0] = DPCD_SCRAMBLING_DISABLED | DPCD_TRAINING_PATTERN_2; |
| 518 | buf[1] = lt_ctl_val[0]; |
| 519 | buf[2] = lt_ctl_val[1]; |
| 520 | buf[3] = lt_ctl_val[2]; |
| 521 | buf[4] = lt_ctl_val[3]; |
| 522 | |
| 523 | ret = exynos_dp_write_bytes_to_dpcd( |
| 524 | DPCD_TRAINING_PATTERN_SET, 5, buf); |
| 525 | if (ret != EXYNOS_DP_SUCCESS) { |
| 526 | printk(BIOS_ERR, "DP write training pattern1 failed\n"); |
| 527 | edp_info->lt_info.lt_status = DP_LT_FAIL; |
| 528 | return ret; |
| 529 | } else |
| 530 | edp_info->lt_info.lt_status = DP_LT_ET; |
| 531 | } else { |
| 532 | for (i = 0; i < edp_info->lane_cnt; i++) { |
| 533 | lt_ctl_val[i] = exynos_dp_get_lanex_pre_emphasis(i); |
| 534 | ret = exynos_dp_read_dpcd_adj_req(i, |
| 535 | &adj_req_sw, &adj_req_em); |
| 536 | if (ret != EXYNOS_DP_SUCCESS) { |
| 537 | printk(BIOS_ERR, "DP read adj req failed\n"); |
| 538 | edp_info->lt_info.lt_status = DP_LT_FAIL; |
| 539 | return ret; |
| 540 | } |
| 541 | |
| 542 | if ((adj_req_sw == VOLTAGE_LEVEL_3) || |
| 543 | (adj_req_em == PRE_EMPHASIS_LEVEL_3)) |
| 544 | ret = exynos_dp_reduce_link_rate(edp_info); |
| 545 | |
| 546 | if ((DRIVE_CURRENT_SET_0_GET(lt_ctl_val[i]) == |
| 547 | adj_req_sw) && |
| 548 | (PRE_EMPHASIS_SET_0_GET(lt_ctl_val[i]) == |
| 549 | adj_req_em)) { |
| 550 | edp_info->lt_info.cr_loop[i]++; |
| 551 | if (edp_info->lt_info.cr_loop[i] == MAX_CR_LOOP) |
| 552 | ret = exynos_dp_reduce_link_rate( |
| 553 | edp_info); |
| 554 | } |
| 555 | |
| 556 | lt_ctl_val[i] = 0; |
| 557 | lt_ctl_val[i] = adj_req_em << 3 | adj_req_sw; |
| 558 | |
| 559 | if ((adj_req_sw == VOLTAGE_LEVEL_3) || |
| 560 | (adj_req_em == PRE_EMPHASIS_LEVEL_3)) { |
| 561 | lt_ctl_val[i] |= MAX_DRIVE_CURRENT_REACH_3 | |
| 562 | MAX_PRE_EMPHASIS_REACH_3; |
| 563 | } |
| 564 | exynos_dp_set_lanex_pre_emphasis(lt_ctl_val[i], i); |
| 565 | } |
| 566 | |
| 567 | ret = exynos_dp_write_bytes_to_dpcd( |
| 568 | DPCD_TRAINING_LANE0_SET, 4, lt_ctl_val); |
| 569 | if (ret != EXYNOS_DP_SUCCESS) { |
| 570 | printk(BIOS_ERR, "DP write training pattern2 failed\n"); |
| 571 | edp_info->lt_info.lt_status = DP_LT_FAIL; |
| 572 | return ret; |
| 573 | } |
| 574 | } |
| 575 | |
| 576 | return ret; |
| 577 | } |
| 578 | |
| 579 | static unsigned int exynos_dp_process_equalizer_training(struct edp_device_info |
| 580 | *edp_info) |
| 581 | { |
| 582 | unsigned int ret; |
| 583 | unsigned char lane_stat, adj_req_sw, adj_req_em, i; |
| 584 | unsigned char lt_ctl_val[DP_LANE_CNT_4] = {0,}; |
| 585 | unsigned char interlane_aligned = 0; |
| 586 | unsigned char f_bw; |
| 587 | unsigned char f_lane_cnt; |
| 588 | unsigned char sink_stat; |
| 589 | |
| 590 | mdelay(1); |
| 591 | |
| 592 | ret = exynos_dp_read_dpcd_lane_stat(edp_info, &lane_stat); |
| 593 | if (ret != EXYNOS_DP_SUCCESS) { |
| 594 | printk(BIOS_ERR, "DP read lane status failed\n"); |
| 595 | edp_info->lt_info.lt_status = DP_LT_FAIL; |
| 596 | return ret; |
| 597 | } |
| 598 | |
| 599 | printk(BIOS_DEBUG,"DP lane stat : %x\n", lane_stat); |
| 600 | |
| 601 | if (lane_stat & DP_LANE_STAT_CR_DONE) { |
| 602 | printk(BIOS_DEBUG, "DP_LANE_STAT_CR_DONE ok\n"); |
| 603 | ret = exynos_dp_read_byte_from_dpcd(DPCD_LN_ALIGN_UPDATED, |
| 604 | &sink_stat); |
| 605 | if (ret != EXYNOS_DP_SUCCESS) { |
| 606 | edp_info->lt_info.lt_status = DP_LT_FAIL; |
| 607 | printk(BIOS_ERR, "DP read DPCD_LN_ALIGN_UPDATED failed\n"); |
| 608 | return ret; |
| 609 | } |
| 610 | |
| 611 | interlane_aligned = (sink_stat & DPCD_INTERLANE_ALIGN_DONE); |
| 612 | printk(BIOS_DEBUG, "interlane_aligned: %d\n", interlane_aligned); |
| 613 | printk(BIOS_DEBUG, "Check %d lanes\n", edp_info->lane_cnt); |
| 614 | |
| 615 | for (i = 0; i < edp_info->lane_cnt; i++) { |
| 616 | ret = exynos_dp_read_dpcd_adj_req(i, |
| 617 | &adj_req_sw, &adj_req_em); |
| 618 | if (ret != EXYNOS_DP_SUCCESS) { |
| 619 | printk(BIOS_ERR, "DP read adj req 1 failed\n"); |
| 620 | edp_info->lt_info.lt_status = DP_LT_FAIL; |
| 621 | |
| 622 | return ret; |
| 623 | } |
| 624 | |
| 625 | lt_ctl_val[i] = 0; |
| 626 | lt_ctl_val[i] = adj_req_em << 3 | adj_req_sw; |
| 627 | |
| 628 | if ((adj_req_sw == VOLTAGE_LEVEL_3) || |
| 629 | (adj_req_em == PRE_EMPHASIS_LEVEL_3)) { |
| 630 | lt_ctl_val[i] |= MAX_DRIVE_CURRENT_REACH_3; |
| 631 | lt_ctl_val[i] |= MAX_PRE_EMPHASIS_REACH_3; |
| 632 | } |
| 633 | } |
| 634 | |
| 635 | if (((lane_stat&DP_LANE_STAT_CE_DONE) && |
| 636 | (lane_stat&DP_LANE_STAT_SYM_LOCK)) |
| 637 | && (interlane_aligned == DPCD_INTERLANE_ALIGN_DONE)) { |
| 638 | printk(BIOS_DEBUG,"DP Equalizer training succeed\n"); |
| 639 | |
| 640 | f_bw = exynos_dp_get_link_bandwidth(); |
| 641 | f_lane_cnt = exynos_dp_get_lane_count(); |
| 642 | |
| 643 | printk(BIOS_DEBUG,"DP final BandWidth : %x\n", f_bw); |
| 644 | printk(BIOS_DEBUG,"DP final Lane Count : %x\n", f_lane_cnt); |
| 645 | |
| 646 | edp_info->lt_info.lt_status = DP_LT_FINISHED; |
| 647 | |
| 648 | exynos_dp_equalizer_err_link(edp_info); |
| 649 | |
| 650 | } else { |
| 651 | edp_info->lt_info.ep_loop++; |
| 652 | |
| 653 | if (edp_info->lt_info.ep_loop > MAX_EQ_LOOP) { |
| 654 | if (edp_info->lane_bw == DP_LANE_BW_2_70) { |
| 655 | ret = exynos_dp_reduce_link_rate( |
| 656 | edp_info); |
| 657 | } else { |
| 658 | edp_info->lt_info.lt_status = |
| 659 | DP_LT_FAIL; |
| 660 | exynos_dp_equalizer_err_link(edp_info); |
| 661 | } |
| 662 | } else { |
| 663 | for (i = 0; i < edp_info->lane_cnt; i++) |
| 664 | exynos_dp_set_lanex_pre_emphasis( |
| 665 | lt_ctl_val[i], i); |
| 666 | |
| 667 | ret = exynos_dp_write_bytes_to_dpcd( |
| 668 | DPCD_TRAINING_LANE0_SET, |
| 669 | 4, lt_ctl_val); |
| 670 | if (ret != EXYNOS_DP_SUCCESS) { |
| 671 | printk(BIOS_ERR, "DP set lt pattern failed\n"); |
| 672 | edp_info->lt_info.lt_status = |
| 673 | DP_LT_FAIL; |
| 674 | exynos_dp_equalizer_err_link(edp_info); |
| 675 | } |
| 676 | } |
| 677 | } |
| 678 | } else if (edp_info->lane_bw == DP_LANE_BW_2_70) { |
| 679 | ret = exynos_dp_reduce_link_rate(edp_info); |
| 680 | } else { |
| 681 | edp_info->lt_info.lt_status = DP_LT_FAIL; |
| 682 | exynos_dp_equalizer_err_link(edp_info); |
| 683 | } |
| 684 | |
| 685 | return ret; |
| 686 | } |
| 687 | |
| 688 | static unsigned int exynos_dp_sw_link_training(struct edp_device_info *edp_info) |
| 689 | { |
| 690 | /* the C compiler is almost smart enough to know this gets set. |
| 691 | * But not quite. |
| 692 | */ |
| 693 | unsigned int ret = 0; |
| 694 | int training_finished; |
| 695 | |
| 696 | /* Turn off unnecessary lane */ |
| 697 | if (edp_info->lane_cnt == 1) |
| 698 | exynos_dp_set_analog_power_down(CH1_BLOCK, 1); |
| 699 | |
| 700 | training_finished = 0; |
| 701 | |
| 702 | edp_info->lt_info.lt_status = DP_LT_START; |
| 703 | |
| 704 | /* Process here */ |
| 705 | while (!training_finished) { |
| 706 | switch (edp_info->lt_info.lt_status) { |
| 707 | case DP_LT_START: |
| 708 | ret = exynos_dp_link_start(edp_info); |
| 709 | if (ret != EXYNOS_DP_SUCCESS) { |
| 710 | printk(BIOS_ERR, "DP LT:link start failed\n"); |
| 711 | training_finished = 1; |
| 712 | } |
| 713 | break; |
| 714 | case DP_LT_CR: |
| 715 | ret = exynos_dp_process_clock_recovery(edp_info); |
| 716 | if (ret != EXYNOS_DP_SUCCESS) { |
| 717 | printk(BIOS_ERR, "DP LT:clock recovery failed\n"); |
| 718 | training_finished = 1; |
| 719 | } |
| 720 | break; |
| 721 | case DP_LT_ET: |
| 722 | ret = exynos_dp_process_equalizer_training(edp_info); |
| 723 | if (ret != EXYNOS_DP_SUCCESS) { |
| 724 | printk(BIOS_ERR, "DP LT:equalizer training failed\n"); |
| 725 | training_finished = 1; |
| 726 | } |
| 727 | break; |
| 728 | case DP_LT_FINISHED: |
| 729 | training_finished = 1; |
| 730 | break; |
| 731 | case DP_LT_FAIL: |
| 732 | printk(BIOS_ERR,"DP: %s: DP_LT_FAIL: failed\n", __func__); |
| 733 | training_finished = 1; |
| 734 | ret = -1; |
| 735 | } |
| 736 | } |
| 737 | |
| 738 | return ret; |
| 739 | } |
| 740 | |
| 741 | static unsigned int exynos_dp_set_link_train(struct edp_device_info *edp_info) |
| 742 | { |
| 743 | unsigned int ret; |
| 744 | |
| 745 | exynos_dp_init_training(); |
| 746 | |
| 747 | ret = exynos_dp_sw_link_training(edp_info); |
| 748 | if (ret != EXYNOS_DP_SUCCESS) |
| 749 | printk(BIOS_ERR, "DP dp_sw_link_traning() failed\n"); |
| 750 | |
| 751 | return ret; |
| 752 | } |
| 753 | |
| 754 | static void exynos_dp_enable_scramble(unsigned int enable) |
| 755 | { |
| 756 | unsigned char data; |
| 757 | |
| 758 | if (enable) { |
| 759 | exynos_dp_enable_scrambling(DP_ENABLE); |
| 760 | |
| 761 | exynos_dp_read_byte_from_dpcd(DPCD_TRAINING_PATTERN_SET, |
| 762 | &data); |
| 763 | exynos_dp_write_byte_to_dpcd(DPCD_TRAINING_PATTERN_SET, |
| 764 | (u8)(data & ~DPCD_SCRAMBLING_DISABLED)); |
| 765 | } else { |
| 766 | exynos_dp_enable_scrambling(DP_DISABLE); |
| 767 | exynos_dp_read_byte_from_dpcd(DPCD_TRAINING_PATTERN_SET, |
| 768 | &data); |
| 769 | exynos_dp_write_byte_to_dpcd(DPCD_TRAINING_PATTERN_SET, |
| 770 | (u8)(data | DPCD_SCRAMBLING_DISABLED)); |
| 771 | } |
| 772 | } |
| 773 | |
| 774 | static unsigned int exynos_dp_config_video(struct edp_device_info *edp_info) |
| 775 | { |
| 776 | unsigned int ret = 0; |
| 777 | unsigned int retry_cnt; |
| 778 | |
| 779 | mdelay(1); |
| 780 | |
| 781 | if (edp_info->video_info.master_mode) { |
| 782 | printk(BIOS_ERR, |
| 783 | "DP does not support master mode: bailing out\n"); |
| 784 | return -1; |
| 785 | } else { |
| 786 | /* debug slave */ |
| 787 | exynos_dp_config_video_slave_mode(&edp_info->video_info); |
| 788 | } |
| 789 | |
| 790 | exynos_dp_set_video_color_format(&edp_info->video_info); |
| 791 | |
| 792 | ret = exynos_dp_get_pll_lock_status(); |
| 793 | if (ret != PLL_LOCKED) { |
| 794 | printk(BIOS_ERR, "DP PLL is not locked yet\n"); |
| 795 | return -1; |
| 796 | } |
| 797 | |
| 798 | if (edp_info->video_info.master_mode == 0) { |
| 799 | retry_cnt = 10; |
| 800 | while (retry_cnt) { |
| 801 | ret = exynos_dp_is_slave_video_stream_clock_on(); |
| 802 | if (ret != EXYNOS_DP_SUCCESS) { |
| 803 | if (retry_cnt == 0) { |
| 804 | printk(BIOS_ERR, "DP stream_clock_on failed\n"); |
| 805 | return ret; |
| 806 | } |
| 807 | retry_cnt--; |
| 808 | mdelay(1); |
| 809 | } else { |
| 810 | printk(BIOS_DEBUG, "DP stream_clock succeeds\n"); |
| 811 | break; |
| 812 | } |
| 813 | } |
| 814 | } |
| 815 | |
| 816 | /* Set to use the register calculated M/N video */ |
| 817 | exynos_dp_set_video_cr_mn(CALCULATED_M, 0, 0); |
| 818 | |
| 819 | /* For video bist, Video timing must be generated by register |
| 820 | * not clear if we still need this. We could take it out and it |
| 821 | * might appear to work, then fail strangely. |
| 822 | */ |
| 823 | exynos_dp_set_video_timing_mode(VIDEO_TIMING_FROM_CAPTURE); |
| 824 | |
| 825 | /* we need to be sure this is off. */ |
| 826 | exynos_dp_disable_video_bist(); |
| 827 | |
| 828 | /* Disable video mute */ |
| 829 | exynos_dp_enable_video_mute(DP_DISABLE); |
| 830 | |
| 831 | /* Configure video Master or Slave mode */ |
| 832 | exynos_dp_enable_video_master(edp_info->video_info.master_mode); |
| 833 | |
| 834 | /* Enable video */ |
| 835 | exynos_dp_start_video(); |
| 836 | |
| 837 | if (edp_info->video_info.master_mode == 0) { |
Ronald G. Minnich | cff6667 | 2013-08-29 09:16:25 -0700 | [diff] [blame] | 838 | retry_cnt = 500; |
Ronald G. Minnich | c0d5eb2 | 2013-08-01 11:38:05 -0700 | [diff] [blame] | 839 | while (retry_cnt) { |
| 840 | ret = exynos_dp_is_video_stream_on(); |
| 841 | if (ret != EXYNOS_DP_SUCCESS) { |
| 842 | retry_cnt--; |
| 843 | if (retry_cnt == 0) { |
| 844 | printk(BIOS_ERR, "DP Timeout of video stream\n"); |
| 845 | } |
| 846 | } else { |
| 847 | printk(BIOS_DEBUG, "DP video stream is on\n"); |
| 848 | break; |
| 849 | } |
Ronald G. Minnich | cff6667 | 2013-08-29 09:16:25 -0700 | [diff] [blame] | 850 | /* this is a cheap operation, involving some register |
| 851 | * reads, and no AUX channel IO. A ms. delay is fine. |
| 852 | */ |
| 853 | mdelay(1); |
Ronald G. Minnich | c0d5eb2 | 2013-08-01 11:38:05 -0700 | [diff] [blame] | 854 | } |
| 855 | } |
| 856 | |
| 857 | return ret; |
| 858 | } |
| 859 | |
| 860 | int exynos_init_dp(struct edp_device_info *edp_info) |
| 861 | { |
| 862 | unsigned int ret; |
| 863 | |
| 864 | |
| 865 | dp_phy_control(1); |
| 866 | |
| 867 | ret = exynos_dp_init_dp(); |
| 868 | if (ret != EXYNOS_DP_SUCCESS) { |
| 869 | printk(BIOS_ERR, "DP exynos_dp_init_dp() failed\n"); |
| 870 | return ret; |
| 871 | } |
| 872 | |
| 873 | ret = exynos_dp_handle_edid(edp_info); |
| 874 | if (ret != EXYNOS_DP_SUCCESS) { |
| 875 | printk(BIOS_ERR, "EDP handle_edid fail\n"); |
| 876 | return ret; |
| 877 | } |
| 878 | |
| 879 | ret = exynos_dp_set_link_train(edp_info); |
| 880 | if (ret != EXYNOS_DP_SUCCESS) { |
| 881 | printk(BIOS_ERR, "DP link training fail\n"); |
| 882 | return ret; |
| 883 | } |
| 884 | printk(BIOS_DEBUG, "EDP link training ok\n"); |
| 885 | |
| 886 | exynos_dp_enable_scramble(DP_ENABLE); |
| 887 | exynos_dp_enable_rx_to_enhanced_mode(DP_ENABLE); |
| 888 | exynos_dp_enable_enhanced_mode(DP_ENABLE); |
| 889 | |
| 890 | exynos_dp_set_link_bandwidth(edp_info->lane_bw); |
| 891 | exynos_dp_set_lane_count(edp_info->lane_cnt); |
| 892 | |
| 893 | exynos_dp_init_video(); |
| 894 | ret = exynos_dp_config_video(edp_info); |
| 895 | |
| 896 | if (ret != EXYNOS_DP_SUCCESS) { |
| 897 | printk(BIOS_ERR, "Exynos DP init failed\n"); |
| 898 | return ret; |
| 899 | } |
| 900 | printk(BIOS_DEBUG, "Exynos DP init done\n"); |
| 901 | |
| 902 | return ret; |
| 903 | } |