blob: 8e517741e351e2f6b4ad2b667b37f24649a2e872 [file] [log] [blame]
Gabe Black607c0b62013-05-16 05:45:57 -07001/*
2 * This file is part of the coreboot project.
3 *
4 * Copyright 2013 Google Inc.
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; version 2 of the License.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
Gabe Black607c0b62013-05-16 05:45:57 -070014 */
15
Gabe Blackee4bfbf2013-08-13 21:05:43 -070016#include <arch/cache.h>
Julius Werner80af4422014-10-20 13:18:56 -070017#include <bootblock_common.h>
18#include <soc/clk.h>
19#include <soc/wakeup.h>
20#include <soc/cpu.h>
Gabe Black607c0b62013-05-16 05:45:57 -070021
Gabe Blackee4bfbf2013-08-13 21:05:43 -070022/* convenient shorthand (in MB) */
Julius Wernerf0cd03c2013-09-19 20:15:45 -070023#define SRAM_START (EXYNOS5_SRAM_BASE >> 20)
Gabe Blackee4bfbf2013-08-13 21:05:43 -070024#define SRAM_SIZE 1
25#define SRAM_END (SRAM_START + SRAM_SIZE) /* plus one... */
26
Vadim Bendebury0b341b32014-04-23 11:09:44 -070027void bootblock_soc_init(void)
Gabe Black607c0b62013-05-16 05:45:57 -070028{
Gabe Black607c0b62013-05-16 05:45:57 -070029 if (get_wakeup_state() == WAKEUP_DIRECT) {
30 wakeup();
31 /* Never returns. */
32 }
33
Gabe Blackee4bfbf2013-08-13 21:05:43 -070034 /* set up dcache and MMU */
35 mmu_init();
Julius Wernerf0cd03c2013-09-19 20:15:45 -070036 mmu_disable_range(0, SRAM_START);
Gabe Blackee4bfbf2013-08-13 21:05:43 -070037 mmu_config_range(SRAM_START, SRAM_SIZE, DCACHE_WRITEBACK);
38 mmu_config_range(SRAM_END, 4096 - SRAM_END, DCACHE_OFF);
Gabe Blackee4bfbf2013-08-13 21:05:43 -070039 dcache_mmu_enable();
40
Gabe Black607c0b62013-05-16 05:45:57 -070041 /* For most ARM systems, we have to initialize firmware media source
42 * (ex, SPI, SD/MMC, or eMMC) now; but for Exynos platform, that is
43 * already handled by iROM so there's no need to setup again.
44 */
Gabe Black607c0b62013-05-16 05:45:57 -070045}