David Hendricks | 90a7009 | 2013-04-18 14:01:45 -0700 | [diff] [blame] | 1 | /* |
Stefan Reinauer | 08dc357 | 2013-05-14 16:57:50 -0700 | [diff] [blame] | 2 | * This file is part of the coreboot project. |
David Hendricks | 90a7009 | 2013-04-18 14:01:45 -0700 | [diff] [blame] | 3 | * |
Stefan Reinauer | 08dc357 | 2013-05-14 16:57:50 -0700 | [diff] [blame] | 4 | * Copyright (C) 2012 Samsung Electronics |
| 5 | * Copyright 2013 Google Inc. |
David Hendricks | 90a7009 | 2013-04-18 14:01:45 -0700 | [diff] [blame] | 6 | * |
| 7 | * This program is free software; you can redistribute it and/or modify |
Stefan Reinauer | 08dc357 | 2013-05-14 16:57:50 -0700 | [diff] [blame] | 8 | * it under the terms of the GNU General Public License as published by |
| 9 | * the Free Software Foundation; version 2 of the License. |
| 10 | * |
| 11 | * This program is distributed in the hope that it will be useful, |
| 12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 14 | * GNU General Public License for more details. |
David Hendricks | 90a7009 | 2013-04-18 14:01:45 -0700 | [diff] [blame] | 15 | */ |
| 16 | |
Stefan Reinauer | 08dc357 | 2013-05-14 16:57:50 -0700 | [diff] [blame] | 17 | /* EXYNOS - Thermal Management Unit */ |
David Hendricks | cd14ed7 | 2013-04-18 14:21:15 -0700 | [diff] [blame] | 18 | |
Stefan Reinauer | 08dc357 | 2013-05-14 16:57:50 -0700 | [diff] [blame] | 19 | #include <arch/io.h> |
Julius Werner | 1ed0c8c | 2014-10-20 13:16:29 -0700 | [diff] [blame] | 20 | #include <console/console.h> |
| 21 | #include <soc/power.h> |
| 22 | #include <soc/tmu.h> |
David Hendricks | 90a7009 | 2013-04-18 14:01:45 -0700 | [diff] [blame] | 23 | |
| 24 | #define TRIMINFO_RELOAD 1 |
| 25 | #define CORE_EN 1 |
| 26 | #define THERM_TRIP_EN (1 << 12) |
| 27 | |
| 28 | #define INTEN_RISE0 1 |
| 29 | #define INTEN_RISE1 (1 << 4) |
| 30 | #define INTEN_RISE2 (1 << 8) |
| 31 | #define INTEN_FALL0 (1 << 16) |
| 32 | #define INTEN_FALL1 (1 << 20) |
| 33 | #define INTEN_FALL2 (1 << 24) |
| 34 | |
| 35 | #define TRIM_INFO_MASK 0xff |
| 36 | |
| 37 | #define INTCLEAR_RISE0 1 |
| 38 | #define INTCLEAR_RISE1 (1 << 4) |
| 39 | #define INTCLEAR_RISE2 (1 << 8) |
| 40 | #define INTCLEAR_FALL0 (1 << 16) |
| 41 | #define INTCLEAR_FALL1 (1 << 20) |
| 42 | #define INTCLEAR_FALL2 (1 << 24) |
| 43 | #define INTCLEARALL (INTCLEAR_RISE0 | INTCLEAR_RISE1 | \ |
| 44 | INTCLEAR_RISE2 | INTCLEAR_FALL0 | \ |
| 45 | INTCLEAR_FALL1 | INTCLEAR_FALL2) |
| 46 | |
Stefan Reinauer | 08dc357 | 2013-05-14 16:57:50 -0700 | [diff] [blame] | 47 | struct tmu_info exynos5250_tmu_info = { |
| 48 | .tmu_base = 0x10060000, |
| 49 | .tmu_mux = 6, |
| 50 | .data = { |
| 51 | .ts = { |
| 52 | .min_val = 25, |
| 53 | .max_val = 125, |
| 54 | .start_warning = 95, |
| 55 | .start_tripping = 105, |
| 56 | .hardware_tripping = 110, |
| 57 | }, |
| 58 | .efuse_min_value = 40, |
| 59 | .efuse_value = 55, |
| 60 | .efuse_max_value = 100, |
| 61 | .slope = 0x10008802, |
| 62 | }, |
| 63 | .dc_value = 25, |
| 64 | }; |
| 65 | |
David Hendricks | 90a7009 | 2013-04-18 14:01:45 -0700 | [diff] [blame] | 66 | /* |
| 67 | * After reading temperature code from register, compensating |
Martin Roth | 4c3ab73 | 2013-07-08 16:23:54 -0600 | [diff] [blame] | 68 | * its value and calculating celsius temperature, |
| 69 | * get current temperature. |
David Hendricks | 90a7009 | 2013-04-18 14:01:45 -0700 | [diff] [blame] | 70 | * |
| 71 | * @return current temperature of the chip as sensed by TMU |
| 72 | */ |
David Hendricks | cd14ed7 | 2013-04-18 14:21:15 -0700 | [diff] [blame] | 73 | static int get_cur_temp(struct tmu_info *info) |
David Hendricks | 90a7009 | 2013-04-18 14:01:45 -0700 | [diff] [blame] | 74 | { |
| 75 | int cur_temp; |
| 76 | struct tmu_reg *reg = (struct tmu_reg *)info->tmu_base; |
| 77 | |
| 78 | /* Temperature code range between min 25 and max 125 */ |
Julius Werner | 2f37bd6 | 2015-02-19 14:51:15 -0800 | [diff] [blame] | 79 | cur_temp = read32(®->current_temp) & 0xff; |
David Hendricks | 90a7009 | 2013-04-18 14:01:45 -0700 | [diff] [blame] | 80 | |
| 81 | /* Calibrate current temperature */ |
| 82 | if (cur_temp) |
| 83 | cur_temp = cur_temp - info->te1 + info->dc_value; |
| 84 | |
| 85 | return cur_temp; |
| 86 | } |
| 87 | |
| 88 | /* |
| 89 | * Monitors status of the TMU device and exynos temperature |
| 90 | * |
David Hendricks | cd14ed7 | 2013-04-18 14:21:15 -0700 | [diff] [blame] | 91 | * @info TMU info |
| 92 | * @temp pointer to the current temperature value |
David Hendricks | 90a7009 | 2013-04-18 14:01:45 -0700 | [diff] [blame] | 93 | * @return enum tmu_status_t value, code indicating event to execute |
| 94 | */ |
David Hendricks | cd14ed7 | 2013-04-18 14:21:15 -0700 | [diff] [blame] | 95 | enum tmu_status_t tmu_monitor(struct tmu_info *info, int *temp) |
David Hendricks | 90a7009 | 2013-04-18 14:01:45 -0700 | [diff] [blame] | 96 | { |
David Hendricks | cd14ed7 | 2013-04-18 14:21:15 -0700 | [diff] [blame] | 97 | if (info->tmu_state == TMU_STATUS_INIT) |
David Hendricks | 90a7009 | 2013-04-18 14:01:45 -0700 | [diff] [blame] | 98 | return -1; |
| 99 | |
| 100 | int cur_temp; |
David Hendricks | cd14ed7 | 2013-04-18 14:21:15 -0700 | [diff] [blame] | 101 | struct tmu_data *data = &info->data; |
David Hendricks | 90a7009 | 2013-04-18 14:01:45 -0700 | [diff] [blame] | 102 | |
| 103 | /* Read current temperature of the SOC */ |
David Hendricks | cd14ed7 | 2013-04-18 14:21:15 -0700 | [diff] [blame] | 104 | cur_temp = get_cur_temp(info); |
David Hendricks | 90a7009 | 2013-04-18 14:01:45 -0700 | [diff] [blame] | 105 | *temp = cur_temp; |
| 106 | |
| 107 | /* Temperature code lies between min 25 and max 125 */ |
| 108 | if (cur_temp >= data->ts.start_tripping && |
| 109 | cur_temp <= data->ts.max_val) |
| 110 | return TMU_STATUS_TRIPPED; |
| 111 | else if (cur_temp >= data->ts.start_warning) |
| 112 | return TMU_STATUS_WARNING; |
| 113 | else if (cur_temp < data->ts.start_warning && |
| 114 | cur_temp >= data->ts.min_val) |
| 115 | return TMU_STATUS_NORMAL; |
| 116 | /* Temperature code does not lie between min 25 and max 125 */ |
| 117 | else { |
David Hendricks | cd14ed7 | 2013-04-18 14:21:15 -0700 | [diff] [blame] | 118 | info->tmu_state = TMU_STATUS_INIT; |
| 119 | printk(BIOS_DEBUG, "EXYNOS_TMU: Thermal reading failed\n"); |
David Hendricks | 90a7009 | 2013-04-18 14:01:45 -0700 | [diff] [blame] | 120 | return -1; |
| 121 | } |
| 122 | return 0; |
| 123 | } |
| 124 | |
| 125 | /* |
David Hendricks | 90a7009 | 2013-04-18 14:01:45 -0700 | [diff] [blame] | 126 | * Calibrate and calculate threshold values and |
| 127 | * enable interrupt levels |
| 128 | * |
| 129 | * @param info pointer to the tmu_info struct |
| 130 | */ |
David Hendricks | cd14ed7 | 2013-04-18 14:21:15 -0700 | [diff] [blame] | 131 | static void tmu_setup_parameters(struct tmu_info *info) |
David Hendricks | 90a7009 | 2013-04-18 14:01:45 -0700 | [diff] [blame] | 132 | { |
| 133 | unsigned int te_temp, con; |
| 134 | unsigned int warning_code, trip_code, hwtrip_code; |
| 135 | unsigned int cooling_temp; |
| 136 | unsigned int rising_value; |
| 137 | struct tmu_data *data = &info->data; |
| 138 | struct tmu_reg *reg = (struct tmu_reg *)info->tmu_base; |
| 139 | |
| 140 | /* Must reload for using efuse value at EXYNOS */ |
Julius Werner | 2f37bd6 | 2015-02-19 14:51:15 -0800 | [diff] [blame] | 141 | write32(®->triminfo_control, TRIMINFO_RELOAD); |
David Hendricks | 90a7009 | 2013-04-18 14:01:45 -0700 | [diff] [blame] | 142 | |
| 143 | /* Get the compensation parameter */ |
Julius Werner | 2f37bd6 | 2015-02-19 14:51:15 -0800 | [diff] [blame] | 144 | te_temp = read32(®->triminfo); |
David Hendricks | 90a7009 | 2013-04-18 14:01:45 -0700 | [diff] [blame] | 145 | info->te1 = te_temp & TRIM_INFO_MASK; |
| 146 | info->te2 = ((te_temp >> 8) & TRIM_INFO_MASK); |
| 147 | |
| 148 | if ((data->efuse_min_value > info->te1) || |
| 149 | (info->te1 > data->efuse_max_value) |
| 150 | || (info->te2 != 0)) |
| 151 | info->te1 = data->efuse_value; |
| 152 | |
| 153 | /* Get RISING & FALLING Threshold value */ |
| 154 | warning_code = data->ts.start_warning |
| 155 | + info->te1 - info->dc_value; |
| 156 | trip_code = data->ts.start_tripping |
| 157 | + info->te1 - info->dc_value; |
| 158 | hwtrip_code = data->ts.hardware_tripping |
| 159 | + info->te1 - info->dc_value; |
| 160 | |
| 161 | cooling_temp = 0; |
| 162 | |
| 163 | rising_value = ((warning_code << 8) | |
| 164 | (trip_code << 16) | |
| 165 | (hwtrip_code << 24)); |
| 166 | |
| 167 | /* Set interrupt level */ |
Julius Werner | 2f37bd6 | 2015-02-19 14:51:15 -0800 | [diff] [blame] | 168 | write32(®->threshold_temp_rise, rising_value); |
| 169 | write32(®->threshold_temp_fall, cooling_temp); |
David Hendricks | 90a7009 | 2013-04-18 14:01:45 -0700 | [diff] [blame] | 170 | |
| 171 | /* |
| 172 | * Need to init all register settings after getting parameter info |
| 173 | * [28:23] vref [11:8] slope - Tuning parameter |
| 174 | * |
| 175 | * WARNING: this slope value writes into many bits in the tmu_control |
| 176 | * register, with the default FDT value of 268470274 (0x10008802) |
| 177 | * we are using this essentially sets the default register setting |
| 178 | * from the TRM for tmu_control. |
| 179 | * TODO(bhthompson): rewrite this code such that we are not performing |
| 180 | * a hard wipe of tmu_control and re verify functionality. |
| 181 | */ |
Julius Werner | 2f37bd6 | 2015-02-19 14:51:15 -0800 | [diff] [blame] | 182 | write32(®->tmu_control, data->slope); |
David Hendricks | 90a7009 | 2013-04-18 14:01:45 -0700 | [diff] [blame] | 183 | |
Julius Werner | 2f37bd6 | 2015-02-19 14:51:15 -0800 | [diff] [blame] | 184 | write32(®->intclear, INTCLEARALL); |
David Hendricks | 90a7009 | 2013-04-18 14:01:45 -0700 | [diff] [blame] | 185 | /* TMU core enable */ |
Julius Werner | 2f37bd6 | 2015-02-19 14:51:15 -0800 | [diff] [blame] | 186 | con = read32(®->tmu_control); |
David Hendricks | 90a7009 | 2013-04-18 14:01:45 -0700 | [diff] [blame] | 187 | con |= (info->tmu_mux << 20) | THERM_TRIP_EN | CORE_EN; |
| 188 | |
Julius Werner | 2f37bd6 | 2015-02-19 14:51:15 -0800 | [diff] [blame] | 189 | write32(®->tmu_control, con); |
David Hendricks | 90a7009 | 2013-04-18 14:01:45 -0700 | [diff] [blame] | 190 | |
| 191 | /* Enable HW thermal trip */ |
| 192 | power_enable_hw_thermal_trip(); |
| 193 | |
| 194 | /* LEV1 LEV2 interrupt enable */ |
Julius Werner | 2f37bd6 | 2015-02-19 14:51:15 -0800 | [diff] [blame] | 195 | write32(®->inten, INTEN_RISE1 | INTEN_RISE2); |
David Hendricks | 90a7009 | 2013-04-18 14:01:45 -0700 | [diff] [blame] | 196 | } |
| 197 | |
| 198 | /* |
| 199 | * Initialize TMU device |
| 200 | * |
David Hendricks | 90a7009 | 2013-04-18 14:01:45 -0700 | [diff] [blame] | 201 | * @return int value, 0 for success |
| 202 | */ |
David Hendricks | cd14ed7 | 2013-04-18 14:21:15 -0700 | [diff] [blame] | 203 | int tmu_init(struct tmu_info *info) |
David Hendricks | 90a7009 | 2013-04-18 14:01:45 -0700 | [diff] [blame] | 204 | { |
David Hendricks | cd14ed7 | 2013-04-18 14:21:15 -0700 | [diff] [blame] | 205 | info->tmu_state = TMU_STATUS_INIT; |
David Hendricks | 90a7009 | 2013-04-18 14:01:45 -0700 | [diff] [blame] | 206 | |
David Hendricks | cd14ed7 | 2013-04-18 14:21:15 -0700 | [diff] [blame] | 207 | tmu_setup_parameters(info); |
| 208 | info->tmu_state = TMU_STATUS_NORMAL; |
David Hendricks | 90a7009 | 2013-04-18 14:01:45 -0700 | [diff] [blame] | 209 | |
| 210 | return 0; |
| 211 | } |