Stefan Reinauer | 9fe20cb | 2012-12-07 17:18:43 -0800 | [diff] [blame] | 1 | /* |
Stefan Reinauer | 08dc357 | 2013-05-14 16:57:50 -0700 | [diff] [blame] | 2 | * This file is part of the coreboot project. |
Stefan Reinauer | 9fe20cb | 2012-12-07 17:18:43 -0800 | [diff] [blame] | 3 | * |
| 4 | * Copyright (C) 2012 Samsung Electronics |
| 5 | * |
Stefan Reinauer | 08dc357 | 2013-05-14 16:57:50 -0700 | [diff] [blame] | 6 | * This program is free software; you can redistribute it and/or modify |
| 7 | * it under the terms of the GNU General Public License as published by |
| 8 | * the Free Software Foundation; version 2 of the License. |
Stefan Reinauer | 9fe20cb | 2012-12-07 17:18:43 -0800 | [diff] [blame] | 9 | * |
| 10 | * This program is distributed in the hope that it will be useful, |
| 11 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 12 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 13 | * GNU General Public License for more details. |
Stefan Reinauer | 9fe20cb | 2012-12-07 17:18:43 -0800 | [diff] [blame] | 14 | */ |
| 15 | |
Stefan Reinauer | 08dc357 | 2013-05-14 16:57:50 -0700 | [diff] [blame] | 16 | /* DDR3 mem setup file for SMDK5250 board based on EXYNOS5 */ |
| 17 | |
Stefan Reinauer | 9fe20cb | 2012-12-07 17:18:43 -0800 | [diff] [blame] | 18 | #include <arch/io.h> |
Julius Werner | fa938c7 | 2013-08-29 14:17:36 -0700 | [diff] [blame] | 19 | #include <console/console.h> |
Julius Werner | 1ed0c8c | 2014-10-20 13:16:29 -0700 | [diff] [blame] | 20 | #include <delay.h> |
| 21 | #include <soc/clk.h> |
| 22 | #include <soc/cpu.h> |
| 23 | #include <soc/dmc.h> |
| 24 | #include <soc/setup.h> |
Stefan Reinauer | 9fe20cb | 2012-12-07 17:18:43 -0800 | [diff] [blame] | 25 | |
| 26 | #define RDLVL_COMPLETE_TIMEOUT 10000 |
| 27 | |
| 28 | static void reset_phy_ctrl(void) |
| 29 | { |
Julius Werner | 2f37bd6 | 2015-02-19 14:51:15 -0800 | [diff] [blame] | 30 | write32(&exynos_clock->lpddr3phy_ctrl, |
| 31 | LPDDR3PHY_CTRL_PHY_RESET_ENABLE); |
| 32 | write32(&exynos_clock->lpddr3phy_ctrl, |
| 33 | LPDDR3PHY_CTRL_PHY_RESET_DISABLE); |
Stefan Reinauer | 9fe20cb | 2012-12-07 17:18:43 -0800 | [diff] [blame] | 34 | |
David Hendricks | 1fb11d1 | 2013-04-12 15:11:05 -0700 | [diff] [blame] | 35 | #if 0 |
Stefan Reinauer | 9fe20cb | 2012-12-07 17:18:43 -0800 | [diff] [blame] | 36 | /* |
| 37 | * For proper memory initialization there should be a minimum delay of |
| 38 | * 500us after the LPDDR3PHY_CTRL_PHY_RESET signal. |
| 39 | * The below value is an approximate value whose calculation in done |
| 40 | * considering that sdelay takes 2 instruction for every 1 delay cycle. |
| 41 | * And assuming each instruction takes 1 clock cycle i.e 1/(1.7 Ghz)sec |
| 42 | * So for 500 usec, the number of delay cycle should be |
| 43 | * (500 * 10^-6) * (1.7 * 10^9) / 2 = 425000 |
| 44 | * |
| 45 | * TODO(hatim.rv@samsung.com): Implement the delay using timer/counter |
| 46 | */ |
| 47 | sdelay(425000); |
David Hendricks | 1fb11d1 | 2013-04-12 15:11:05 -0700 | [diff] [blame] | 48 | #endif |
| 49 | udelay(500); |
Stefan Reinauer | 9fe20cb | 2012-12-07 17:18:43 -0800 | [diff] [blame] | 50 | } |
| 51 | |
Hung-Te Lin | 55c753d | 2013-04-25 16:14:19 +0800 | [diff] [blame] | 52 | int ddr3_mem_ctrl_init(struct mem_timings *mem, unsigned long mem_iv_size, |
| 53 | int mem_reset) |
Stefan Reinauer | 9fe20cb | 2012-12-07 17:18:43 -0800 | [diff] [blame] | 54 | { |
| 55 | unsigned int val; |
Stefan Reinauer | 9fe20cb | 2012-12-07 17:18:43 -0800 | [diff] [blame] | 56 | int i; |
| 57 | |
Ronald G. Minnich | 6da7046 | 2013-06-26 09:51:21 -0700 | [diff] [blame] | 58 | if (mem_reset) |
Hung-Te Lin | 55c753d | 2013-04-25 16:14:19 +0800 | [diff] [blame] | 59 | reset_phy_ctrl(); |
Stefan Reinauer | 9fe20cb | 2012-12-07 17:18:43 -0800 | [diff] [blame] | 60 | |
| 61 | /* Set Impedance Output Driver */ |
| 62 | val = (mem->impedance << CA_CK_DRVR_DS_OFFSET) | |
| 63 | (mem->impedance << CA_CKE_DRVR_DS_OFFSET) | |
| 64 | (mem->impedance << CA_CS_DRVR_DS_OFFSET) | |
| 65 | (mem->impedance << CA_ADR_DRVR_DS_OFFSET); |
Julius Werner | 2f37bd6 | 2015-02-19 14:51:15 -0800 | [diff] [blame] | 66 | write32(&exynos_phy0_control->phy_con39, val); |
| 67 | write32(&exynos_phy1_control->phy_con39, val); |
Stefan Reinauer | 9fe20cb | 2012-12-07 17:18:43 -0800 | [diff] [blame] | 68 | |
| 69 | /* Set Read Latency and Burst Length for PHY0 and PHY1 */ |
| 70 | val = (mem->ctrl_bstlen << PHY_CON42_CTRL_BSTLEN_SHIFT) | |
| 71 | (mem->ctrl_rdlat << PHY_CON42_CTRL_RDLAT_SHIFT); |
Julius Werner | 2f37bd6 | 2015-02-19 14:51:15 -0800 | [diff] [blame] | 72 | write32(&exynos_phy0_control->phy_con42, val); |
| 73 | write32(&exynos_phy1_control->phy_con42, val); |
Stefan Reinauer | 9fe20cb | 2012-12-07 17:18:43 -0800 | [diff] [blame] | 74 | |
| 75 | /* ZQ Calibration */ |
Julius Werner | fa938c7 | 2013-08-29 14:17:36 -0700 | [diff] [blame] | 76 | if (dmc_config_zq(mem, exynos_phy0_control, exynos_phy1_control)){ |
Ronald G. Minnich | 6da7046 | 2013-06-26 09:51:21 -0700 | [diff] [blame] | 77 | printk(BIOS_EMERG, "DRAM ZQ CALIBRATION FAILURE\n"); |
Stefan Reinauer | 9fe20cb | 2012-12-07 17:18:43 -0800 | [diff] [blame] | 78 | return SETUP_ERR_ZQ_CALIBRATION_FAILURE; |
Ronald G. Minnich | 6da7046 | 2013-06-26 09:51:21 -0700 | [diff] [blame] | 79 | } |
Stefan Reinauer | 9fe20cb | 2012-12-07 17:18:43 -0800 | [diff] [blame] | 80 | |
| 81 | /* DQ Signal */ |
Julius Werner | 2f37bd6 | 2015-02-19 14:51:15 -0800 | [diff] [blame] | 82 | write32(&exynos_phy0_control->phy_con14, mem->phy0_pulld_dqs); |
| 83 | write32(&exynos_phy1_control->phy_con14, mem->phy1_pulld_dqs); |
Stefan Reinauer | 9fe20cb | 2012-12-07 17:18:43 -0800 | [diff] [blame] | 84 | |
Julius Werner | 9418476 | 2015-02-19 20:19:23 -0800 | [diff] [blame] | 85 | write32(&exynos_dmc->concontrol, mem->concontrol | |
| 86 | (mem->rd_fetch << CONCONTROL_RD_FETCH_SHIFT) | |
| 87 | (mem->dfi_init_start << CONCONTROL_DFI_INIT_START_SHIFT)); |
Stefan Reinauer | 9fe20cb | 2012-12-07 17:18:43 -0800 | [diff] [blame] | 88 | |
Julius Werner | fa938c7 | 2013-08-29 14:17:36 -0700 | [diff] [blame] | 89 | update_reset_dll(exynos_dmc, DDR_MODE_DDR3); |
Stefan Reinauer | 9fe20cb | 2012-12-07 17:18:43 -0800 | [diff] [blame] | 90 | |
| 91 | /* DQS Signal */ |
Julius Werner | 2f37bd6 | 2015-02-19 14:51:15 -0800 | [diff] [blame] | 92 | write32(&exynos_phy0_control->phy_con4, mem->phy0_dqs); |
| 93 | write32(&exynos_phy1_control->phy_con4, mem->phy1_dqs); |
Stefan Reinauer | 9fe20cb | 2012-12-07 17:18:43 -0800 | [diff] [blame] | 94 | |
Julius Werner | 2f37bd6 | 2015-02-19 14:51:15 -0800 | [diff] [blame] | 95 | write32(&exynos_phy0_control->phy_con6, mem->phy0_dq); |
| 96 | write32(&exynos_phy1_control->phy_con6, mem->phy1_dq); |
Stefan Reinauer | 9fe20cb | 2012-12-07 17:18:43 -0800 | [diff] [blame] | 97 | |
Julius Werner | 2f37bd6 | 2015-02-19 14:51:15 -0800 | [diff] [blame] | 98 | write32(&exynos_phy0_control->phy_con10, mem->phy0_tFS); |
| 99 | write32(&exynos_phy1_control->phy_con10, mem->phy1_tFS); |
Stefan Reinauer | 9fe20cb | 2012-12-07 17:18:43 -0800 | [diff] [blame] | 100 | |
| 101 | val = (mem->ctrl_start_point << PHY_CON12_CTRL_START_POINT_SHIFT) | |
| 102 | (mem->ctrl_inc << PHY_CON12_CTRL_INC_SHIFT) | |
| 103 | (mem->ctrl_dll_on << PHY_CON12_CTRL_DLL_ON_SHIFT) | |
| 104 | (mem->ctrl_ref << PHY_CON12_CTRL_REF_SHIFT); |
Julius Werner | 2f37bd6 | 2015-02-19 14:51:15 -0800 | [diff] [blame] | 105 | write32(&exynos_phy0_control->phy_con12, val); |
| 106 | write32(&exynos_phy1_control->phy_con12, val); |
Stefan Reinauer | 9fe20cb | 2012-12-07 17:18:43 -0800 | [diff] [blame] | 107 | |
| 108 | /* Start DLL locking */ |
Julius Werner | 2f37bd6 | 2015-02-19 14:51:15 -0800 | [diff] [blame] | 109 | write32(&exynos_phy0_control->phy_con12, |
| 110 | val | (mem->ctrl_start << PHY_CON12_CTRL_START_SHIFT)); |
| 111 | write32(&exynos_phy1_control->phy_con12, |
| 112 | val | (mem->ctrl_start << PHY_CON12_CTRL_START_SHIFT)); |
Stefan Reinauer | 9fe20cb | 2012-12-07 17:18:43 -0800 | [diff] [blame] | 113 | |
Julius Werner | fa938c7 | 2013-08-29 14:17:36 -0700 | [diff] [blame] | 114 | update_reset_dll(exynos_dmc, DDR_MODE_DDR3); |
Stefan Reinauer | 9fe20cb | 2012-12-07 17:18:43 -0800 | [diff] [blame] | 115 | |
Julius Werner | 2f37bd6 | 2015-02-19 14:51:15 -0800 | [diff] [blame] | 116 | write32(&exynos_dmc->concontrol, |
| 117 | mem->concontrol | (mem->rd_fetch << CONCONTROL_RD_FETCH_SHIFT)); |
Stefan Reinauer | 9fe20cb | 2012-12-07 17:18:43 -0800 | [diff] [blame] | 118 | |
Julius Werner | fa938c7 | 2013-08-29 14:17:36 -0700 | [diff] [blame] | 119 | /* Memory Channel Inteleaving Size */ |
Julius Werner | 2f37bd6 | 2015-02-19 14:51:15 -0800 | [diff] [blame] | 120 | write32(&exynos_dmc->ivcontrol, mem->iv_size); |
Stefan Reinauer | 9fe20cb | 2012-12-07 17:18:43 -0800 | [diff] [blame] | 121 | |
| 122 | /* Set DMC MEMCONTROL register */ |
| 123 | val = mem->memcontrol & ~DMC_MEMCONTROL_DSREF_ENABLE; |
Julius Werner | 2f37bd6 | 2015-02-19 14:51:15 -0800 | [diff] [blame] | 124 | write32(&exynos_dmc->memcontrol, val); |
Stefan Reinauer | 9fe20cb | 2012-12-07 17:18:43 -0800 | [diff] [blame] | 125 | |
Julius Werner | 2f37bd6 | 2015-02-19 14:51:15 -0800 | [diff] [blame] | 126 | write32(&exynos_dmc->memconfig0, mem->memconfig); |
| 127 | write32(&exynos_dmc->memconfig1, mem->memconfig); |
| 128 | write32(&exynos_dmc->membaseconfig0, mem->membaseconfig0); |
| 129 | write32(&exynos_dmc->membaseconfig1, mem->membaseconfig1); |
Stefan Reinauer | 9fe20cb | 2012-12-07 17:18:43 -0800 | [diff] [blame] | 130 | |
| 131 | /* Precharge Configuration */ |
Julius Werner | 2f37bd6 | 2015-02-19 14:51:15 -0800 | [diff] [blame] | 132 | write32(&exynos_dmc->prechconfig, |
| 133 | mem->prechconfig_tp_cnt << PRECHCONFIG_TP_CNT_SHIFT); |
Stefan Reinauer | 9fe20cb | 2012-12-07 17:18:43 -0800 | [diff] [blame] | 134 | |
| 135 | /* Power Down mode Configuration */ |
Julius Werner | 2f37bd6 | 2015-02-19 14:51:15 -0800 | [diff] [blame] | 136 | write32(&exynos_dmc->pwrdnconfig, |
Julius Werner | 9418476 | 2015-02-19 20:19:23 -0800 | [diff] [blame] | 137 | mem->dpwrdn_cyc << PWRDNCONFIG_DPWRDN_CYC_SHIFT | |
| 138 | mem->dsref_cyc << PWRDNCONFIG_DSREF_CYC_SHIFT); |
Stefan Reinauer | 9fe20cb | 2012-12-07 17:18:43 -0800 | [diff] [blame] | 139 | |
| 140 | /* TimingRow, TimingData, TimingPower and Timingaref |
| 141 | * values as per Memory AC parameters |
| 142 | */ |
Julius Werner | 2f37bd6 | 2015-02-19 14:51:15 -0800 | [diff] [blame] | 143 | write32(&exynos_dmc->timingref, mem->timing_ref); |
| 144 | write32(&exynos_dmc->timingrow, mem->timing_row); |
| 145 | write32(&exynos_dmc->timingdata, mem->timing_data); |
| 146 | write32(&exynos_dmc->timingpower, mem->timing_power); |
Stefan Reinauer | 9fe20cb | 2012-12-07 17:18:43 -0800 | [diff] [blame] | 147 | |
| 148 | /* Send PALL command */ |
Julius Werner | fa938c7 | 2013-08-29 14:17:36 -0700 | [diff] [blame] | 149 | dmc_config_prech(mem, exynos_dmc); |
Stefan Reinauer | 9fe20cb | 2012-12-07 17:18:43 -0800 | [diff] [blame] | 150 | |
Hung-Te Lin | c0491d4 | 2013-08-06 10:48:48 +0800 | [diff] [blame] | 151 | if (mem_reset) { |
| 152 | /* Send NOP, MRS and ZQINIT commands. |
| 153 | * Sending MRS command will reset the DRAM. We should not be |
| 154 | * reseting the DRAM after resume, this will lead to memory |
| 155 | * corruption as DRAM content is lost after DRAM reset |
| 156 | */ |
Julius Werner | fa938c7 | 2013-08-29 14:17:36 -0700 | [diff] [blame] | 157 | dmc_config_mrs(mem, exynos_dmc); |
Hung-Te Lin | c0491d4 | 2013-08-06 10:48:48 +0800 | [diff] [blame] | 158 | } |
Stefan Reinauer | 9fe20cb | 2012-12-07 17:18:43 -0800 | [diff] [blame] | 159 | |
| 160 | if (mem->gate_leveling_enable) { |
| 161 | val = PHY_CON0_RESET_VAL; |
| 162 | val |= P0_CMD_EN; |
Julius Werner | 2f37bd6 | 2015-02-19 14:51:15 -0800 | [diff] [blame] | 163 | write32(&exynos_phy0_control->phy_con0, val); |
| 164 | write32(&exynos_phy1_control->phy_con0, val); |
Stefan Reinauer | 9fe20cb | 2012-12-07 17:18:43 -0800 | [diff] [blame] | 165 | |
| 166 | val = PHY_CON2_RESET_VAL; |
| 167 | val |= INIT_DESKEW_EN; |
Julius Werner | 2f37bd6 | 2015-02-19 14:51:15 -0800 | [diff] [blame] | 168 | write32(&exynos_phy0_control->phy_con2, val); |
| 169 | write32(&exynos_phy1_control->phy_con2, val); |
Stefan Reinauer | 9fe20cb | 2012-12-07 17:18:43 -0800 | [diff] [blame] | 170 | |
| 171 | val = PHY_CON0_RESET_VAL; |
| 172 | val |= P0_CMD_EN; |
| 173 | val |= BYTE_RDLVL_EN; |
Julius Werner | 2f37bd6 | 2015-02-19 14:51:15 -0800 | [diff] [blame] | 174 | write32(&exynos_phy0_control->phy_con0, val); |
| 175 | write32(&exynos_phy1_control->phy_con0, val); |
Stefan Reinauer | 9fe20cb | 2012-12-07 17:18:43 -0800 | [diff] [blame] | 176 | |
| 177 | val = (mem->ctrl_start_point << |
| 178 | PHY_CON12_CTRL_START_POINT_SHIFT) | |
| 179 | (mem->ctrl_inc << PHY_CON12_CTRL_INC_SHIFT) | |
| 180 | (mem->ctrl_force << PHY_CON12_CTRL_FORCE_SHIFT) | |
| 181 | (mem->ctrl_start << PHY_CON12_CTRL_START_SHIFT) | |
| 182 | (mem->ctrl_ref << PHY_CON12_CTRL_REF_SHIFT); |
Julius Werner | 2f37bd6 | 2015-02-19 14:51:15 -0800 | [diff] [blame] | 183 | write32(&exynos_phy0_control->phy_con12, val); |
| 184 | write32(&exynos_phy1_control->phy_con12, val); |
Stefan Reinauer | 9fe20cb | 2012-12-07 17:18:43 -0800 | [diff] [blame] | 185 | |
| 186 | val = PHY_CON2_RESET_VAL; |
| 187 | val |= INIT_DESKEW_EN; |
| 188 | val |= RDLVL_GATE_EN; |
Julius Werner | 2f37bd6 | 2015-02-19 14:51:15 -0800 | [diff] [blame] | 189 | write32(&exynos_phy0_control->phy_con2, val); |
| 190 | write32(&exynos_phy1_control->phy_con2, val); |
Stefan Reinauer | 9fe20cb | 2012-12-07 17:18:43 -0800 | [diff] [blame] | 191 | |
| 192 | val = PHY_CON0_RESET_VAL; |
| 193 | val |= P0_CMD_EN; |
| 194 | val |= BYTE_RDLVL_EN; |
| 195 | val |= CTRL_SHGATE; |
Julius Werner | 2f37bd6 | 2015-02-19 14:51:15 -0800 | [diff] [blame] | 196 | write32(&exynos_phy0_control->phy_con0, val); |
| 197 | write32(&exynos_phy1_control->phy_con0, val); |
Stefan Reinauer | 9fe20cb | 2012-12-07 17:18:43 -0800 | [diff] [blame] | 198 | |
| 199 | val = PHY_CON1_RESET_VAL; |
| 200 | val &= ~(CTRL_GATEDURADJ_MASK); |
Julius Werner | 2f37bd6 | 2015-02-19 14:51:15 -0800 | [diff] [blame] | 201 | write32(&exynos_phy0_control->phy_con1, val); |
| 202 | write32(&exynos_phy1_control->phy_con1, val); |
Stefan Reinauer | 9fe20cb | 2012-12-07 17:18:43 -0800 | [diff] [blame] | 203 | |
Julius Werner | 2f37bd6 | 2015-02-19 14:51:15 -0800 | [diff] [blame] | 204 | write32(&exynos_dmc->rdlvl_config, CTRL_RDLVL_GATE_ENABLE); |
Stefan Reinauer | 9fe20cb | 2012-12-07 17:18:43 -0800 | [diff] [blame] | 205 | i = RDLVL_COMPLETE_TIMEOUT; |
Julius Werner | 2f37bd6 | 2015-02-19 14:51:15 -0800 | [diff] [blame] | 206 | while ((read32(&exynos_dmc->phystatus) & |
Stefan Reinauer | 9fe20cb | 2012-12-07 17:18:43 -0800 | [diff] [blame] | 207 | (RDLVL_COMPLETE_CHO | RDLVL_COMPLETE_CH1)) != |
| 208 | (RDLVL_COMPLETE_CHO | RDLVL_COMPLETE_CH1) && i > 0) { |
| 209 | /* |
| 210 | * TODO(waihong): Comment on how long this take to |
| 211 | * timeout |
| 212 | */ |
David Hendricks | 1fb11d1 | 2013-04-12 15:11:05 -0700 | [diff] [blame] | 213 | udelay(1); |
Stefan Reinauer | 9fe20cb | 2012-12-07 17:18:43 -0800 | [diff] [blame] | 214 | i--; |
| 215 | } |
Ronald G. Minnich | 88e4691 | 2013-01-29 14:16:35 -0800 | [diff] [blame] | 216 | if (!i){ |
Ronald G. Minnich | 6da7046 | 2013-06-26 09:51:21 -0700 | [diff] [blame] | 217 | printk(BIOS_EMERG, "Timeout on RDLVL. No DRAM.\n"); |
Stefan Reinauer | 9fe20cb | 2012-12-07 17:18:43 -0800 | [diff] [blame] | 218 | return SETUP_ERR_RDLV_COMPLETE_TIMEOUT; |
Ronald G. Minnich | 88e4691 | 2013-01-29 14:16:35 -0800 | [diff] [blame] | 219 | } |
Julius Werner | 2f37bd6 | 2015-02-19 14:51:15 -0800 | [diff] [blame] | 220 | write32(&exynos_dmc->rdlvl_config, CTRL_RDLVL_GATE_DISABLE); |
Stefan Reinauer | 9fe20cb | 2012-12-07 17:18:43 -0800 | [diff] [blame] | 221 | |
Julius Werner | 2f37bd6 | 2015-02-19 14:51:15 -0800 | [diff] [blame] | 222 | write32(&exynos_phy0_control->phy_con14, 0); |
| 223 | write32(&exynos_phy1_control->phy_con14, 0); |
Stefan Reinauer | 9fe20cb | 2012-12-07 17:18:43 -0800 | [diff] [blame] | 224 | |
| 225 | val = (mem->ctrl_start_point << |
| 226 | PHY_CON12_CTRL_START_POINT_SHIFT) | |
| 227 | (mem->ctrl_inc << PHY_CON12_CTRL_INC_SHIFT) | |
| 228 | (mem->ctrl_force << PHY_CON12_CTRL_FORCE_SHIFT) | |
| 229 | (mem->ctrl_start << PHY_CON12_CTRL_START_SHIFT) | |
| 230 | (mem->ctrl_dll_on << PHY_CON12_CTRL_DLL_ON_SHIFT) | |
| 231 | (mem->ctrl_ref << PHY_CON12_CTRL_REF_SHIFT); |
Julius Werner | 2f37bd6 | 2015-02-19 14:51:15 -0800 | [diff] [blame] | 232 | write32(&exynos_phy0_control->phy_con12, val); |
| 233 | write32(&exynos_phy1_control->phy_con12, val); |
Stefan Reinauer | 9fe20cb | 2012-12-07 17:18:43 -0800 | [diff] [blame] | 234 | |
Julius Werner | fa938c7 | 2013-08-29 14:17:36 -0700 | [diff] [blame] | 235 | update_reset_dll(exynos_dmc, DDR_MODE_DDR3); |
Stefan Reinauer | 9fe20cb | 2012-12-07 17:18:43 -0800 | [diff] [blame] | 236 | } |
| 237 | |
| 238 | /* Send PALL command */ |
Julius Werner | fa938c7 | 2013-08-29 14:17:36 -0700 | [diff] [blame] | 239 | dmc_config_prech(mem, exynos_dmc); |
Stefan Reinauer | 9fe20cb | 2012-12-07 17:18:43 -0800 | [diff] [blame] | 240 | |
Julius Werner | 2f37bd6 | 2015-02-19 14:51:15 -0800 | [diff] [blame] | 241 | write32(&exynos_dmc->memcontrol, mem->memcontrol); |
Stefan Reinauer | 9fe20cb | 2012-12-07 17:18:43 -0800 | [diff] [blame] | 242 | |
| 243 | /* Set DMC Concontrol and enable auto-refresh counter */ |
Julius Werner | 9418476 | 2015-02-19 20:19:23 -0800 | [diff] [blame] | 244 | write32(&exynos_dmc->concontrol, mem->concontrol | |
| 245 | (mem->rd_fetch << CONCONTROL_RD_FETCH_SHIFT) | |
| 246 | (mem->aref_en << CONCONTROL_AREF_EN_SHIFT)); |
Stefan Reinauer | 9fe20cb | 2012-12-07 17:18:43 -0800 | [diff] [blame] | 247 | return 0; |
| 248 | } |