Stefan Reinauer | 9fe20cb | 2012-12-07 17:18:43 -0800 | [diff] [blame] | 1 | /* |
Stefan Reinauer | 08dc357 | 2013-05-14 16:57:50 -0700 | [diff] [blame] | 2 | * This file is part of the coreboot project. |
Stefan Reinauer | 9fe20cb | 2012-12-07 17:18:43 -0800 | [diff] [blame] | 3 | * |
| 4 | * Copyright (C) 2012 Samsung Electronics |
| 5 | * |
Stefan Reinauer | 08dc357 | 2013-05-14 16:57:50 -0700 | [diff] [blame] | 6 | * This program is free software; you can redistribute it and/or modify |
| 7 | * it under the terms of the GNU General Public License as published by |
| 8 | * the Free Software Foundation; version 2 of the License. |
Stefan Reinauer | 9fe20cb | 2012-12-07 17:18:43 -0800 | [diff] [blame] | 9 | * |
| 10 | * This program is distributed in the hope that it will be useful, |
| 11 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 12 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 13 | * GNU General Public License for more details. |
Stefan Reinauer | 9fe20cb | 2012-12-07 17:18:43 -0800 | [diff] [blame] | 14 | */ |
| 15 | |
Stefan Reinauer | 08dc357 | 2013-05-14 16:57:50 -0700 | [diff] [blame] | 16 | /* Mem setup common file for different types of DDR present on SMDK5250 boards. |
| 17 | */ |
Stefan Reinauer | 9fe20cb | 2012-12-07 17:18:43 -0800 | [diff] [blame] | 18 | |
Stefan Reinauer | 08dc357 | 2013-05-14 16:57:50 -0700 | [diff] [blame] | 19 | #include <arch/io.h> |
Julius Werner | 1ed0c8c | 2014-10-20 13:16:29 -0700 | [diff] [blame] | 20 | #include <console/console.h> |
Stefan Reinauer | 08dc357 | 2013-05-14 16:57:50 -0700 | [diff] [blame] | 21 | #include <delay.h> |
Julius Werner | 1ed0c8c | 2014-10-20 13:16:29 -0700 | [diff] [blame] | 22 | #include <soc/clk.h> |
| 23 | #include <soc/dmc.h> |
| 24 | #include <soc/setup.h> |
Stefan Reinauer | 9fe20cb | 2012-12-07 17:18:43 -0800 | [diff] [blame] | 25 | |
| 26 | #define ZQ_INIT_TIMEOUT 10000 |
| 27 | |
| 28 | int dmc_config_zq(struct mem_timings *mem, |
| 29 | struct exynos5_phy_control *phy0_ctrl, |
| 30 | struct exynos5_phy_control *phy1_ctrl) |
| 31 | { |
| 32 | unsigned long val = 0; |
| 33 | int i; |
| 34 | |
| 35 | /* |
| 36 | * ZQ Calibration: |
| 37 | * Select Driver Strength, |
| 38 | * long calibration for manual calibration |
| 39 | */ |
| 40 | val = PHY_CON16_RESET_VAL; |
| 41 | val |= mem->zq_mode_dds << PHY_CON16_ZQ_MODE_DDS_SHIFT; |
| 42 | val |= mem->zq_mode_term << PHY_CON16_ZQ_MODE_TERM_SHIFT; |
| 43 | val |= ZQ_CLK_DIV_EN; |
Julius Werner | 2f37bd6 | 2015-02-19 14:51:15 -0800 | [diff] [blame] | 44 | write32(&phy0_ctrl->phy_con16, val); |
| 45 | write32(&phy1_ctrl->phy_con16, val); |
Stefan Reinauer | 9fe20cb | 2012-12-07 17:18:43 -0800 | [diff] [blame] | 46 | |
| 47 | /* Disable termination */ |
| 48 | if (mem->zq_mode_noterm) |
| 49 | val |= PHY_CON16_ZQ_MODE_NOTERM_MASK; |
Julius Werner | 2f37bd6 | 2015-02-19 14:51:15 -0800 | [diff] [blame] | 50 | write32(&phy0_ctrl->phy_con16, val); |
| 51 | write32(&phy1_ctrl->phy_con16, val); |
Stefan Reinauer | 9fe20cb | 2012-12-07 17:18:43 -0800 | [diff] [blame] | 52 | |
| 53 | /* ZQ_MANUAL_START: Enable */ |
| 54 | val |= ZQ_MANUAL_STR; |
Julius Werner | 2f37bd6 | 2015-02-19 14:51:15 -0800 | [diff] [blame] | 55 | write32(&phy0_ctrl->phy_con16, val); |
| 56 | write32(&phy1_ctrl->phy_con16, val); |
Stefan Reinauer | 9fe20cb | 2012-12-07 17:18:43 -0800 | [diff] [blame] | 57 | |
| 58 | /* ZQ_MANUAL_START: Disable */ |
| 59 | val &= ~ZQ_MANUAL_STR; |
| 60 | |
| 61 | /* |
Martin Roth | 4c3ab73 | 2013-07-08 16:23:54 -0600 | [diff] [blame] | 62 | * Since we are manually calibrating the ZQ values, |
Stefan Reinauer | 9fe20cb | 2012-12-07 17:18:43 -0800 | [diff] [blame] | 63 | * we are looping for the ZQ_init to complete. |
| 64 | */ |
| 65 | i = ZQ_INIT_TIMEOUT; |
Julius Werner | 2f37bd6 | 2015-02-19 14:51:15 -0800 | [diff] [blame] | 66 | while ((read32(&phy0_ctrl->phy_con17) & ZQ_DONE) != ZQ_DONE && i > 0) { |
David Hendricks | 1fb11d1 | 2013-04-12 15:11:05 -0700 | [diff] [blame] | 67 | udelay(1); |
Stefan Reinauer | 9fe20cb | 2012-12-07 17:18:43 -0800 | [diff] [blame] | 68 | i--; |
| 69 | } |
| 70 | if (!i) |
| 71 | return -1; |
Julius Werner | 2f37bd6 | 2015-02-19 14:51:15 -0800 | [diff] [blame] | 72 | write32(&phy0_ctrl->phy_con16, val); |
Stefan Reinauer | 9fe20cb | 2012-12-07 17:18:43 -0800 | [diff] [blame] | 73 | |
| 74 | i = ZQ_INIT_TIMEOUT; |
Julius Werner | 2f37bd6 | 2015-02-19 14:51:15 -0800 | [diff] [blame] | 75 | while ((read32(&phy1_ctrl->phy_con17) & ZQ_DONE) != ZQ_DONE && i > 0) { |
David Hendricks | 1fb11d1 | 2013-04-12 15:11:05 -0700 | [diff] [blame] | 76 | udelay(1); |
Stefan Reinauer | 9fe20cb | 2012-12-07 17:18:43 -0800 | [diff] [blame] | 77 | i--; |
| 78 | } |
| 79 | if (!i) |
| 80 | return -1; |
Julius Werner | 2f37bd6 | 2015-02-19 14:51:15 -0800 | [diff] [blame] | 81 | write32(&phy1_ctrl->phy_con16, val); |
Stefan Reinauer | 9fe20cb | 2012-12-07 17:18:43 -0800 | [diff] [blame] | 82 | |
| 83 | return 0; |
| 84 | } |
| 85 | |
| 86 | void update_reset_dll(struct exynos5_dmc *dmc, enum ddr_mode mode) |
| 87 | { |
| 88 | unsigned long val; |
| 89 | |
| 90 | if (mode == DDR_MODE_DDR3) { |
| 91 | val = MEM_TERM_EN | PHY_TERM_EN | DMC_CTRL_SHGATE; |
Julius Werner | 2f37bd6 | 2015-02-19 14:51:15 -0800 | [diff] [blame] | 92 | write32(&dmc->phycontrol0, val); |
Stefan Reinauer | 9fe20cb | 2012-12-07 17:18:43 -0800 | [diff] [blame] | 93 | } |
| 94 | |
Martin Roth | 4c3ab73 | 2013-07-08 16:23:54 -0600 | [diff] [blame] | 95 | /* Update DLL Information: Force DLL Resynchronization */ |
Julius Werner | 2f37bd6 | 2015-02-19 14:51:15 -0800 | [diff] [blame] | 96 | val = read32(&dmc->phycontrol0); |
Stefan Reinauer | 9fe20cb | 2012-12-07 17:18:43 -0800 | [diff] [blame] | 97 | val |= FP_RSYNC; |
Julius Werner | 2f37bd6 | 2015-02-19 14:51:15 -0800 | [diff] [blame] | 98 | write32(&dmc->phycontrol0, val); |
Stefan Reinauer | 9fe20cb | 2012-12-07 17:18:43 -0800 | [diff] [blame] | 99 | |
Martin Roth | 4c3ab73 | 2013-07-08 16:23:54 -0600 | [diff] [blame] | 100 | /* Reset Force DLL Resynchronization */ |
Julius Werner | 2f37bd6 | 2015-02-19 14:51:15 -0800 | [diff] [blame] | 101 | val = read32(&dmc->phycontrol0); |
Stefan Reinauer | 9fe20cb | 2012-12-07 17:18:43 -0800 | [diff] [blame] | 102 | val &= ~FP_RSYNC; |
Julius Werner | 2f37bd6 | 2015-02-19 14:51:15 -0800 | [diff] [blame] | 103 | write32(&dmc->phycontrol0, val); |
Stefan Reinauer | 9fe20cb | 2012-12-07 17:18:43 -0800 | [diff] [blame] | 104 | } |
| 105 | |
| 106 | void dmc_config_mrs(struct mem_timings *mem, struct exynos5_dmc *dmc) |
| 107 | { |
| 108 | int channel, chip; |
| 109 | |
| 110 | for (channel = 0; channel < mem->dmc_channels; channel++) { |
| 111 | unsigned long mask; |
| 112 | |
| 113 | mask = channel << DIRECT_CMD_CHANNEL_SHIFT; |
| 114 | for (chip = 0; chip < mem->chips_to_configure; chip++) { |
| 115 | int i; |
| 116 | |
| 117 | mask |= chip << DIRECT_CMD_CHIP_SHIFT; |
| 118 | |
| 119 | /* Sending NOP command */ |
Julius Werner | 2f37bd6 | 2015-02-19 14:51:15 -0800 | [diff] [blame] | 120 | write32(&dmc->directcmd, DIRECT_CMD_NOP | mask); |
Stefan Reinauer | 9fe20cb | 2012-12-07 17:18:43 -0800 | [diff] [blame] | 121 | |
| 122 | /* |
| 123 | * TODO(alim.akhtar@samsung.com): Do we need these |
| 124 | * delays? This one and the next were not there for |
| 125 | * DDR3. |
| 126 | */ |
David Hendricks | 1fb11d1 | 2013-04-12 15:11:05 -0700 | [diff] [blame] | 127 | udelay(100); |
Stefan Reinauer | 9fe20cb | 2012-12-07 17:18:43 -0800 | [diff] [blame] | 128 | |
| 129 | /* Sending EMRS/MRS commands */ |
| 130 | for (i = 0; i < MEM_TIMINGS_MSR_COUNT; i++) { |
Julius Werner | 2f37bd6 | 2015-02-19 14:51:15 -0800 | [diff] [blame] | 131 | write32(&dmc->directcmd, |
| 132 | mem->direct_cmd_msr[i] | mask); |
David Hendricks | 1fb11d1 | 2013-04-12 15:11:05 -0700 | [diff] [blame] | 133 | udelay(100); |
Stefan Reinauer | 9fe20cb | 2012-12-07 17:18:43 -0800 | [diff] [blame] | 134 | } |
| 135 | |
| 136 | if (mem->send_zq_init) { |
| 137 | /* Sending ZQINIT command */ |
Julius Werner | 2f37bd6 | 2015-02-19 14:51:15 -0800 | [diff] [blame] | 138 | write32(&dmc->directcmd, |
| 139 | DIRECT_CMD_ZQINIT | mask); |
David Hendricks | 1fb11d1 | 2013-04-12 15:11:05 -0700 | [diff] [blame] | 140 | /* |
| 141 | * FIXME: This was originally sdelay(10000) |
| 142 | * in the imported u-boot code. That may have |
| 143 | * been meant to be sdelay(0x10000) since that |
| 144 | * was used elsewhere in this function. Either |
| 145 | * way seems to work, though. |
| 146 | */ |
| 147 | udelay(12); |
Stefan Reinauer | 9fe20cb | 2012-12-07 17:18:43 -0800 | [diff] [blame] | 148 | } |
| 149 | } |
| 150 | } |
| 151 | } |
| 152 | |
| 153 | void dmc_config_prech(struct mem_timings *mem, struct exynos5_dmc *dmc) |
| 154 | { |
| 155 | int channel, chip; |
| 156 | |
| 157 | for (channel = 0; channel < mem->dmc_channels; channel++) { |
| 158 | unsigned long mask; |
| 159 | |
| 160 | mask = channel << DIRECT_CMD_CHANNEL_SHIFT; |
| 161 | for (chip = 0; chip < mem->chips_per_channel; chip++) { |
| 162 | mask |= chip << DIRECT_CMD_CHIP_SHIFT; |
| 163 | |
| 164 | /* PALL (all banks precharge) CMD */ |
Julius Werner | 2f37bd6 | 2015-02-19 14:51:15 -0800 | [diff] [blame] | 165 | write32(&dmc->directcmd, DIRECT_CMD_PALL | mask); |
David Hendricks | 1fb11d1 | 2013-04-12 15:11:05 -0700 | [diff] [blame] | 166 | udelay(100); |
Stefan Reinauer | 9fe20cb | 2012-12-07 17:18:43 -0800 | [diff] [blame] | 167 | } |
| 168 | } |
| 169 | } |
| 170 | |
| 171 | void dmc_config_memory(struct mem_timings *mem, struct exynos5_dmc *dmc) |
| 172 | { |
Julius Werner | 2f37bd6 | 2015-02-19 14:51:15 -0800 | [diff] [blame] | 173 | write32(&dmc->memconfig0, mem->memconfig); |
| 174 | write32(&dmc->memconfig1, mem->memconfig); |
| 175 | write32(&dmc->membaseconfig0, DMC_MEMBASECONFIG0_VAL); |
| 176 | write32(&dmc->membaseconfig1, DMC_MEMBASECONFIG1_VAL); |
Stefan Reinauer | 9fe20cb | 2012-12-07 17:18:43 -0800 | [diff] [blame] | 177 | } |