Stefan Reinauer | 9fe20cb | 2012-12-07 17:18:43 -0800 | [diff] [blame] | 1 | /* |
Stefan Reinauer | 08dc357 | 2013-05-14 16:57:50 -0700 | [diff] [blame] | 2 | * This file is part of the coreboot project. |
| 3 | * |
Stefan Reinauer | 9fe20cb | 2012-12-07 17:18:43 -0800 | [diff] [blame] | 4 | * Copyright (C) 2010 Samsung Electronics |
Stefan Reinauer | 9fe20cb | 2012-12-07 17:18:43 -0800 | [diff] [blame] | 5 | * |
Stefan Reinauer | 08dc357 | 2013-05-14 16:57:50 -0700 | [diff] [blame] | 6 | * This program is free software; you can redistribute it and/or modify |
| 7 | * it under the terms of the GNU General Public License as published by |
| 8 | * the Free Software Foundation; version 2 of the License. |
Stefan Reinauer | 9fe20cb | 2012-12-07 17:18:43 -0800 | [diff] [blame] | 9 | * |
| 10 | * This program is distributed in the hope that it will be useful, |
| 11 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 12 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 13 | * GNU General Public License for more details. |
Stefan Reinauer | 9fe20cb | 2012-12-07 17:18:43 -0800 | [diff] [blame] | 14 | */ |
| 15 | |
Julius Werner | 1ed0c8c | 2014-10-20 13:16:29 -0700 | [diff] [blame] | 16 | #include <arch/io.h> |
Stefan Reinauer | 08dc357 | 2013-05-14 16:57:50 -0700 | [diff] [blame] | 17 | #include <assert.h> |
Julius Werner | 1ed0c8c | 2014-10-20 13:16:29 -0700 | [diff] [blame] | 18 | #include <console/console.h> |
| 19 | #include <soc/clk.h> |
| 20 | #include <soc/periph.h> |
Julius Werner | fa938c7 | 2013-08-29 14:17:36 -0700 | [diff] [blame] | 21 | #include <stdlib.h> |
Edward O'Callaghan | 9b152b2 | 2014-12-26 12:36:47 +1100 | [diff] [blame] | 22 | #include <timer.h> |
Stefan Reinauer | 9fe20cb | 2012-12-07 17:18:43 -0800 | [diff] [blame] | 23 | |
| 24 | /* input clock of PLL: SMDK5250 has 24MHz input clock */ |
| 25 | #define CONFIG_SYS_CLK_FREQ 24000000 |
| 26 | |
Stefan Reinauer | 08dc357 | 2013-05-14 16:57:50 -0700 | [diff] [blame] | 27 | static struct arm_clk_ratios arm_clk_ratios[] = { |
David Hendricks | 0d4f97e | 2013-02-03 18:09:58 -0800 | [diff] [blame] | 28 | { |
| 29 | .arm_freq_mhz = 600, |
| 30 | |
| 31 | .apll_mdiv = 0xc8, |
| 32 | .apll_pdiv = 0x4, |
| 33 | .apll_sdiv = 0x1, |
| 34 | |
| 35 | .arm2_ratio = 0x0, |
| 36 | .apll_ratio = 0x1, |
| 37 | .pclk_dbg_ratio = 0x1, |
| 38 | .atb_ratio = 0x2, |
| 39 | .periph_ratio = 0x7, |
| 40 | .acp_ratio = 0x7, |
| 41 | .cpud_ratio = 0x1, |
| 42 | .arm_ratio = 0x0, |
| 43 | }, { |
| 44 | .arm_freq_mhz = 800, |
| 45 | |
| 46 | .apll_mdiv = 0x64, |
| 47 | .apll_pdiv = 0x3, |
| 48 | .apll_sdiv = 0x0, |
| 49 | |
| 50 | .arm2_ratio = 0x0, |
| 51 | .apll_ratio = 0x1, |
| 52 | .pclk_dbg_ratio = 0x1, |
| 53 | .atb_ratio = 0x3, |
| 54 | .periph_ratio = 0x7, |
| 55 | .acp_ratio = 0x7, |
| 56 | .cpud_ratio = 0x2, |
| 57 | .arm_ratio = 0x0, |
| 58 | }, { |
| 59 | .arm_freq_mhz = 1000, |
| 60 | |
| 61 | .apll_mdiv = 0x7d, |
| 62 | .apll_pdiv = 0x3, |
| 63 | .apll_sdiv = 0x0, |
| 64 | |
| 65 | .arm2_ratio = 0x0, |
| 66 | .apll_ratio = 0x1, |
| 67 | .pclk_dbg_ratio = 0x1, |
| 68 | .atb_ratio = 0x4, |
| 69 | .periph_ratio = 0x7, |
| 70 | .acp_ratio = 0x7, |
| 71 | .cpud_ratio = 0x2, |
| 72 | .arm_ratio = 0x0, |
| 73 | }, { |
| 74 | .arm_freq_mhz = 1200, |
| 75 | |
| 76 | .apll_mdiv = 0x96, |
| 77 | .apll_pdiv = 0x3, |
| 78 | .apll_sdiv = 0x0, |
| 79 | |
| 80 | .arm2_ratio = 0x0, |
| 81 | .apll_ratio = 0x3, |
| 82 | .pclk_dbg_ratio = 0x1, |
| 83 | .atb_ratio = 0x5, |
| 84 | .periph_ratio = 0x7, |
| 85 | .acp_ratio = 0x7, |
| 86 | .cpud_ratio = 0x3, |
| 87 | .arm_ratio = 0x0, |
| 88 | }, { |
| 89 | .arm_freq_mhz = 1400, |
| 90 | |
| 91 | .apll_mdiv = 0xaf, |
| 92 | .apll_pdiv = 0x3, |
| 93 | .apll_sdiv = 0x0, |
| 94 | |
| 95 | .arm2_ratio = 0x0, |
| 96 | .apll_ratio = 0x3, |
| 97 | .pclk_dbg_ratio = 0x1, |
| 98 | .atb_ratio = 0x6, |
| 99 | .periph_ratio = 0x7, |
| 100 | .acp_ratio = 0x7, |
| 101 | .cpud_ratio = 0x3, |
| 102 | .arm_ratio = 0x0, |
| 103 | }, { |
| 104 | .arm_freq_mhz = 1700, |
| 105 | |
| 106 | .apll_mdiv = 0x1a9, |
| 107 | .apll_pdiv = 0x6, |
| 108 | .apll_sdiv = 0x0, |
| 109 | |
| 110 | .arm2_ratio = 0x0, |
| 111 | .apll_ratio = 0x3, |
| 112 | .pclk_dbg_ratio = 0x1, |
| 113 | .atb_ratio = 0x6, |
| 114 | .periph_ratio = 0x7, |
| 115 | .acp_ratio = 0x7, |
| 116 | .cpud_ratio = 0x3, |
| 117 | .arm_ratio = 0x0, |
| 118 | } |
| 119 | }; |
Stefan Reinauer | 9fe20cb | 2012-12-07 17:18:43 -0800 | [diff] [blame] | 120 | |
| 121 | /* src_bit div_bit prediv_bit */ |
| 122 | static struct clk_bit_info clk_bit_info[PERIPH_ID_COUNT] = { |
| 123 | {0, 4, 0, -1}, |
| 124 | {4, 4, 4, -1}, |
| 125 | {8, 4, 8, -1}, |
| 126 | {12, 4, 12, -1}, |
| 127 | {0, 4, 0, 8}, |
| 128 | {4, 4, 16, 24}, |
| 129 | {8, 4, 0, 8}, |
| 130 | {12, 4, 16, 24}, |
| 131 | {-1, -1, -1, -1}, |
| 132 | {16, 4, 0, 8}, /* PERIPH_ID_SROMC */ |
| 133 | {20, 4, 16, 24}, |
| 134 | {24, 4, 0, 8}, |
| 135 | {0, 4, 0, 4}, |
| 136 | {4, 4, 12, 16}, |
| 137 | {-1, 4, -1, -1}, |
| 138 | {-1, 4, -1, -1}, |
| 139 | {-1, 4, 24, 0}, |
| 140 | {-1, 4, 24, 0}, |
| 141 | {-1, 4, 24, 0}, |
| 142 | {-1, 4, 24, 0}, |
| 143 | {-1, 4, 24, 0}, |
| 144 | {-1, 4, 24, 0}, |
| 145 | {-1, 4, 24, 0}, |
| 146 | {-1, 4, 24, 0}, |
| 147 | {24, 4, 0, -1}, |
| 148 | {24, 4, 0, -1}, |
| 149 | {24, 4, 0, -1}, |
| 150 | {24, 4, 0, -1}, |
| 151 | {24, 4, 0, -1}, |
| 152 | {-1, -1, -1, -1}, |
| 153 | {-1, -1, -1, -1}, |
| 154 | {-1, -1, -1, -1}, /* PERIPH_ID_I2S1 */ |
| 155 | {24, 1, 20, -1}, /* PERIPH_ID_SATA */ |
| 156 | }; |
| 157 | |
Martin Roth | 4c3ab73 | 2013-07-08 16:23:54 -0600 | [diff] [blame] | 158 | /* Epll Clock division values to achieve different frequency output */ |
Stefan Reinauer | 9fe20cb | 2012-12-07 17:18:43 -0800 | [diff] [blame] | 159 | static struct st_epll_con_val epll_div[] = { |
| 160 | { 192000000, 0, 48, 3, 1, 0 }, |
| 161 | { 180000000, 0, 45, 3, 1, 0 }, |
| 162 | { 73728000, 1, 73, 3, 3, 47710 }, |
| 163 | { 67737600, 1, 90, 4, 3, 20762 }, |
| 164 | { 49152000, 0, 49, 3, 3, 9961 }, |
| 165 | { 45158400, 0, 45, 3, 3, 10381 }, |
| 166 | { 180633600, 0, 45, 3, 1, 10381 } |
| 167 | }; |
| 168 | |
| 169 | /* exynos5: return pll clock frequency */ |
| 170 | unsigned long get_pll_clk(int pllreg) |
| 171 | { |
Stefan Reinauer | 9fe20cb | 2012-12-07 17:18:43 -0800 | [diff] [blame] | 172 | unsigned long r, m, p, s, k = 0, mask, fout; |
| 173 | unsigned int freq; |
| 174 | |
| 175 | switch (pllreg) { |
| 176 | case APLL: |
Julius Werner | 2f37bd6 | 2015-02-19 14:51:15 -0800 | [diff] [blame] | 177 | r = read32(&exynos_clock->apll_con0); |
Stefan Reinauer | 9fe20cb | 2012-12-07 17:18:43 -0800 | [diff] [blame] | 178 | break; |
| 179 | case BPLL: |
Julius Werner | 2f37bd6 | 2015-02-19 14:51:15 -0800 | [diff] [blame] | 180 | r = read32(&exynos_clock->bpll_con0); |
Stefan Reinauer | 9fe20cb | 2012-12-07 17:18:43 -0800 | [diff] [blame] | 181 | break; |
| 182 | case MPLL: |
Julius Werner | 2f37bd6 | 2015-02-19 14:51:15 -0800 | [diff] [blame] | 183 | r = read32(&exynos_clock->mpll_con0); |
Stefan Reinauer | 9fe20cb | 2012-12-07 17:18:43 -0800 | [diff] [blame] | 184 | break; |
| 185 | case EPLL: |
Julius Werner | 2f37bd6 | 2015-02-19 14:51:15 -0800 | [diff] [blame] | 186 | r = read32(&exynos_clock->epll_con0); |
| 187 | k = read32(&exynos_clock->epll_con1); |
Stefan Reinauer | 9fe20cb | 2012-12-07 17:18:43 -0800 | [diff] [blame] | 188 | break; |
| 189 | case VPLL: |
Julius Werner | 2f37bd6 | 2015-02-19 14:51:15 -0800 | [diff] [blame] | 190 | r = read32(&exynos_clock->vpll_con0); |
| 191 | k = read32(&exynos_clock->vpll_con1); |
Stefan Reinauer | 9fe20cb | 2012-12-07 17:18:43 -0800 | [diff] [blame] | 192 | break; |
| 193 | default: |
| 194 | printk(BIOS_DEBUG, "Unsupported PLL (%d)\n", pllreg); |
| 195 | return 0; |
| 196 | } |
| 197 | |
| 198 | /* |
| 199 | * APLL_CON: MIDV [25:16] |
| 200 | * MPLL_CON: MIDV [25:16] |
| 201 | * EPLL_CON: MIDV [24:16] |
| 202 | * VPLL_CON: MIDV [24:16] |
| 203 | */ |
| 204 | if (pllreg == APLL || pllreg == BPLL || pllreg == MPLL) |
| 205 | mask = 0x3ff; |
| 206 | else |
| 207 | mask = 0x1ff; |
| 208 | |
| 209 | m = (r >> 16) & mask; |
| 210 | |
| 211 | /* PDIV [13:8] */ |
| 212 | p = (r >> 8) & 0x3f; |
| 213 | /* SDIV [2:0] */ |
| 214 | s = r & 0x7; |
| 215 | |
| 216 | freq = CONFIG_SYS_CLK_FREQ; |
| 217 | |
| 218 | if (pllreg == EPLL) { |
| 219 | k = k & 0xffff; |
| 220 | /* FOUT = (MDIV + K / 65536) * FIN / (PDIV * 2^SDIV) */ |
| 221 | fout = (m + k / 65536) * (freq / (p * (1 << s))); |
| 222 | } else if (pllreg == VPLL) { |
| 223 | k = k & 0xfff; |
| 224 | /* FOUT = (MDIV + K / 1024) * FIN / (PDIV * 2^SDIV) */ |
| 225 | fout = (m + k / 1024) * (freq / (p * (1 << s))); |
| 226 | } else { |
| 227 | /* FOUT = MDIV * FIN / (PDIV * 2^SDIV) */ |
| 228 | fout = m * (freq / (p * (1 << s))); |
| 229 | } |
| 230 | |
| 231 | return fout; |
| 232 | } |
| 233 | |
| 234 | unsigned long clock_get_periph_rate(enum periph_id peripheral) |
| 235 | { |
Stefan Reinauer | 9fe20cb | 2012-12-07 17:18:43 -0800 | [diff] [blame] | 236 | struct clk_bit_info *bit_info = &clk_bit_info[peripheral]; |
| 237 | unsigned long sclk, sub_clk; |
| 238 | unsigned int src, div, sub_div; |
| 239 | |
| 240 | switch (peripheral) { |
| 241 | case PERIPH_ID_UART0: |
| 242 | case PERIPH_ID_UART1: |
| 243 | case PERIPH_ID_UART2: |
| 244 | case PERIPH_ID_UART3: |
Julius Werner | 2f37bd6 | 2015-02-19 14:51:15 -0800 | [diff] [blame] | 245 | src = read32(&exynos_clock->src_peric0); |
| 246 | div = read32(&exynos_clock->div_peric0); |
Stefan Reinauer | 9fe20cb | 2012-12-07 17:18:43 -0800 | [diff] [blame] | 247 | break; |
| 248 | case PERIPH_ID_PWM0: |
| 249 | case PERIPH_ID_PWM1: |
| 250 | case PERIPH_ID_PWM2: |
| 251 | case PERIPH_ID_PWM3: |
| 252 | case PERIPH_ID_PWM4: |
Julius Werner | 2f37bd6 | 2015-02-19 14:51:15 -0800 | [diff] [blame] | 253 | src = read32(&exynos_clock->src_peric0); |
| 254 | div = read32(&exynos_clock->div_peric3); |
Stefan Reinauer | 9fe20cb | 2012-12-07 17:18:43 -0800 | [diff] [blame] | 255 | break; |
| 256 | case PERIPH_ID_SPI0: |
| 257 | case PERIPH_ID_SPI1: |
Julius Werner | 2f37bd6 | 2015-02-19 14:51:15 -0800 | [diff] [blame] | 258 | src = read32(&exynos_clock->src_peric1); |
| 259 | div = read32(&exynos_clock->div_peric1); |
Stefan Reinauer | 9fe20cb | 2012-12-07 17:18:43 -0800 | [diff] [blame] | 260 | break; |
| 261 | case PERIPH_ID_SPI2: |
Julius Werner | 2f37bd6 | 2015-02-19 14:51:15 -0800 | [diff] [blame] | 262 | src = read32(&exynos_clock->src_peric1); |
| 263 | div = read32(&exynos_clock->div_peric2); |
Stefan Reinauer | 9fe20cb | 2012-12-07 17:18:43 -0800 | [diff] [blame] | 264 | break; |
| 265 | case PERIPH_ID_SPI3: |
| 266 | case PERIPH_ID_SPI4: |
Julius Werner | 2f37bd6 | 2015-02-19 14:51:15 -0800 | [diff] [blame] | 267 | src = read32(&exynos_clock->sclk_src_isp); |
| 268 | div = read32(&exynos_clock->sclk_div_isp); |
Stefan Reinauer | 9fe20cb | 2012-12-07 17:18:43 -0800 | [diff] [blame] | 269 | break; |
| 270 | case PERIPH_ID_SATA: |
Julius Werner | 2f37bd6 | 2015-02-19 14:51:15 -0800 | [diff] [blame] | 271 | src = read32(&exynos_clock->src_fsys); |
| 272 | div = read32(&exynos_clock->div_fsys0); |
Stefan Reinauer | 9fe20cb | 2012-12-07 17:18:43 -0800 | [diff] [blame] | 273 | break; |
| 274 | case PERIPH_ID_SDMMC0: |
| 275 | case PERIPH_ID_SDMMC1: |
| 276 | case PERIPH_ID_SDMMC2: |
| 277 | case PERIPH_ID_SDMMC3: |
Julius Werner | 2f37bd6 | 2015-02-19 14:51:15 -0800 | [diff] [blame] | 278 | src = read32(&exynos_clock->src_fsys); |
| 279 | div = read32(&exynos_clock->div_fsys1); |
Stefan Reinauer | 9fe20cb | 2012-12-07 17:18:43 -0800 | [diff] [blame] | 280 | break; |
| 281 | case PERIPH_ID_I2C0: |
| 282 | case PERIPH_ID_I2C1: |
| 283 | case PERIPH_ID_I2C2: |
| 284 | case PERIPH_ID_I2C3: |
| 285 | case PERIPH_ID_I2C4: |
| 286 | case PERIPH_ID_I2C5: |
| 287 | case PERIPH_ID_I2C6: |
| 288 | case PERIPH_ID_I2C7: |
| 289 | sclk = get_pll_clk(MPLL); |
Julius Werner | 2f37bd6 | 2015-02-19 14:51:15 -0800 | [diff] [blame] | 290 | sub_div = ((read32(&exynos_clock->div_top1) |
Julius Werner | fa938c7 | 2013-08-29 14:17:36 -0700 | [diff] [blame] | 291 | >> bit_info->div_bit) & 0x7) + 1; |
Julius Werner | 2f37bd6 | 2015-02-19 14:51:15 -0800 | [diff] [blame] | 292 | div = ((read32(&exynos_clock->div_top0) |
Julius Werner | fa938c7 | 2013-08-29 14:17:36 -0700 | [diff] [blame] | 293 | >> bit_info->prediv_bit) & 0x7) + 1; |
Stefan Reinauer | 9fe20cb | 2012-12-07 17:18:43 -0800 | [diff] [blame] | 294 | return (sclk / sub_div) / div; |
| 295 | default: |
| 296 | printk(BIOS_DEBUG, "%s: invalid peripheral %d", __func__, peripheral); |
| 297 | return -1; |
| 298 | }; |
| 299 | |
| 300 | src = (src >> bit_info->src_bit) & ((1 << bit_info->n_src_bits) - 1); |
| 301 | if (peripheral == PERIPH_ID_SATA) { |
| 302 | if (src) |
| 303 | sclk = get_pll_clk(BPLL); |
| 304 | else |
| 305 | sclk = get_pll_clk(MPLL); |
| 306 | } else { |
| 307 | if (src == SRC_MPLL) |
| 308 | sclk = get_pll_clk(MPLL); |
| 309 | else if (src == SRC_EPLL) |
| 310 | sclk = get_pll_clk(EPLL); |
| 311 | else if (src == SRC_VPLL) |
| 312 | sclk = get_pll_clk(VPLL); |
| 313 | else |
| 314 | return 0; |
| 315 | } |
| 316 | |
| 317 | sub_div = (div >> bit_info->div_bit) & 0xf; |
| 318 | sub_clk = sclk / (sub_div + 1); |
| 319 | |
| 320 | if (peripheral == PERIPH_ID_SDMMC0 || peripheral == PERIPH_ID_SDMMC2) { |
| 321 | div = (div >> bit_info->prediv_bit) & 0xff; |
| 322 | return sub_clk / (div + 1); |
| 323 | } |
| 324 | |
| 325 | return sub_clk; |
| 326 | } |
| 327 | |
| 328 | /* exynos5: return ARM clock frequency */ |
| 329 | unsigned long get_arm_clk(void) |
| 330 | { |
Stefan Reinauer | 9fe20cb | 2012-12-07 17:18:43 -0800 | [diff] [blame] | 331 | unsigned long div; |
| 332 | unsigned long armclk; |
| 333 | unsigned int arm_ratio; |
| 334 | unsigned int arm2_ratio; |
| 335 | |
Julius Werner | 2f37bd6 | 2015-02-19 14:51:15 -0800 | [diff] [blame] | 336 | div = read32(&exynos_clock->div_cpu0); |
Stefan Reinauer | 9fe20cb | 2012-12-07 17:18:43 -0800 | [diff] [blame] | 337 | |
| 338 | /* ARM_RATIO: [2:0], ARM2_RATIO: [30:28] */ |
| 339 | arm_ratio = (div >> 0) & 0x7; |
| 340 | arm2_ratio = (div >> 28) & 0x7; |
| 341 | |
| 342 | armclk = get_pll_clk(APLL) / (arm_ratio + 1); |
| 343 | armclk /= (arm2_ratio + 1); |
| 344 | |
| 345 | return armclk; |
| 346 | } |
| 347 | |
David Hendricks | 0d4f97e | 2013-02-03 18:09:58 -0800 | [diff] [blame] | 348 | struct arm_clk_ratios *get_arm_clk_ratios(void) |
| 349 | { |
| 350 | struct arm_clk_ratios *arm_ratio; |
| 351 | unsigned long arm_freq = 1700; /* FIXME: use get_arm_clk() */ |
| 352 | int i; |
| 353 | |
| 354 | for (i = 0, arm_ratio = arm_clk_ratios; i < ARRAY_SIZE(arm_clk_ratios); |
| 355 | i++, arm_ratio++) { |
| 356 | if (arm_ratio->arm_freq_mhz == arm_freq) |
| 357 | return arm_ratio; |
| 358 | } |
| 359 | |
| 360 | return NULL; |
| 361 | } |
| 362 | |
Stefan Reinauer | 9fe20cb | 2012-12-07 17:18:43 -0800 | [diff] [blame] | 363 | /* exynos5: set the mmc clock */ |
| 364 | void set_mmc_clk(int dev_index, unsigned int div) |
| 365 | { |
David Hendricks | 086b369 | 2013-04-08 20:01:18 -0700 | [diff] [blame] | 366 | unsigned int *addr; |
Stefan Reinauer | 9fe20cb | 2012-12-07 17:18:43 -0800 | [diff] [blame] | 367 | unsigned int val; |
| 368 | |
| 369 | /* |
| 370 | * CLK_DIV_FSYS1 |
| 371 | * MMC0_PRE_RATIO [15:8], MMC1_PRE_RATIO [31:24] |
| 372 | * CLK_DIV_FSYS2 |
| 373 | * MMC2_PRE_RATIO [15:8], MMC3_PRE_RATIO [31:24] |
| 374 | */ |
| 375 | if (dev_index < 2) { |
Julius Werner | fa938c7 | 2013-08-29 14:17:36 -0700 | [diff] [blame] | 376 | addr = &exynos_clock->div_fsys1; |
Stefan Reinauer | 9fe20cb | 2012-12-07 17:18:43 -0800 | [diff] [blame] | 377 | } else { |
Julius Werner | fa938c7 | 2013-08-29 14:17:36 -0700 | [diff] [blame] | 378 | addr = &exynos_clock->div_fsys2; |
Stefan Reinauer | 9fe20cb | 2012-12-07 17:18:43 -0800 | [diff] [blame] | 379 | dev_index -= 2; |
| 380 | } |
| 381 | |
Julius Werner | 2f37bd6 | 2015-02-19 14:51:15 -0800 | [diff] [blame] | 382 | val = read32(addr); |
Stefan Reinauer | 9fe20cb | 2012-12-07 17:18:43 -0800 | [diff] [blame] | 383 | val &= ~(0xff << ((dev_index << 4) + 8)); |
| 384 | val |= (div & 0xff) << ((dev_index << 4) + 8); |
Julius Werner | 2f37bd6 | 2015-02-19 14:51:15 -0800 | [diff] [blame] | 385 | write32(addr, val); |
Stefan Reinauer | 9fe20cb | 2012-12-07 17:18:43 -0800 | [diff] [blame] | 386 | } |
| 387 | |
| 388 | void clock_ll_set_pre_ratio(enum periph_id periph_id, unsigned divisor) |
| 389 | { |
Stefan Reinauer | 9fe20cb | 2012-12-07 17:18:43 -0800 | [diff] [blame] | 390 | unsigned shift; |
| 391 | unsigned mask = 0xff; |
| 392 | u32 *reg; |
| 393 | |
| 394 | /* |
Martin Roth | 4c3ab73 | 2013-07-08 16:23:54 -0600 | [diff] [blame] | 395 | * For now we only handle a very small subset of peripherals here. |
Stefan Reinauer | 9fe20cb | 2012-12-07 17:18:43 -0800 | [diff] [blame] | 396 | * Others will need to (and do) mangle the clock registers |
| 397 | * themselves, At some point it is hoped that this function can work |
| 398 | * from a table or calculated register offset / mask. For now this |
| 399 | * is at least better than spreading clock control code around |
| 400 | * U-Boot. |
| 401 | */ |
| 402 | switch (periph_id) { |
| 403 | case PERIPH_ID_SPI0: |
Julius Werner | fa938c7 | 2013-08-29 14:17:36 -0700 | [diff] [blame] | 404 | reg = &exynos_clock->div_peric1; |
Stefan Reinauer | 9fe20cb | 2012-12-07 17:18:43 -0800 | [diff] [blame] | 405 | shift = 8; |
| 406 | break; |
| 407 | case PERIPH_ID_SPI1: |
Julius Werner | fa938c7 | 2013-08-29 14:17:36 -0700 | [diff] [blame] | 408 | reg = &exynos_clock->div_peric1; |
Stefan Reinauer | 9fe20cb | 2012-12-07 17:18:43 -0800 | [diff] [blame] | 409 | shift = 24; |
| 410 | break; |
| 411 | case PERIPH_ID_SPI2: |
Julius Werner | fa938c7 | 2013-08-29 14:17:36 -0700 | [diff] [blame] | 412 | reg = &exynos_clock->div_peric2; |
Stefan Reinauer | 9fe20cb | 2012-12-07 17:18:43 -0800 | [diff] [blame] | 413 | shift = 8; |
| 414 | break; |
| 415 | case PERIPH_ID_SPI3: |
Julius Werner | fa938c7 | 2013-08-29 14:17:36 -0700 | [diff] [blame] | 416 | reg = &exynos_clock->sclk_div_isp; |
Stefan Reinauer | 9fe20cb | 2012-12-07 17:18:43 -0800 | [diff] [blame] | 417 | shift = 4; |
| 418 | break; |
| 419 | case PERIPH_ID_SPI4: |
Julius Werner | fa938c7 | 2013-08-29 14:17:36 -0700 | [diff] [blame] | 420 | reg = &exynos_clock->sclk_div_isp; |
Stefan Reinauer | 9fe20cb | 2012-12-07 17:18:43 -0800 | [diff] [blame] | 421 | shift = 16; |
| 422 | break; |
| 423 | default: |
Stefan Reinauer | 08dc357 | 2013-05-14 16:57:50 -0700 | [diff] [blame] | 424 | printk(BIOS_DEBUG, "%s: Unsupported peripheral ID %d\n", __func__, |
Stefan Reinauer | 9fe20cb | 2012-12-07 17:18:43 -0800 | [diff] [blame] | 425 | periph_id); |
| 426 | return; |
| 427 | } |
| 428 | clrsetbits_le32(reg, mask << shift, (divisor & mask) << shift); |
| 429 | } |
| 430 | |
| 431 | void clock_ll_set_ratio(enum periph_id periph_id, unsigned divisor) |
| 432 | { |
Stefan Reinauer | 9fe20cb | 2012-12-07 17:18:43 -0800 | [diff] [blame] | 433 | unsigned shift; |
| 434 | unsigned mask = 0xff; |
| 435 | u32 *reg; |
| 436 | |
| 437 | switch (periph_id) { |
| 438 | case PERIPH_ID_SPI0: |
Julius Werner | fa938c7 | 2013-08-29 14:17:36 -0700 | [diff] [blame] | 439 | reg = &exynos_clock->div_peric1; |
Stefan Reinauer | 9fe20cb | 2012-12-07 17:18:43 -0800 | [diff] [blame] | 440 | shift = 0; |
| 441 | break; |
| 442 | case PERIPH_ID_SPI1: |
Julius Werner | fa938c7 | 2013-08-29 14:17:36 -0700 | [diff] [blame] | 443 | reg = &exynos_clock->div_peric1; |
Stefan Reinauer | 9fe20cb | 2012-12-07 17:18:43 -0800 | [diff] [blame] | 444 | shift = 16; |
| 445 | break; |
| 446 | case PERIPH_ID_SPI2: |
Julius Werner | fa938c7 | 2013-08-29 14:17:36 -0700 | [diff] [blame] | 447 | reg = &exynos_clock->div_peric2; |
Stefan Reinauer | 9fe20cb | 2012-12-07 17:18:43 -0800 | [diff] [blame] | 448 | shift = 0; |
| 449 | break; |
| 450 | case PERIPH_ID_SPI3: |
Julius Werner | fa938c7 | 2013-08-29 14:17:36 -0700 | [diff] [blame] | 451 | reg = &exynos_clock->sclk_div_isp; |
Stefan Reinauer | 9fe20cb | 2012-12-07 17:18:43 -0800 | [diff] [blame] | 452 | shift = 0; |
| 453 | break; |
| 454 | case PERIPH_ID_SPI4: |
Julius Werner | fa938c7 | 2013-08-29 14:17:36 -0700 | [diff] [blame] | 455 | reg = &exynos_clock->sclk_div_isp; |
Stefan Reinauer | 9fe20cb | 2012-12-07 17:18:43 -0800 | [diff] [blame] | 456 | shift = 12; |
| 457 | break; |
| 458 | default: |
Stefan Reinauer | 08dc357 | 2013-05-14 16:57:50 -0700 | [diff] [blame] | 459 | printk(BIOS_DEBUG, "%s: Unsupported peripheral ID %d\n", __func__, |
Stefan Reinauer | 9fe20cb | 2012-12-07 17:18:43 -0800 | [diff] [blame] | 460 | periph_id); |
| 461 | return; |
| 462 | } |
| 463 | clrsetbits_le32(reg, mask << shift, (divisor & mask) << shift); |
| 464 | } |
| 465 | |
| 466 | /** |
| 467 | * Linearly searches for the most accurate main and fine stage clock scalars |
| 468 | * (divisors) for a specified target frequency and scalar bit sizes by checking |
| 469 | * all multiples of main_scalar_bits values. Will always return scalars up to or |
| 470 | * slower than target. |
| 471 | * |
| 472 | * @param main_scalar_bits Number of main scalar bits, must be > 0 and < 32 |
| 473 | * @param fine_scalar_bits Number of fine scalar bits, must be > 0 and < 32 |
Martin Roth | 32bc6b6 | 2015-01-04 16:54:35 -0700 | [diff] [blame] | 474 | * @param input_rate Clock frequency to be scaled in Hz |
| 475 | * @param target_rate Desired clock frequency in Hz |
Stefan Reinauer | 9fe20cb | 2012-12-07 17:18:43 -0800 | [diff] [blame] | 476 | * @param best_fine_scalar Pointer to store the fine stage divisor |
| 477 | * |
| 478 | * @return best_main_scalar Main scalar for desired frequency or -1 if none |
| 479 | * found |
| 480 | */ |
| 481 | static int clock_calc_best_scalar(unsigned int main_scaler_bits, |
| 482 | unsigned int fine_scalar_bits, unsigned int input_rate, |
| 483 | unsigned int target_rate, unsigned int *best_fine_scalar) |
| 484 | { |
| 485 | int i; |
| 486 | int best_main_scalar = -1; |
| 487 | unsigned int best_error = target_rate; |
| 488 | const unsigned int cap = (1 << fine_scalar_bits) - 1; |
| 489 | const unsigned int loops = 1 << main_scaler_bits; |
| 490 | |
Stefan Reinauer | 08dc357 | 2013-05-14 16:57:50 -0700 | [diff] [blame] | 491 | printk(BIOS_DEBUG, "Input Rate is %u, Target is %u, Cap is %u\n", input_rate, |
Stefan Reinauer | 9fe20cb | 2012-12-07 17:18:43 -0800 | [diff] [blame] | 492 | target_rate, cap); |
| 493 | |
Stefan Reinauer | 08dc357 | 2013-05-14 16:57:50 -0700 | [diff] [blame] | 494 | ASSERT(best_fine_scalar != NULL); |
| 495 | ASSERT(main_scaler_bits <= fine_scalar_bits); |
Stefan Reinauer | 9fe20cb | 2012-12-07 17:18:43 -0800 | [diff] [blame] | 496 | |
| 497 | *best_fine_scalar = 1; |
| 498 | |
| 499 | if (input_rate == 0 || target_rate == 0) |
| 500 | return -1; |
| 501 | |
| 502 | if (target_rate >= input_rate) |
| 503 | return 1; |
| 504 | |
| 505 | for (i = 1; i <= loops; i++) { |
| 506 | const unsigned int effective_div = MAX(MIN(input_rate / i / |
| 507 | target_rate, cap), 1); |
| 508 | const unsigned int effective_rate = input_rate / i / |
| 509 | effective_div; |
| 510 | const int error = target_rate - effective_rate; |
| 511 | |
Stefan Reinauer | 08dc357 | 2013-05-14 16:57:50 -0700 | [diff] [blame] | 512 | printk(BIOS_DEBUG, "%d|effdiv:%u, effrate:%u, error:%d\n", i, effective_div, |
Stefan Reinauer | 9fe20cb | 2012-12-07 17:18:43 -0800 | [diff] [blame] | 513 | effective_rate, error); |
| 514 | |
| 515 | if (error >= 0 && error <= best_error) { |
| 516 | best_error = error; |
| 517 | best_main_scalar = i; |
| 518 | *best_fine_scalar = effective_div; |
| 519 | } |
| 520 | } |
| 521 | |
| 522 | return best_main_scalar; |
| 523 | } |
| 524 | |
| 525 | int clock_set_rate(enum periph_id periph_id, unsigned int rate) |
| 526 | { |
Patrick Georgi | 905e6f2 | 2014-08-14 20:23:51 +0200 | [diff] [blame] | 527 | int main_scalar; |
Stefan Reinauer | 9fe20cb | 2012-12-07 17:18:43 -0800 | [diff] [blame] | 528 | unsigned int fine; |
| 529 | |
| 530 | switch (periph_id) { |
| 531 | case PERIPH_ID_SPI0: |
| 532 | case PERIPH_ID_SPI1: |
| 533 | case PERIPH_ID_SPI2: |
| 534 | case PERIPH_ID_SPI3: |
| 535 | case PERIPH_ID_SPI4: |
Patrick Georgi | 905e6f2 | 2014-08-14 20:23:51 +0200 | [diff] [blame] | 536 | main_scalar = clock_calc_best_scalar(4, 8, 400000000, rate, &fine); |
| 537 | if (main_scalar < 0) { |
Stefan Reinauer | 08dc357 | 2013-05-14 16:57:50 -0700 | [diff] [blame] | 538 | printk(BIOS_DEBUG, "%s: Cannot set clock rate for periph %d", |
Stefan Reinauer | 9fe20cb | 2012-12-07 17:18:43 -0800 | [diff] [blame] | 539 | __func__, periph_id); |
| 540 | return -1; |
| 541 | } |
Patrick Georgi | 905e6f2 | 2014-08-14 20:23:51 +0200 | [diff] [blame] | 542 | clock_ll_set_ratio(periph_id, main_scalar - 1); |
Stefan Reinauer | 9fe20cb | 2012-12-07 17:18:43 -0800 | [diff] [blame] | 543 | clock_ll_set_pre_ratio(periph_id, fine - 1); |
| 544 | break; |
| 545 | default: |
Stefan Reinauer | 08dc357 | 2013-05-14 16:57:50 -0700 | [diff] [blame] | 546 | printk(BIOS_DEBUG, "%s: Unsupported peripheral ID %d\n", __func__, |
Stefan Reinauer | 9fe20cb | 2012-12-07 17:18:43 -0800 | [diff] [blame] | 547 | periph_id); |
| 548 | return -1; |
| 549 | } |
| 550 | |
| 551 | return 0; |
| 552 | } |
| 553 | |
| 554 | int clock_set_mshci(enum periph_id peripheral) |
| 555 | { |
Stefan Reinauer | 9fe20cb | 2012-12-07 17:18:43 -0800 | [diff] [blame] | 556 | u32 *addr; |
| 557 | unsigned int clock; |
| 558 | unsigned int tmp; |
| 559 | unsigned int i; |
| 560 | |
| 561 | /* get mpll clock */ |
| 562 | clock = get_pll_clk(MPLL) / 1000000; |
| 563 | |
| 564 | /* |
| 565 | * CLK_DIV_FSYS1 |
| 566 | * MMC0_PRE_RATIO [15:8], MMC0_RATIO [3:0] |
| 567 | * CLK_DIV_FSYS2 |
| 568 | * MMC2_PRE_RATIO [15:8], MMC2_RATIO [3:0] |
| 569 | */ |
| 570 | switch (peripheral) { |
| 571 | case PERIPH_ID_SDMMC0: |
Julius Werner | fa938c7 | 2013-08-29 14:17:36 -0700 | [diff] [blame] | 572 | addr = &exynos_clock->div_fsys1; |
Stefan Reinauer | 9fe20cb | 2012-12-07 17:18:43 -0800 | [diff] [blame] | 573 | break; |
| 574 | case PERIPH_ID_SDMMC2: |
Julius Werner | fa938c7 | 2013-08-29 14:17:36 -0700 | [diff] [blame] | 575 | addr = &exynos_clock->div_fsys2; |
Stefan Reinauer | 9fe20cb | 2012-12-07 17:18:43 -0800 | [diff] [blame] | 576 | break; |
| 577 | default: |
Stefan Reinauer | 08dc357 | 2013-05-14 16:57:50 -0700 | [diff] [blame] | 578 | printk(BIOS_DEBUG, "invalid peripheral\n"); |
Stefan Reinauer | 9fe20cb | 2012-12-07 17:18:43 -0800 | [diff] [blame] | 579 | return -1; |
| 580 | } |
Julius Werner | 2f37bd6 | 2015-02-19 14:51:15 -0800 | [diff] [blame] | 581 | tmp = read32(addr) & ~0xff0f; |
Stefan Reinauer | 9fe20cb | 2012-12-07 17:18:43 -0800 | [diff] [blame] | 582 | for (i = 0; i <= 0xf; i++) { |
| 583 | if ((clock / (i + 1)) <= 400) { |
Julius Werner | 2f37bd6 | 2015-02-19 14:51:15 -0800 | [diff] [blame] | 584 | write32(addr, tmp | i << 0); |
Stefan Reinauer | 9fe20cb | 2012-12-07 17:18:43 -0800 | [diff] [blame] | 585 | break; |
| 586 | } |
| 587 | } |
| 588 | return 0; |
| 589 | } |
| 590 | |
Stefan Reinauer | 9fe20cb | 2012-12-07 17:18:43 -0800 | [diff] [blame] | 591 | int clock_epll_set_rate(unsigned long rate) |
| 592 | { |
| 593 | unsigned int epll_con, epll_con_k; |
| 594 | unsigned int i; |
| 595 | unsigned int lockcnt; |
Aaron Durbin | 4393346 | 2014-09-24 10:27:29 -0500 | [diff] [blame] | 596 | struct stopwatch sw; |
Stefan Reinauer | 9fe20cb | 2012-12-07 17:18:43 -0800 | [diff] [blame] | 597 | |
Julius Werner | 2f37bd6 | 2015-02-19 14:51:15 -0800 | [diff] [blame] | 598 | epll_con = read32(&exynos_clock->epll_con0); |
Stefan Reinauer | 9fe20cb | 2012-12-07 17:18:43 -0800 | [diff] [blame] | 599 | epll_con &= ~((EPLL_CON0_LOCK_DET_EN_MASK << |
| 600 | EPLL_CON0_LOCK_DET_EN_SHIFT) | |
| 601 | EPLL_CON0_MDIV_MASK << EPLL_CON0_MDIV_SHIFT | |
| 602 | EPLL_CON0_PDIV_MASK << EPLL_CON0_PDIV_SHIFT | |
| 603 | EPLL_CON0_SDIV_MASK << EPLL_CON0_SDIV_SHIFT); |
| 604 | |
| 605 | for (i = 0; i < ARRAY_SIZE(epll_div); i++) { |
| 606 | if (epll_div[i].freq_out == rate) |
| 607 | break; |
| 608 | } |
| 609 | |
| 610 | if (i == ARRAY_SIZE(epll_div)) |
| 611 | return -1; |
| 612 | |
| 613 | epll_con_k = epll_div[i].k_dsm << 0; |
| 614 | epll_con |= epll_div[i].en_lock_det << EPLL_CON0_LOCK_DET_EN_SHIFT; |
| 615 | epll_con |= epll_div[i].m_div << EPLL_CON0_MDIV_SHIFT; |
| 616 | epll_con |= epll_div[i].p_div << EPLL_CON0_PDIV_SHIFT; |
| 617 | epll_con |= epll_div[i].s_div << EPLL_CON0_SDIV_SHIFT; |
| 618 | |
| 619 | /* |
Martin Roth | 4c3ab73 | 2013-07-08 16:23:54 -0600 | [diff] [blame] | 620 | * Required period ( in cycles) to generate a stable clock output. |
Stefan Reinauer | 9fe20cb | 2012-12-07 17:18:43 -0800 | [diff] [blame] | 621 | * The maximum clock time can be up to 3000 * PDIV cycles of PLLs |
| 622 | * frequency input (as per spec) |
| 623 | */ |
| 624 | lockcnt = 3000 * epll_div[i].p_div; |
| 625 | |
Julius Werner | 2f37bd6 | 2015-02-19 14:51:15 -0800 | [diff] [blame] | 626 | write32(&exynos_clock->epll_lock, lockcnt); |
| 627 | write32(&exynos_clock->epll_con0, epll_con); |
| 628 | write32(&exynos_clock->epll_con1, epll_con_k); |
Stefan Reinauer | 9fe20cb | 2012-12-07 17:18:43 -0800 | [diff] [blame] | 629 | |
Aaron Durbin | 4393346 | 2014-09-24 10:27:29 -0500 | [diff] [blame] | 630 | stopwatch_init_msecs_expire(&sw, TIMEOUT_EPLL_LOCK); |
Stefan Reinauer | 9fe20cb | 2012-12-07 17:18:43 -0800 | [diff] [blame] | 631 | |
Julius Werner | 2f37bd6 | 2015-02-19 14:51:15 -0800 | [diff] [blame] | 632 | while (!(read32(&exynos_clock->epll_con0) & |
Stefan Reinauer | 9fe20cb | 2012-12-07 17:18:43 -0800 | [diff] [blame] | 633 | (0x1 << EXYNOS5_EPLLCON0_LOCKED_SHIFT))) { |
Aaron Durbin | 4393346 | 2014-09-24 10:27:29 -0500 | [diff] [blame] | 634 | if (stopwatch_expired(&sw)) { |
| 635 | printk(BIOS_DEBUG, |
| 636 | "%s: Timeout waiting for EPLL lock\n", |
| 637 | __func__); |
Stefan Reinauer | 9fe20cb | 2012-12-07 17:18:43 -0800 | [diff] [blame] | 638 | return -1; |
| 639 | } |
| 640 | } |
| 641 | |
| 642 | return 0; |
| 643 | } |
| 644 | |
| 645 | void clock_select_i2s_clk_source(void) |
| 646 | { |
Julius Werner | fa938c7 | 2013-08-29 14:17:36 -0700 | [diff] [blame] | 647 | clrsetbits_le32(&exynos_clock->src_peric1, AUDIO1_SEL_MASK, |
Stefan Reinauer | 9fe20cb | 2012-12-07 17:18:43 -0800 | [diff] [blame] | 648 | (CLK_SRC_SCLK_EPLL)); |
| 649 | } |
| 650 | |
| 651 | int clock_set_i2s_clk_prescaler(unsigned int src_frq, unsigned int dst_frq) |
| 652 | { |
Stefan Reinauer | 9fe20cb | 2012-12-07 17:18:43 -0800 | [diff] [blame] | 653 | unsigned int div ; |
| 654 | |
| 655 | if ((dst_frq == 0) || (src_frq == 0)) { |
Martin Roth | 4c3ab73 | 2013-07-08 16:23:54 -0600 | [diff] [blame] | 656 | printk(BIOS_DEBUG, "%s: Invalid frequency input for prescaler\n", __func__); |
Stefan Reinauer | 08dc357 | 2013-05-14 16:57:50 -0700 | [diff] [blame] | 657 | printk(BIOS_DEBUG, "src frq = %d des frq = %d ", src_frq, dst_frq); |
Stefan Reinauer | 9fe20cb | 2012-12-07 17:18:43 -0800 | [diff] [blame] | 658 | return -1; |
| 659 | } |
| 660 | |
| 661 | div = (src_frq / dst_frq); |
| 662 | if (div > AUDIO_1_RATIO_MASK) { |
Stefan Reinauer | 08dc357 | 2013-05-14 16:57:50 -0700 | [diff] [blame] | 663 | printk(BIOS_DEBUG, "%s: Frequency ratio is out of range\n", __func__); |
| 664 | printk(BIOS_DEBUG, "src frq = %d des frq = %d ", src_frq, dst_frq); |
Stefan Reinauer | 9fe20cb | 2012-12-07 17:18:43 -0800 | [diff] [blame] | 665 | return -1; |
| 666 | } |
Julius Werner | fa938c7 | 2013-08-29 14:17:36 -0700 | [diff] [blame] | 667 | clrsetbits_le32(&exynos_clock->div_peric4, AUDIO_1_RATIO_MASK, |
Stefan Reinauer | 9fe20cb | 2012-12-07 17:18:43 -0800 | [diff] [blame] | 668 | (div & AUDIO_1_RATIO_MASK)); |
| 669 | return 0; |
| 670 | } |