Vadim Bendebury | 3cfb6a0 | 2015-02-11 15:13:04 -0800 | [diff] [blame] | 1 | /* |
| 2 | * Copyright (c) 2015, The Linux Foundation. All rights reserved. |
| 3 | * |
| 4 | * Redistribution and use in source and binary forms, with or without |
| 5 | * modification, are permitted provided that the following conditions are |
| 6 | * met: |
| 7 | * * Redistributions of source code must retain the above copyright |
| 8 | * notice, this list of conditions and the following disclaimer. |
| 9 | * * Redistributions in binary form must reproduce the above |
| 10 | * copyright notice, this list of conditions and the following |
| 11 | * disclaimer in the documentation and/or other materials provided |
| 12 | * with the distribution. |
| 13 | * * Neither the name of The Linux Foundation nor the names of its |
| 14 | * contributors may be used to endorse or promote products derived |
| 15 | * from this software without specific prior written permission. |
| 16 | * |
| 17 | * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED |
| 18 | * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF |
| 19 | * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT |
| 20 | * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS |
| 21 | * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR |
| 22 | * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF |
| 23 | * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR |
| 24 | * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, |
| 25 | * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE |
| 26 | * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN |
| 27 | * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
| 28 | */ |
| 29 | |
| 30 | #include <stdlib.h> |
| 31 | #include <stdint.h> |
| 32 | #include <delay.h> |
| 33 | #include <console/console.h> |
| 34 | #include <soc/clock.h> |
| 35 | #include <soc/lcc-reg.h> |
| 36 | #include <arch/io.h> |
| 37 | |
| 38 | typedef struct { |
| 39 | void *gcc_apcs_regs; |
| 40 | void *lcc_pll0_regs; |
| 41 | void *lcc_ahbix_regs; |
| 42 | void *lcc_mi2s_regs; |
| 43 | void *lcc_pll_regs; |
| 44 | } Ipq806xLccClocks; |
| 45 | |
| 46 | typedef struct __attribute__((packed)) { |
| 47 | uint32_t apcs; |
| 48 | } Ipq806xLccGccRegs; |
| 49 | |
| 50 | typedef struct __attribute__((packed)) { |
| 51 | uint32_t mode; |
| 52 | uint32_t l_val; |
| 53 | uint32_t m_val; |
| 54 | uint32_t n_val; |
| 55 | uint32_t UNUSED; |
| 56 | uint32_t config; |
| 57 | uint32_t status; |
| 58 | } Ipq806xLccPll0Regs; |
| 59 | |
| 60 | typedef struct __attribute__((packed)) { |
| 61 | uint32_t ns; |
| 62 | uint32_t md; |
| 63 | uint32_t UNUSED; |
| 64 | uint32_t status; |
| 65 | } Ipq806xLccAhbixRegs; |
| 66 | |
| 67 | typedef struct __attribute__((packed)) { |
| 68 | uint32_t ns; |
| 69 | uint32_t md; |
| 70 | uint32_t status; |
| 71 | } Ipq806xLccMi2sRegs; |
| 72 | |
| 73 | typedef struct __attribute__((packed)) { |
| 74 | uint32_t pri; |
| 75 | uint32_t sec; |
| 76 | } Ipq806xLccPllRegs; |
| 77 | |
| 78 | struct lcc_freq_tbl { |
| 79 | unsigned freq; |
| 80 | unsigned pd; |
| 81 | unsigned m; |
| 82 | unsigned n; |
| 83 | unsigned d; |
| 84 | }; |
| 85 | |
| 86 | static const struct lcc_freq_tbl lcc_mi2s_freq_tbl[] = { |
| 87 | { 1024000, 4, 1, 96, 8 }, |
| 88 | { 1411200, 4, 2, 139, 8 }, |
| 89 | { 1536000, 4, 1, 64, 8 }, |
| 90 | { 2048000, 4, 1, 48, 8 }, |
| 91 | { 2116800, 4, 2, 93, 8 }, |
| 92 | { 2304000, 4, 2, 85, 8 }, |
| 93 | { 2822400, 4, 6, 209, 8 }, |
| 94 | { 3072000, 4, 1, 32, 8 }, |
| 95 | { 3175200, 4, 1, 31, 8 }, |
| 96 | { 4096000, 4, 1, 24, 8 }, |
| 97 | { 4233600, 4, 9, 209, 8 }, |
| 98 | { 4608000, 4, 3, 64, 8 }, |
| 99 | { 5644800, 4, 12, 209, 8 }, |
| 100 | { 6144000, 4, 1, 16, 8 }, |
| 101 | { 6350400, 4, 2, 31, 8 }, |
| 102 | { 8192000, 4, 1, 12, 8 }, |
| 103 | { 8467200, 4, 18, 209, 8 }, |
| 104 | { 9216000, 4, 3, 32, 8 }, |
| 105 | { 11289600, 4, 24, 209, 8 }, |
| 106 | { 12288000, 4, 1, 8, 8 }, |
| 107 | { 12700800, 4, 27, 209, 8 }, |
| 108 | { 13824000, 4, 9, 64, 8 }, |
| 109 | { 16384000, 4, 1, 6, 8 }, |
| 110 | { 16934400, 4, 41, 238, 8 }, |
| 111 | { 18432000, 4, 3, 16, 8 }, |
| 112 | { 22579200, 2, 24, 209, 8 }, |
| 113 | { 24576000, 4, 1, 4, 8 }, |
| 114 | { 27648000, 4, 9, 32, 8 }, |
| 115 | { 33868800, 4, 41, 119, 8 }, |
| 116 | { 36864000, 4, 3, 8, 8 }, |
| 117 | { 45158400, 1, 24, 209, 8 }, |
| 118 | { 49152000, 4, 1, 2, 8 }, |
| 119 | { 50803200, 1, 27, 209, 8 }, |
| 120 | { } |
| 121 | }; |
| 122 | |
| 123 | static int lcc_init_enable_pll0(Ipq806xLccClocks *bus) |
| 124 | { |
| 125 | Ipq806xLccGccRegs *gcc_regs = bus->gcc_apcs_regs; |
| 126 | Ipq806xLccPll0Regs *pll0_regs = bus->lcc_pll0_regs; |
| 127 | Ipq806xLccPllRegs *pll_regs = bus->lcc_pll_regs; |
| 128 | uint32_t regval; |
| 129 | |
| 130 | regval = 0; |
| 131 | regval = 15 << LCC_PLL0_L_SHIFT & LCC_PLL0_L_MASK; |
Julius Werner | 2f37bd6 | 2015-02-19 14:51:15 -0800 | [diff] [blame] | 132 | write32(&pll0_regs->l_val, regval); |
Vadim Bendebury | 3cfb6a0 | 2015-02-11 15:13:04 -0800 | [diff] [blame] | 133 | |
| 134 | regval = 0; |
| 135 | regval = 145 << LCC_PLL0_M_SHIFT & LCC_PLL0_M_MASK; |
Julius Werner | 2f37bd6 | 2015-02-19 14:51:15 -0800 | [diff] [blame] | 136 | write32(&pll0_regs->m_val, regval); |
Vadim Bendebury | 3cfb6a0 | 2015-02-11 15:13:04 -0800 | [diff] [blame] | 137 | |
| 138 | regval = 0; |
| 139 | regval = 199 << LCC_PLL0_N_SHIFT & LCC_PLL0_N_MASK; |
Julius Werner | 2f37bd6 | 2015-02-19 14:51:15 -0800 | [diff] [blame] | 140 | write32(&pll0_regs->n_val, regval); |
Vadim Bendebury | 3cfb6a0 | 2015-02-11 15:13:04 -0800 | [diff] [blame] | 141 | |
| 142 | regval = 0; |
| 143 | regval |= LCC_PLL0_CFG_LV_MAIN_ENABLE; |
| 144 | regval |= LCC_PLL0_CFG_FRAC_ENABLE; |
Julius Werner | 2f37bd6 | 2015-02-19 14:51:15 -0800 | [diff] [blame] | 145 | write32(&pll0_regs->config, regval); |
Vadim Bendebury | 3cfb6a0 | 2015-02-11 15:13:04 -0800 | [diff] [blame] | 146 | |
| 147 | regval = 0; |
| 148 | regval |= LCC_PLL_PCLK_SRC_PRI; |
Julius Werner | 2f37bd6 | 2015-02-19 14:51:15 -0800 | [diff] [blame] | 149 | write32(&pll_regs->pri, regval); |
Vadim Bendebury | 3cfb6a0 | 2015-02-11 15:13:04 -0800 | [diff] [blame] | 150 | |
| 151 | regval = 0; |
| 152 | regval |= 1 << LCC_PLL0_MODE_BIAS_CNT_SHIFT & |
| 153 | LCC_PLL0_MODE_BIAS_CNT_MASK; |
| 154 | regval |= 8 << LCC_PLL0_MODE_LOCK_CNT_SHIFT & |
| 155 | LCC_PLL0_MODE_LOCK_CNT_MASK; |
Julius Werner | 2f37bd6 | 2015-02-19 14:51:15 -0800 | [diff] [blame] | 156 | write32(&pll0_regs->mode, regval); |
Vadim Bendebury | 3cfb6a0 | 2015-02-11 15:13:04 -0800 | [diff] [blame] | 157 | |
Julius Werner | 2f37bd6 | 2015-02-19 14:51:15 -0800 | [diff] [blame] | 158 | regval = read32(&gcc_regs->apcs); |
Vadim Bendebury | 3cfb6a0 | 2015-02-11 15:13:04 -0800 | [diff] [blame] | 159 | regval |= GCC_PLL_APCS_PLL4_ENABLE; |
Julius Werner | 2f37bd6 | 2015-02-19 14:51:15 -0800 | [diff] [blame] | 160 | write32(&gcc_regs->apcs, regval); |
Vadim Bendebury | 3cfb6a0 | 2015-02-11 15:13:04 -0800 | [diff] [blame] | 161 | |
Julius Werner | 2f37bd6 | 2015-02-19 14:51:15 -0800 | [diff] [blame] | 162 | regval = read32(&pll0_regs->mode); |
Vadim Bendebury | 3cfb6a0 | 2015-02-11 15:13:04 -0800 | [diff] [blame] | 163 | regval |= LCC_PLL0_MODE_FSM_VOTE_ENABLE; |
Julius Werner | 2f37bd6 | 2015-02-19 14:51:15 -0800 | [diff] [blame] | 164 | write32(&pll0_regs->mode, regval); |
Vadim Bendebury | 3cfb6a0 | 2015-02-11 15:13:04 -0800 | [diff] [blame] | 165 | |
| 166 | mdelay(1); |
| 167 | |
Julius Werner | 2f37bd6 | 2015-02-19 14:51:15 -0800 | [diff] [blame] | 168 | regval = read32(&pll0_regs->status); |
Vadim Bendebury | 3cfb6a0 | 2015-02-11 15:13:04 -0800 | [diff] [blame] | 169 | if (regval & LCC_PLL0_STAT_ACTIVE_MASK) |
| 170 | return 0; |
| 171 | |
| 172 | printk(BIOS_ERR, "%s: error enabling PLL4 clock\n", __func__); |
| 173 | return 1; |
| 174 | } |
| 175 | |
| 176 | static int lcc_init_enable_ahbix(Ipq806xLccClocks *bus) |
| 177 | { |
| 178 | Ipq806xLccAhbixRegs *ahbix_regs = bus->lcc_ahbix_regs; |
| 179 | uint32_t regval; |
| 180 | |
| 181 | regval = 0; |
| 182 | regval |= 1 << LCC_AHBIX_MD_M_VAL_SHIFT & LCC_AHBIX_MD_M_VAL_MASK; |
| 183 | regval |= 252 << LCC_AHBIX_MD_NOT_2D_VAL_SHIFT & |
| 184 | LCC_AHBIX_MD_NOT_2D_VAL_MASK; |
Julius Werner | 2f37bd6 | 2015-02-19 14:51:15 -0800 | [diff] [blame] | 185 | write32(&ahbix_regs->md, regval); |
Vadim Bendebury | 3cfb6a0 | 2015-02-11 15:13:04 -0800 | [diff] [blame] | 186 | |
| 187 | regval = 0; |
| 188 | regval |= 253 << LCC_AHBIX_NS_N_VAL_SHIFT & LCC_AHBIX_NS_N_VAL_MASK; |
| 189 | regval |= LCC_AHBIX_NS_CRC_ENABLE; |
| 190 | regval |= LCC_AHBIX_NS_GFM_SEL_MNC; |
| 191 | regval |= LCC_AHBIX_NS_MNC_CLK_ENABLE; |
| 192 | regval |= LCC_AHBIX_NS_MNC_ENABLE; |
| 193 | regval |= LCC_AHBIX_NS_MNC_MODE_DUAL; |
| 194 | regval |= LCC_AHBIX_NS_PREDIV_BYPASS; |
| 195 | regval |= LCC_AHBIX_NS_MN_SRC_LPA; |
Julius Werner | 2f37bd6 | 2015-02-19 14:51:15 -0800 | [diff] [blame] | 196 | write32(&ahbix_regs->ns, regval); |
Vadim Bendebury | 3cfb6a0 | 2015-02-11 15:13:04 -0800 | [diff] [blame] | 197 | |
| 198 | mdelay(1); |
| 199 | |
Julius Werner | 2f37bd6 | 2015-02-19 14:51:15 -0800 | [diff] [blame] | 200 | regval = read32(&ahbix_regs->status); |
Vadim Bendebury | 3cfb6a0 | 2015-02-11 15:13:04 -0800 | [diff] [blame] | 201 | if (regval & LCC_AHBIX_STAT_AIF_CLK_MASK) |
| 202 | return 0; |
| 203 | |
| 204 | printk(BIOS_ERR, "%s: error enabling AHBIX clock\n", __func__); |
| 205 | return 1; |
| 206 | } |
| 207 | |
| 208 | static int lcc_init_mi2s(Ipq806xLccClocks *bus, unsigned freq) |
| 209 | { |
| 210 | Ipq806xLccMi2sRegs *mi2s_regs = bus->lcc_mi2s_regs; |
| 211 | uint32_t regval; |
| 212 | uint8_t pd, m, n, d; |
| 213 | unsigned i; |
| 214 | |
| 215 | i = 0; |
| 216 | while (lcc_mi2s_freq_tbl[i].freq != 0) { |
| 217 | if (lcc_mi2s_freq_tbl[i].freq == freq) |
| 218 | break; |
| 219 | ++i; |
| 220 | } |
| 221 | if (lcc_mi2s_freq_tbl[i].freq == 0) { |
| 222 | printk(BIOS_ERR, "%s: invalid frequency given: %u\n", |
| 223 | __func__, freq); |
| 224 | return 1; |
| 225 | } |
| 226 | |
| 227 | switch (lcc_mi2s_freq_tbl[i].pd) { |
| 228 | case 1: |
| 229 | pd = LCC_MI2S_NS_PREDIV_BYPASS; |
| 230 | break; |
| 231 | case 2: |
| 232 | pd = LCC_MI2S_NS_PREDIV_DIV2; |
| 233 | break; |
| 234 | case 4: |
| 235 | pd = LCC_MI2S_NS_PREDIV_DIV4; |
| 236 | break; |
| 237 | default: |
| 238 | printk(BIOS_ERR, "%s: invalid prediv found: %u\n", __func__, |
| 239 | lcc_mi2s_freq_tbl[i].pd); |
| 240 | return 1; |
| 241 | } |
| 242 | |
| 243 | m = lcc_mi2s_freq_tbl[i].m; |
| 244 | n = ~(lcc_mi2s_freq_tbl[i].n - m); |
| 245 | d = ~(lcc_mi2s_freq_tbl[i].d * 2); |
| 246 | |
| 247 | regval = 0; |
| 248 | regval |= m << LCC_MI2S_MD_M_VAL_SHIFT & LCC_MI2S_MD_M_VAL_MASK; |
| 249 | regval |= d << LCC_MI2S_MD_NOT_2D_VAL_SHIFT & |
| 250 | LCC_MI2S_MD_NOT_2D_VAL_MASK; |
Julius Werner | 2f37bd6 | 2015-02-19 14:51:15 -0800 | [diff] [blame] | 251 | write32(&mi2s_regs->md, regval); |
Vadim Bendebury | 3cfb6a0 | 2015-02-11 15:13:04 -0800 | [diff] [blame] | 252 | |
| 253 | regval = 0; |
| 254 | regval |= n << LCC_MI2S_NS_N_VAL_SHIFT & LCC_MI2S_NS_N_VAL_MASK; |
| 255 | regval |= LCC_MI2S_NS_BIT_DIV_DIV4; |
| 256 | regval |= LCC_MI2S_NS_MNC_CLK_ENABLE; |
| 257 | regval |= LCC_MI2S_NS_MNC_ENABLE; |
| 258 | regval |= LCC_MI2S_NS_MNC_MODE_DUAL; |
| 259 | regval |= pd; |
| 260 | regval |= LCC_MI2S_NS_MN_SRC_LPA; |
Julius Werner | 2f37bd6 | 2015-02-19 14:51:15 -0800 | [diff] [blame] | 261 | write32(&mi2s_regs->ns, regval); |
Vadim Bendebury | 3cfb6a0 | 2015-02-11 15:13:04 -0800 | [diff] [blame] | 262 | |
| 263 | return 0; |
| 264 | } |
| 265 | |
| 266 | static int lcc_enable_mi2s(Ipq806xLccClocks *bus) |
| 267 | { |
| 268 | Ipq806xLccMi2sRegs *mi2s_regs = bus->lcc_mi2s_regs; |
| 269 | uint32_t regval; |
| 270 | |
Julius Werner | 2f37bd6 | 2015-02-19 14:51:15 -0800 | [diff] [blame] | 271 | regval = read32(&mi2s_regs->ns); |
Vadim Bendebury | 3cfb6a0 | 2015-02-11 15:13:04 -0800 | [diff] [blame] | 272 | regval |= LCC_MI2S_NS_OSR_CXC_ENABLE; |
| 273 | regval |= LCC_MI2S_NS_BIT_CXC_ENABLE; |
Julius Werner | 2f37bd6 | 2015-02-19 14:51:15 -0800 | [diff] [blame] | 274 | write32(&mi2s_regs->ns, regval); |
Vadim Bendebury | 3cfb6a0 | 2015-02-11 15:13:04 -0800 | [diff] [blame] | 275 | |
| 276 | udelay(10); |
| 277 | |
Julius Werner | 2f37bd6 | 2015-02-19 14:51:15 -0800 | [diff] [blame] | 278 | regval = read32(&mi2s_regs->status); |
Vadim Bendebury | 3cfb6a0 | 2015-02-11 15:13:04 -0800 | [diff] [blame] | 279 | if (regval & LCC_MI2S_STAT_OSR_CLK_MASK) |
| 280 | if (regval & LCC_MI2S_STAT_BIT_CLK_MASK) |
| 281 | return 0; |
| 282 | |
| 283 | printk(BIOS_ERR, "%s: error enabling MI2S clocks: %u\n", |
| 284 | __func__, regval); |
| 285 | return 1; |
| 286 | } |
| 287 | |
| 288 | int audio_clock_config(unsigned frequency) |
| 289 | { |
| 290 | Ipq806xLccClocks *bus = malloc(sizeof(*bus)); |
| 291 | |
| 292 | if (!bus) { |
| 293 | printk(BIOS_ERR, "%s: failed to allocate bus structure\n", |
| 294 | __func__); |
| 295 | return 1; |
| 296 | } |
| 297 | |
| 298 | bus->gcc_apcs_regs = (void *)(MSM_GCC_BASE + GCC_PLL_APCS_REG); |
| 299 | bus->lcc_pll0_regs = (void *)(MSM_LPASS_LCC_BASE + LCC_PLL0_MODE_REG); |
| 300 | bus->lcc_ahbix_regs = (void *)(MSM_LPASS_LCC_BASE + LCC_AHBIX_NS_REG); |
| 301 | bus->lcc_mi2s_regs = (void *)(MSM_LPASS_LCC_BASE + LCC_MI2S_NS_REG); |
| 302 | bus->lcc_pll_regs = (void *)(MSM_LPASS_LCC_BASE + LCC_PLL_PCLK_REG); |
| 303 | |
| 304 | |
| 305 | if (lcc_init_enable_pll0(bus)) |
| 306 | return 1; |
| 307 | if (lcc_init_enable_ahbix(bus)) |
| 308 | return 1; |
| 309 | if (lcc_init_mi2s(bus, frequency)) |
| 310 | return 1; |
| 311 | |
| 312 | if (lcc_enable_mi2s(bus)) |
| 313 | return 1; |
| 314 | |
| 315 | return 0; |
| 316 | } |