Patrick Georgi | 40a3e32 | 2015-06-22 19:41:29 +0200 | [diff] [blame] | 1 | /* |
| 2 | * This file is part of the coreboot project. |
| 3 | * |
| 4 | * Copyright 2014 Google Inc. |
| 5 | * |
| 6 | * This program is free software; you can redistribute it and/or modify |
| 7 | * it under the terms of the GNU General Public License as published by |
| 8 | * the Free Software Foundation; version 2 of the License. |
| 9 | * |
| 10 | * This program is distributed in the hope that it will be useful, |
| 11 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 12 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 13 | * GNU General Public License for more details. |
Patrick Georgi | 40a3e32 | 2015-06-22 19:41:29 +0200 | [diff] [blame] | 14 | */ |
| 15 | |
| 16 | #include <arch/io.h> |
| 17 | #include <cbfs.h> |
| 18 | #include <console/console.h> |
| 19 | #include <soc/addressmap.h> |
| 20 | #include <soc/clock.h> |
| 21 | #include <soc/clk_rst.h> |
| 22 | #include <soc/ccplex.h> |
| 23 | #include <soc/cpu.h> |
| 24 | #include <soc/flow.h> |
| 25 | #include <soc/mc.h> |
| 26 | #include <soc/pmc.h> |
| 27 | #include <soc/power.h> |
| 28 | #include <soc/romstage.h> |
| 29 | #include <string.h> |
| 30 | #include <timer.h> |
| 31 | |
| 32 | #define PMC_REGS (void *)(uintptr_t)(TEGRA_PMC_BASE) |
| 33 | |
| 34 | static void enable_cpu_clocks(void) |
| 35 | { |
| 36 | clock_enable(CLK_ENB_CPU, 0, 0, SET_CLK_ENB_CPUG_ENABLE | |
| 37 | SET_CLK_ENB_CPULP_ENABLE, 0, 0, 0); |
| 38 | } |
| 39 | |
| 40 | static void enable_cpu_power_partitions(void) |
| 41 | { |
| 42 | /* Bring up fast cluster, non-CPU, CPU0, CPU1, CPU2 and CPU3 parts. */ |
| 43 | power_ungate_partition(POWER_PARTID_CRAIL); |
| 44 | power_ungate_partition(POWER_PARTID_C0NC); |
| 45 | power_ungate_partition(POWER_PARTID_CE0); |
Patrick Georgi | 40a3e32 | 2015-06-22 19:41:29 +0200 | [diff] [blame] | 46 | |
| 47 | if (IS_ENABLED(CONFIG_ARM64_USE_ARM_TRUSTED_FIRMWARE)) { |
| 48 | /* |
| 49 | * Deassert reset signal of all the secondary CPUs. |
| 50 | * PMC and flow controller will take over the power sequence |
| 51 | * controller in the ATF. |
| 52 | */ |
| 53 | uint32_t reg = CRC_RST_CPUG_CLR_CPU1 | CRC_RST_CPUG_CLR_DBG1 | |
| 54 | CRC_RST_CPUG_CLR_CORE1 | CRC_RST_CPUG_CLR_CX1 | |
| 55 | CRC_RST_CPUG_CLR_CPU2 | CRC_RST_CPUG_CLR_DBG2 | |
| 56 | CRC_RST_CPUG_CLR_CORE2 | CRC_RST_CPUG_CLR_CX2 | |
| 57 | CRC_RST_CPUG_CLR_CPU3 | CRC_RST_CPUG_CLR_DBG3 | |
| 58 | CRC_RST_CPUG_CLR_CORE3 | CRC_RST_CPUG_CLR_CX3; |
| 59 | write32(CLK_RST_REG(rst_cpug_cmplx_clr), reg); |
| 60 | } |
| 61 | } |
| 62 | |
| 63 | static void request_ram_repair(void) |
| 64 | { |
| 65 | struct flow_ctlr * const flow = (void *)(uintptr_t)TEGRA_FLOW_BASE; |
| 66 | const uint32_t req = 1 << 0; |
| 67 | const uint32_t sts = 1 << 1; |
| 68 | uint32_t reg; |
| 69 | struct stopwatch sw; |
| 70 | |
| 71 | printk(BIOS_DEBUG, "Requesting RAM repair.\n"); |
| 72 | |
| 73 | stopwatch_init(&sw); |
| 74 | |
| 75 | /* Perform ram repair */ |
| 76 | reg = read32(&flow->ram_repair); |
| 77 | reg |= req; |
| 78 | write32(&flow->ram_repair, reg); |
| 79 | while ((read32(&flow->ram_repair) & sts) != sts) |
| 80 | ; |
| 81 | |
| 82 | printk(BIOS_DEBUG, "RAM repair complete in %ld usecs.\n", |
| 83 | stopwatch_duration_usecs(&sw)); |
| 84 | } |
| 85 | |
Yen Lin | cad9e7a | 2015-05-06 13:56:50 -0700 | [diff] [blame] | 86 | static void set_cpu_ack_width(uint32_t val) |
| 87 | { |
| 88 | uint32_t reg; |
| 89 | |
| 90 | reg = read32(CLK_RST_REG(cpu_softrst_ctrl2)); |
| 91 | reg &= ~CAR2PMC_CPU_ACK_WIDTH_MASK; |
| 92 | reg |= val; |
| 93 | write32(CLK_RST_REG(cpu_softrst_ctrl2), reg); |
| 94 | } |
| 95 | |
Patrick Georgi | 40a3e32 | 2015-06-22 19:41:29 +0200 | [diff] [blame] | 96 | void ccplex_cpu_prepare(void) |
| 97 | { |
| 98 | enable_cpu_clocks(); |
Yen Lin | cad9e7a | 2015-05-06 13:56:50 -0700 | [diff] [blame] | 99 | |
| 100 | /* |
| 101 | * The POR value of CAR2PMC_CPU_ACK_WIDTH is 0x200. |
| 102 | * The recommended value is 0. |
| 103 | */ |
| 104 | set_cpu_ack_width(0); |
| 105 | |
Patrick Georgi | 40a3e32 | 2015-06-22 19:41:29 +0200 | [diff] [blame] | 106 | enable_cpu_power_partitions(); |
| 107 | |
| 108 | mainboard_configure_pmc(); |
| 109 | mainboard_enable_vdd_cpu(); |
| 110 | |
| 111 | request_ram_repair(); |
| 112 | } |
| 113 | |
| 114 | static void start_common_clocks(void) |
| 115 | { |
| 116 | /* Clear fast CPU partition reset. */ |
| 117 | write32(CLK_RST_REG(rst_cpug_cmplx_clr), CRC_RST_CPUG_CLR_NONCPU); |
| 118 | |
| 119 | /* Clear reset of L2 and CoreSight components. */ |
| 120 | write32(CLK_RST_REG(rst_cpug_cmplx_clr), |
| 121 | CRC_RST_CPUG_CLR_L2 | CRC_RST_CPUG_CLR_PDBG); |
| 122 | } |
| 123 | |
| 124 | void ccplex_cpu_start(void *entry_addr) |
| 125 | { |
| 126 | /* Enable common clocks for the shared resources between the cores. */ |
| 127 | start_common_clocks(); |
| 128 | |
| 129 | start_cpu(0, entry_addr); |
| 130 | } |