Tom Warren | 2525885 | 2014-07-15 10:34:19 -0700 | [diff] [blame] | 1 | /* |
| 2 | * This file is part of the coreboot project. |
| 3 | * |
| 4 | * Copyright (C) 2011 The ChromiumOS Authors. All rights reserved. |
| 5 | * Copyright 2014 Google Inc. |
| 6 | * |
| 7 | * This program is free software; you can redistribute it and/or modify |
| 8 | * it under the terms of the GNU General Public License as published by |
| 9 | * the Free Software Foundation; version 2 of the License. |
| 10 | * |
| 11 | * This program is distributed in the hope that it will be useful, |
| 12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 14 | * GNU General Public License for more details. |
Tom Warren | 2525885 | 2014-07-15 10:34:19 -0700 | [diff] [blame] | 15 | */ |
| 16 | |
Tom Warren | 2525885 | 2014-07-15 10:34:19 -0700 | [diff] [blame] | 17 | #include <arch/io.h> |
Aaron Durbin | 127f051 | 2014-08-28 09:46:10 -0500 | [diff] [blame] | 18 | #include <arch/cache.h> |
Aaron Durbin | b6a81fa | 2014-09-06 02:36:40 -0500 | [diff] [blame] | 19 | #include <cpu/cpu.h> |
Aaron Durbin | bc98cc6 | 2015-09-02 09:21:36 -0500 | [diff] [blame] | 20 | #include <bootmode.h> |
Aaron Durbin | 2962d1e | 2014-11-19 12:01:39 -0600 | [diff] [blame] | 21 | #include <bootstate.h> |
Aaron Durbin | 127f051 | 2014-08-28 09:46:10 -0500 | [diff] [blame] | 22 | #include <cbmem.h> |
Julius Werner | 96195ee | 2014-10-20 13:25:21 -0700 | [diff] [blame] | 23 | #include <console/console.h> |
| 24 | #include <device/device.h> |
Jimmy Zhang | 1f4db404 | 2014-11-03 11:41:02 -0800 | [diff] [blame] | 25 | #include <soc/nvidia/tegra/dc.h> |
Tom Warren | 2525885 | 2014-07-15 10:34:19 -0700 | [diff] [blame] | 26 | #include <soc/addressmap.h> |
Furquan Shaikh | eb5e588 | 2014-08-15 15:26:01 -0700 | [diff] [blame] | 27 | #include <soc/clock.h> |
Aaron Durbin | 79eb2b3 | 2014-08-27 17:51:19 -0500 | [diff] [blame] | 28 | #include <soc/cpu.h> |
Aaron Durbin | bf53418 | 2014-08-04 11:40:45 -0500 | [diff] [blame] | 29 | #include <soc/nvidia/tegra/apbmisc.h> |
Julius Werner | 96195ee | 2014-10-20 13:25:21 -0700 | [diff] [blame] | 30 | #include <string.h> |
| 31 | #include <timer.h> |
Julius Werner | 96195ee | 2014-10-20 13:25:21 -0700 | [diff] [blame] | 32 | |
Aaron Durbin | 79eb2b3 | 2014-08-27 17:51:19 -0500 | [diff] [blame] | 33 | #include "chip.h" |
Tom Warren | 2525885 | 2014-07-15 10:34:19 -0700 | [diff] [blame] | 34 | |
| 35 | static void soc_read_resources(device_t dev) |
| 36 | { |
| 37 | unsigned long index = 0; |
| 38 | int i; uintptr_t begin, end; |
| 39 | size_t size; |
| 40 | |
Tom Warren | 2525885 | 2014-07-15 10:34:19 -0700 | [diff] [blame] | 41 | for (i = 0; i < CARVEOUT_NUM; i++) { |
| 42 | carveout_range(i, &begin, &size); |
| 43 | if (size == 0) |
| 44 | continue; |
| 45 | reserved_ram_resource(dev, index++, begin * KiB, size * KiB); |
| 46 | } |
| 47 | |
Tom Warren | 2525885 | 2014-07-15 10:34:19 -0700 | [diff] [blame] | 48 | memory_in_range_below_4gb(&begin, &end); |
| 49 | size = end - begin; |
| 50 | ram_resource(dev, index++, begin * KiB, size * KiB); |
| 51 | |
| 52 | memory_in_range_above_4gb(&begin, &end); |
| 53 | size = end - begin; |
| 54 | ram_resource(dev, index++, begin * KiB, size * KiB); |
| 55 | } |
| 56 | |
Furquan Shaikh | fdb3a8d | 2015-10-15 15:50:30 -0700 | [diff] [blame] | 57 | static struct device_operations soc_ops = { |
| 58 | .read_resources = soc_read_resources, |
| 59 | .set_resources = DEVICE_NOOP, |
| 60 | .enable_resources = DEVICE_NOOP, |
| 61 | .init = DEVICE_NOOP, |
| 62 | .scan_bus = NULL, |
| 63 | }; |
| 64 | |
| 65 | static void enable_tegra132_dev(device_t dev) |
Aaron Durbin | 47f18d4 | 2015-01-23 14:13:23 -0600 | [diff] [blame] | 66 | { |
Furquan Shaikh | fdb3a8d | 2015-10-15 15:50:30 -0700 | [diff] [blame] | 67 | if (dev->path.type == DEVICE_PATH_CPU_CLUSTER) |
| 68 | dev->ops = &soc_ops; |
Aaron Durbin | 47f18d4 | 2015-01-23 14:13:23 -0600 | [diff] [blame] | 69 | |
Aaron Durbin | bc98cc6 | 2015-09-02 09:21:36 -0500 | [diff] [blame] | 70 | if (!IS_ENABLED(CONFIG_MAINBOARD_DO_NATIVE_VGA_INIT)) |
| 71 | return; |
| 72 | |
| 73 | if (display_init_required()) |
Jimmy Zhang | 1f4db404 | 2014-11-03 11:41:02 -0800 | [diff] [blame] | 74 | display_startup(dev); |
Aaron Durbin | bc98cc6 | 2015-09-02 09:21:36 -0500 | [diff] [blame] | 75 | else |
| 76 | printk(BIOS_INFO, "Skipping display init.\n"); |
Tom Warren | 2525885 | 2014-07-15 10:34:19 -0700 | [diff] [blame] | 77 | } |
| 78 | |
Aaron Durbin | bf53418 | 2014-08-04 11:40:45 -0500 | [diff] [blame] | 79 | static void tegra132_init(void *chip_info) |
| 80 | { |
| 81 | struct tegra_revision rev; |
| 82 | |
| 83 | tegra_revision_info(&rev); |
| 84 | |
| 85 | printk(BIOS_INFO, "chip %x rev %02x.%x\n", |
| 86 | rev.chip_id, rev.major, rev.minor); |
| 87 | |
Aaron Durbin | 159aa12 | 2014-09-09 11:58:18 -0500 | [diff] [blame] | 88 | printk(BIOS_INFO, "MTS build %u\n", raw_read_aidr_el1()); |
Aaron Durbin | bf53418 | 2014-08-04 11:40:45 -0500 | [diff] [blame] | 89 | } |
| 90 | |
Tom Warren | 2525885 | 2014-07-15 10:34:19 -0700 | [diff] [blame] | 91 | struct chip_operations soc_nvidia_tegra132_ops = { |
| 92 | CHIP_NAME("SOC Nvidia Tegra132") |
Aaron Durbin | bf53418 | 2014-08-04 11:40:45 -0500 | [diff] [blame] | 93 | .init = tegra132_init, |
Tom Warren | 2525885 | 2014-07-15 10:34:19 -0700 | [diff] [blame] | 94 | .enable_dev = enable_tegra132_dev, |
| 95 | }; |
Aaron Durbin | b6a81fa | 2014-09-06 02:36:40 -0500 | [diff] [blame] | 96 | |
Aaron Durbin | 2962d1e | 2014-11-19 12:01:39 -0600 | [diff] [blame] | 97 | static void enable_plld(void *unused) |
| 98 | { |
| 99 | /* |
| 100 | * Configure a conservative 300MHz clock for PLLD. The kernel cannot |
| 101 | * handle PLLD not being configured so enable PLLD unconditionally |
| 102 | * with a default clock rate. |
| 103 | */ |
| 104 | clock_configure_plld(300 * MHz); |
| 105 | } |
| 106 | |
| 107 | /* |
| 108 | * The PLLD being enabled is done at BS_DEV_INIT time because mainboard_init() |
| 109 | * is the first thing called. This ensures PLLD is up and functional before |
| 110 | * anything that mainboard can do that implicitly relies on PLLD. |
| 111 | */ |
| 112 | BOOT_STATE_INIT_ENTRY(BS_DEV_INIT, BS_ON_ENTRY, enable_plld, NULL); |