| Aaron Durbin | 4058d7b | 2014-08-22 10:24:27 -0500 | [diff] [blame] | 1 | /* |
| 2 | * This file is part of the coreboot project. |
| 3 | * |
| 4 | * Copyright 2014 Google Inc. |
| 5 | * |
| 6 | * This program is free software; you can redistribute it and/or modify |
| 7 | * it under the terms of the GNU General Public License as published by |
| 8 | * the Free Software Foundation; version 2 of the License. |
| 9 | * |
| 10 | * This program is distributed in the hope that it will be useful, |
| 11 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 12 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 13 | * GNU General Public License for more details. |
| Aaron Durbin | 4058d7b | 2014-08-22 10:24:27 -0500 | [diff] [blame] | 14 | */ |
| 15 | |
| 16 | /* |
| 17 | * This code is compiled for both arm64 and arm4, however the code is only |
| 18 | * executed by the armv8 cores coming out of reset. |
| 19 | */ |
| 20 | |
| 21 | #if !defined(__PRE_RAM__) |
| 22 | #define INST .inst |
| 23 | #else |
| 24 | #define INST .word |
| 25 | #endif |
| 26 | |
| 27 | /* |
| 28 | * The Denver cores come up in aarch32 mode. In order to transition to |
| 29 | * 64-bit mode a write to the RMR (reest mangement register) with the |
| 30 | * AA64 bit (0) set while setting RR (reset request bit 1). |
| 31 | */ |
| 32 | .align 6 |
| 33 | .global reset_entry_32bit |
| 34 | reset_entry_32bit: |
| 35 | INST 0xe3a00003 /* mov r0, #3 */ |
| 36 | INST 0xee0c0f50 /* mcr 15, 0, r0, cr12, cr0, {2} */ |
| 37 | INST 0xeafffffe /* b . */ |