blob: cebe405522d36b317db94f6bc9e84685a54cb4e2 [file] [log] [blame]
Gabe Black396b0722013-09-26 16:22:09 -07001/*
2 * This file is part of the coreboot project.
3 *
4 * Copyright 2013 Google Inc.
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; version 2 of the License.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
Gabe Black396b0722013-09-26 16:22:09 -070014 */
15
Jimmy Zhangb3655302014-07-02 17:45:18 -070016#include <assert.h>
Julius Werner85620db2013-11-13 18:22:15 -080017#include <arch/exception.h>
Stefan Reinauera9bc3bf2015-07-09 00:18:03 +020018#include <arch/stages.h>
Gabe Blackd40be112013-10-09 23:45:07 -070019#include <bootblock_common.h>
Gabe Black7f074752013-09-29 06:32:27 -070020#include <cbfs.h>
21#include <console/console.h>
Aaron Durbin825a5a82015-03-20 16:42:17 -050022#include <program_loading.h>
Gabe Blackd40be112013-10-09 23:45:07 -070023#include <soc/clock.h>
Jimmy Zhangbf04eda2014-02-11 17:21:20 -080024#include <soc/nvidia/tegra/apbmisc.h>
Julius Wernerf0d21ff32014-10-20 13:24:14 -070025#include <soc/pinmux.h>
26#include <soc/power.h>
Daisuke Nojiri1b05d882014-08-27 11:48:03 -070027#include <vendorcode/google/chromeos/chromeos.h>
Gabe Blackca436cb2013-09-29 07:06:08 -070028
Aaron Durbin825a5a82015-03-20 16:42:17 -050029static void run_next_stage(void *entry)
30{
31 ASSERT(entry);
32 clock_cpu0_config(entry);
33
34 power_enable_and_ungate_cpu();
35
36 /* Repair ram on cluster0 and cluster1 after CPU is powered on. */
37 ram_repair();
38
39 clock_cpu0_remove_reset();
40
41 clock_halt_avp();
42}
43
Gabe Black7f074752013-09-29 06:32:27 -070044void main(void)
Gabe Black396b0722013-09-26 16:22:09 -070045{
Ken Chang41359bd2014-04-21 17:54:28 +080046 // enable pinmux clamp inputs
47 clamp_tristate_inputs();
48
Jimmy Zhangbf04eda2014-02-11 17:21:20 -080049 // enable JTAG at the earliest stage
50 enable_jtag();
51
Gabe Blackd40be112013-10-09 23:45:07 -070052 clock_early_uart();
Gabe Blackca436cb2013-09-29 07:06:08 -070053
Gabe Black58f30622013-10-04 06:17:22 -070054 // Serial out, tristate off.
55 pinmux_set_config(PINMUX_KB_ROW9_INDEX, PINMUX_KB_ROW9_FUNC_UA3);
56 // Serial in, tristate_on.
57 pinmux_set_config(PINMUX_KB_ROW10_INDEX, PINMUX_KB_ROW10_FUNC_UA3 |
Julius Werneredf6b572013-10-25 17:49:26 -070058 PINMUX_PULL_UP |
Gabe Black58f30622013-10-04 06:17:22 -070059 PINMUX_INPUT_ENABLE);
Julius Werneredf6b572013-10-25 17:49:26 -070060 // Mux some pins away from uart A.
61 pinmux_set_config(PINMUX_UART2_CTS_N_INDEX,
62 PINMUX_UART2_CTS_N_FUNC_UB3 |
Julius Werneredf6b572013-10-25 17:49:26 -070063 PINMUX_INPUT_ENABLE);
64 pinmux_set_config(PINMUX_UART2_RTS_N_INDEX,
65 PINMUX_UART2_RTS_N_FUNC_UB3);
Gabe Black58f30622013-10-04 06:17:22 -070066
Julius Werner85620db2013-11-13 18:22:15 -080067 if (CONFIG_BOOTBLOCK_CONSOLE) {
Gabe Black7f074752013-09-29 06:32:27 -070068 console_init();
Julius Werner85620db2013-11-13 18:22:15 -080069 exception_init();
70 }
Gabe Black7f074752013-09-29 06:32:27 -070071
Gabe Blackd40be112013-10-09 23:45:07 -070072 clock_init();
73
74 bootblock_mainboard_init();
75
76 pinmux_set_config(PINMUX_CORE_PWR_REQ_INDEX,
77 PINMUX_CORE_PWR_REQ_FUNC_PWRON);
78 pinmux_set_config(PINMUX_CPU_PWR_REQ_INDEX,
79 PINMUX_CPU_PWR_REQ_FUNC_CPU);
80 pinmux_set_config(PINMUX_PWR_INT_N_INDEX,
81 PINMUX_PWR_INT_N_FUNC_PMICINTR |
Gabe Blackd40be112013-10-09 23:45:07 -070082 PINMUX_INPUT_ENABLE);
83
Aaron Durbin825a5a82015-03-20 16:42:17 -050084 run_romstage();
85}
Gabe Black7f074752013-09-29 06:32:27 -070086
Aaron Durbin825a5a82015-03-20 16:42:17 -050087void platform_prog_run(struct prog *prog)
88{
89 run_next_stage(prog_entry(prog));
Gabe Black396b0722013-09-26 16:22:09 -070090}