blob: 527a79593bc602713c5587193996c90f60ea5fc3 [file] [log] [blame]
Biao Huang9d48e172015-07-31 17:10:56 +08001/*
2 * This file is part of the coreboot project.
3 *
4 * Copyright 2015 MediaTek Inc.
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; version 2 of the License.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 *
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
18 */
19#include <arch/io.h>
20#include <console/console.h>
21#include <soc/gpio.h>
22#include <soc/mipi.h>
23
24/*
25 * GPIO 47-56 are controlled by MIPI register by default.
26 * When they are used as GPI, we have to set IES of MIPI register to 1.
27 * Additionally, pulls of these pins are controlled by MIPI,
28 * and pull-setting of these pins are forbidden in our driver.
29 */
30static void set_gpi_from_mipi(void)
31{
32 setbits_le32(&mt8173_mipi->mipi_rx_ana4c,
33 1 << 0 | /* RG_MIPI_GPI0_IES GPI47 */
34 1 << 6 | /* RG_MIPI_GPI1_IES GPI48 */
35 1 << 12 | /* RG_MIPI_GPI2_IES GPI49 */
36 1 << 18 | /* RG_MIPI_GPI3_IES GPI50 */
37 1 << 24); /* RF_MIPI_GPI4_IES GPI51 */
38
39 setbits_le32(&mt8173_mipi->mipi_rx_ana50,
40 1 << 0 | /* RG_MIPI_GPI5_IES GPI52 */
41 1 << 6 | /* RG_MIPI_GPI6_IES GPI53 */
42 1 << 12 | /* RG_MIPI_GPI7_IES GPI54 */
43 1 << 18 | /* RG_MIPI_GPI8_IES GPI55 */
44 1 << 24); /* RF_MIPI_GPI9_IES GPI56 */
45}
46
47/*
48 * overwrite the T/RDSEL default value of exmd_ctrl and
49 * msdc2_ctrl5 as b'1010
50 */
51static void gpio_set_duty(enum external_power ext_power)
52{
53 /* EXMD control reg */
54 if (ext_power == GPIO_EINT_1P8V) {
55 /* exmd_ctrl[9:4] = b`000000, [3:0] = b`1010 */
56 write16(&mt8173_gpio->exmd_ctrl[0].rst, 0x3F5);
57 write16(&mt8173_gpio->exmd_ctrl[0].set, 0xA);
58 } else if (ext_power == GPIO_EINT_3P3V) {
59 /* exmd_ctrl[9:4] = b`001100, [3:0] = b`1010 */
60 write16(&mt8173_gpio->exmd_ctrl[0].rst, 0x335);
61 write16(&mt8173_gpio->exmd_ctrl[0].set, 0xCA);
62 }
63
64 /* other R/TDSEL */
65 /* msdc2_ctrl5 , bit[3:0] = b`1010 */
66 write16(&mt8173_gpio->msdc2_ctrl5.set, 0xA);
67 write16(&mt8173_gpio->msdc2_ctrl5.rst, 0x5);
68}
69
70void gpio_init(enum external_power ext_power)
71{
72 set_gpi_from_mipi();
73 gpio_set_duty(ext_power);
74}