Aaron Durbin | e33a172 | 2015-07-30 16:52:56 -0500 | [diff] [blame] | 1 | /* |
| 2 | * This file is part of the coreboot project. |
| 3 | * |
| 4 | * Copyright 2015 Google Inc. |
| 5 | * |
| 6 | * This program is free software; you can redistribute it and/or modify |
| 7 | * it under the terms of the GNU General Public License as published by |
| 8 | * the Free Software Foundation; version 2 of the License. |
| 9 | * |
| 10 | * This program is distributed in the hope that it will be useful, |
| 11 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 12 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 13 | * GNU General Public License for more details. |
Aaron Durbin | e33a172 | 2015-07-30 16:52:56 -0500 | [diff] [blame] | 14 | */ |
| 15 | |
| 16 | #include <stddef.h> |
| 17 | #include <console/uart.h> |
| 18 | #include <soc/iomap.h> |
| 19 | #include <soc/serialio.h> |
| 20 | |
| 21 | unsigned int uart_platform_refclk(void) |
| 22 | { |
| 23 | /* |
| 24 | * Set M and N divisor inputs and enable clock. |
| 25 | * Main reference frequency to UART is: |
| 26 | * 120MHz * M / N = 120MHz * 48 / 3125 = 1843200Hz |
| 27 | * The different order below is to handle integer math overflow. |
| 28 | */ |
| 29 | return 120 * MHz / SIO_REG_PPR_CLOCK_N_DIV * SIO_REG_PPR_CLOCK_M_DIV; |
| 30 | } |
| 31 | |
| 32 | uintptr_t uart_platform_base(int idx) |
| 33 | { |
| 34 | /* Same base address for all debug port usage. In reality UART2 |
| 35 | * is currently only supported. */ |
| 36 | return UART_DEBUG_BASE_ADDRESS; |
| 37 | } |