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Lee Leahyb0005132015-05-12 18:19:47 -07001/*
2 * This file is part of the coreboot project.
3 *
4 * Copyright (C) 2014 Google Inc.
Lee Leahy1d14b3e2015-05-12 18:23:27 -07005 * Copyright (C) 2015 Intel Corporation.
Lee Leahyb0005132015-05-12 18:19:47 -07006 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; version 2 of the License.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
Lee Leahyb0005132015-05-12 18:19:47 -070015 */
16
Lee Leahyb0005132015-05-12 18:19:47 -070017#include <soc/ramstage.h>
Lee Leahyb0005132015-05-12 18:19:47 -070018
Lee Leahy1d14b3e2015-05-12 18:23:27 -070019void soc_init_pre_device(void *chip_info)
Lee Leahyb0005132015-05-12 18:19:47 -070020{
Lee Leahy1d14b3e2015-05-12 18:23:27 -070021 /* Perform silicon specific init. */
22 intel_silicon_init();
Lee Leahyb0005132015-05-12 18:19:47 -070023}