Lee Leahy | b000513 | 2015-05-12 18:19:47 -0700 | [diff] [blame] | 1 | /* |
| 2 | * This file is part of the coreboot project. |
| 3 | * |
| 4 | * Copyright (C) 2014 Google Inc. |
Lee Leahy | 1d14b3e | 2015-05-12 18:23:27 -0700 | [diff] [blame] | 5 | * Copyright (C) 2015 Intel Corporation. |
Lee Leahy | b000513 | 2015-05-12 18:19:47 -0700 | [diff] [blame] | 6 | * |
| 7 | * This program is free software; you can redistribute it and/or modify |
| 8 | * it under the terms of the GNU General Public License as published by |
| 9 | * the Free Software Foundation; version 2 of the License. |
| 10 | * |
| 11 | * This program is distributed in the hope that it will be useful, |
| 12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 14 | * GNU General Public License for more details. |
Lee Leahy | b000513 | 2015-05-12 18:19:47 -0700 | [diff] [blame] | 15 | */ |
| 16 | |
| 17 | #include <arch/io.h> |
| 18 | #include <bootstate.h> |
| 19 | #include <console/console.h> |
| 20 | #include <console/post_codes.h> |
| 21 | #include <cpu/x86/smm.h> |
| 22 | #include <reg_script.h> |
| 23 | #include <spi-generic.h> |
| 24 | #include <stdlib.h> |
| 25 | #include <soc/pci_devs.h> |
Lee Leahy | 1d14b3e | 2015-05-12 18:23:27 -0700 | [diff] [blame] | 26 | #include <soc/pcr.h> |
| 27 | #include <soc/pm.h> |
| 28 | #include <soc/pmc.h> |
Lee Leahy | b000513 | 2015-05-12 18:19:47 -0700 | [diff] [blame] | 29 | #include <soc/spi.h> |
| 30 | #include <soc/systemagent.h> |
Lee Leahy | 1d14b3e | 2015-05-12 18:23:27 -0700 | [diff] [blame] | 31 | #include <device/pci.h> |
Lee Leahy | b000513 | 2015-05-12 18:19:47 -0700 | [diff] [blame] | 32 | |
Lee Leahy | 1d14b3e | 2015-05-12 18:23:27 -0700 | [diff] [blame] | 33 | static void pch_finalize_script(void) |
| 34 | { |
| 35 | device_t dev; |
| 36 | uint32_t reg32, hsfs; |
| 37 | void *spibar = get_spi_bar(); |
| 38 | u8 reg8; |
| 39 | u16 tcobase; |
| 40 | u16 tcocnt; |
| 41 | uint8_t *pmcbase; |
| 42 | u32 pmsyncreg; |
Lee Leahy | b000513 | 2015-05-12 18:19:47 -0700 | [diff] [blame] | 43 | |
Lee Leahy | b000513 | 2015-05-12 18:19:47 -0700 | [diff] [blame] | 44 | /* Set SPI opcode menu */ |
Lee Leahy | 1d14b3e | 2015-05-12 18:23:27 -0700 | [diff] [blame] | 45 | write16(spibar + SPIBAR_PREOP, SPI_OPPREFIX); |
| 46 | write16(spibar + SPIBAR_OPTYPE, SPI_OPTYPE); |
| 47 | write32(spibar + SPIBAR_OPMENU_LOWER, SPI_OPMENU_LOWER); |
| 48 | write32(spibar + SPIBAR_OPMENU_UPPER, SPI_OPMENU_UPPER); |
Lee Leahy | b000513 | 2015-05-12 18:19:47 -0700 | [diff] [blame] | 49 | /* Lock SPIBAR */ |
Lee Leahy | 1d14b3e | 2015-05-12 18:23:27 -0700 | [diff] [blame] | 50 | hsfs = read32(spibar + SPIBAR_HSFS); |
| 51 | hsfs |= SPIBAR_HSFS_FLOCKDN; |
| 52 | write32(spibar + SPIBAR_HSFS, hsfs); |
Lee Leahy | b000513 | 2015-05-12 18:19:47 -0700 | [diff] [blame] | 53 | |
Lee Leahy | 1d14b3e | 2015-05-12 18:23:27 -0700 | [diff] [blame] | 54 | /*TCO Lock down*/ |
| 55 | tcobase = pmc_tco_regs(); |
| 56 | tcocnt = inw(tcobase + TCO1_CNT); |
| 57 | tcocnt |= TCO_LOCK; |
| 58 | outw(tcocnt, tcobase + TCO1_CNT); |
Lee Leahy | b000513 | 2015-05-12 18:19:47 -0700 | [diff] [blame] | 59 | |
| 60 | /* Global SMI Lock */ |
Lee Leahy | 1d14b3e | 2015-05-12 18:23:27 -0700 | [diff] [blame] | 61 | dev = PCH_DEV_PMC; |
| 62 | reg8 = pci_read_config8(dev, GEN_PMCON_A); |
| 63 | reg8 |= SMI_LOCK; |
| 64 | pci_write_config8(dev, GEN_PMCON_A, reg8); |
Lee Leahy | b000513 | 2015-05-12 18:19:47 -0700 | [diff] [blame] | 65 | |
Lee Leahy | 1d14b3e | 2015-05-12 18:23:27 -0700 | [diff] [blame] | 66 | /* Lock down ABASE and sleep stretching policy */ |
| 67 | reg32 = pci_read_config32(dev, GEN_PMCON_B); |
| 68 | reg32 |= (SLP_STR_POL_LOCK | ACPI_BASE_LOCK); |
| 69 | pci_write_config32(dev, GEN_PMCON_B, reg32); |
Lee Leahy | b000513 | 2015-05-12 18:19:47 -0700 | [diff] [blame] | 70 | |
| 71 | /* PMSYNC */ |
Lee Leahy | 1d14b3e | 2015-05-12 18:23:27 -0700 | [diff] [blame] | 72 | pmcbase = pmc_mmio_regs(); |
| 73 | pmsyncreg = read32(pmcbase + PMSYNC_TPR_CFG); |
| 74 | pmsyncreg |= PMSYNC_LOCK; |
| 75 | write32(pmcbase + PMSYNC_TPR_CFG, pmsyncreg); |
| 76 | } |
Lee Leahy | b000513 | 2015-05-12 18:19:47 -0700 | [diff] [blame] | 77 | |
Lee Leahy | 1d14b3e | 2015-05-12 18:23:27 -0700 | [diff] [blame] | 78 | static void soc_finalize(void *unused) |
Lee Leahy | b000513 | 2015-05-12 18:19:47 -0700 | [diff] [blame] | 79 | { |
| 80 | printk(BIOS_DEBUG, "Finalizing chipset.\n"); |
Lee Leahy | 1d14b3e | 2015-05-12 18:23:27 -0700 | [diff] [blame] | 81 | pch_finalize_script(); |
Lee Leahy | b000513 | 2015-05-12 18:19:47 -0700 | [diff] [blame] | 82 | |
| 83 | /* Indicate finalize step with post code */ |
| 84 | post_code(POST_OS_BOOT); |
| 85 | } |
| 86 | |
Lee Leahy | 1d14b3e | 2015-05-12 18:23:27 -0700 | [diff] [blame] | 87 | BOOT_STATE_INIT_ENTRY(BS_OS_RESUME, BS_ON_ENTRY, soc_finalize, NULL); |
| 88 | BOOT_STATE_INIT_ENTRY(BS_PAYLOAD_LOAD, BS_ON_EXIT, soc_finalize, NULL); |