Martin Roth | 433659a | 2014-05-12 21:55:00 -0600 | [diff] [blame] | 1 | /* |
| 2 | * This file is part of the coreboot project. |
| 3 | * |
| 4 | * Copyright (C) 2009 coresystems GmbH |
| 5 | * Copyright (C) 2011 The Chromium OS Authors. All rights reserved. |
| 6 | * Copyright (C) 2013-2014 Sage Electronic Engineering, LLC. |
| 7 | * |
| 8 | * This program is free software; you can redistribute it and/or |
| 9 | * modify it under the terms of the GNU General Public License as |
| 10 | * published by the Free Software Foundation; version 2 of |
| 11 | * the License. |
| 12 | * |
| 13 | * This program is distributed in the hope that it will be useful, |
| 14 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 15 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 16 | * GNU General Public License for more details. |
Martin Roth | 433659a | 2014-05-12 21:55:00 -0600 | [diff] [blame] | 17 | */ |
| 18 | |
| 19 | #include <types.h> |
| 20 | #include <console/console.h> |
| 21 | #include <arch/acpi.h> |
| 22 | #include <arch/acpigen.h> |
| 23 | #include <arch/cpu.h> |
| 24 | #include <cpu/x86/msr.h> |
Martin Roth | bd88fa0 | 2015-11-26 17:46:45 -0700 | [diff] [blame] | 25 | #include <cpu/x86/smm.h> |
Martin Roth | 433659a | 2014-05-12 21:55:00 -0600 | [diff] [blame] | 26 | #include <cpu/intel/speedstep.h> |
| 27 | #include <cpu/intel/turbo.h> |
| 28 | #include <arch/smp/mpspec.h> |
| 29 | #include <device/device.h> |
| 30 | #include <device/pci.h> |
Ben Gardner | fa6014a | 2015-12-08 21:20:25 -0600 | [diff] [blame] | 31 | #include <soc/baytrail.h> |
Martin Roth | 433659a | 2014-05-12 21:55:00 -0600 | [diff] [blame] | 32 | #include <device/pci_ids.h> |
Ben Gardner | fa6014a | 2015-12-08 21:20:25 -0600 | [diff] [blame] | 33 | #include <soc/pci_devs.h> |
| 34 | #include <soc/acpi.h> |
Martin Roth | 433659a | 2014-05-12 21:55:00 -0600 | [diff] [blame] | 35 | #include <string.h> |
Ben Gardner | fa6014a | 2015-12-08 21:20:25 -0600 | [diff] [blame] | 36 | #include <soc/iomap.h> |
| 37 | #include <soc/lpc.h> |
| 38 | #include <soc/pci_devs.h> |
| 39 | #include <soc/pmc.h> |
| 40 | #include <soc/irq.h> |
| 41 | #include <soc/iosf.h> |
Martin Roth | 433659a | 2014-05-12 21:55:00 -0600 | [diff] [blame] | 42 | #include <arch/io.h> |
Ben Gardner | fa6014a | 2015-12-08 21:20:25 -0600 | [diff] [blame] | 43 | #include <soc/msr.h> |
| 44 | #include <soc/pattrs.h> |
| 45 | #include <soc/pmc.h> |
Vladimir Serbinenko | 7fb149d | 2014-10-08 22:56:27 +0200 | [diff] [blame] | 46 | #include <cpu/cpu.h> |
Martin Roth | 433659a | 2014-05-12 21:55:00 -0600 | [diff] [blame] | 47 | #include <cbmem.h> |
| 48 | |
| 49 | #include "chip.h" |
| 50 | |
| 51 | #define MWAIT_RES(state, sub_state) \ |
| 52 | { \ |
| 53 | .addrl = (((state) << 4) | (sub_state)), \ |
| 54 | .space_id = ACPI_ADDRESS_SPACE_FIXED, \ |
| 55 | .bit_width = ACPI_FFIXEDHW_VENDOR_INTEL, \ |
| 56 | .bit_offset = ACPI_FFIXEDHW_CLASS_MWAIT, \ |
| 57 | .access_size = ACPI_FFIXEDHW_FLAG_HW_COORD, \ |
| 58 | } |
| 59 | |
| 60 | /* C-state map without S0ix */ |
| 61 | static acpi_cstate_t cstate_map[] = { |
| 62 | { |
| 63 | /* C1 */ |
| 64 | .ctype = 1, /* ACPI C1 */ |
| 65 | .latency = 1, |
| 66 | .power = 1000, |
| 67 | .resource = MWAIT_RES(0, 0), |
| 68 | }, |
| 69 | { |
| 70 | /* C6NS with no L2 shrink */ |
| 71 | /* NOTE: this substate is above CPUID limit */ |
| 72 | .ctype = 2, /* ACPI C2 */ |
| 73 | .latency = 500, |
| 74 | .power = 10, |
| 75 | .resource = MWAIT_RES(5, 1), |
| 76 | }, |
| 77 | { |
| 78 | /* C6FS with full L2 shrink */ |
| 79 | .ctype = 3, /* ACPI C3 */ |
| 80 | .latency = 1500, /* 1.5ms worst case */ |
| 81 | .power = 10, |
| 82 | .resource = MWAIT_RES(5, 2), |
| 83 | } |
| 84 | }; |
| 85 | |
| 86 | void acpi_init_gnvs(global_nvs_t *gnvs) |
| 87 | { |
Scott Radcliffe | 375e6ce | 2014-10-10 16:26:05 -0400 | [diff] [blame] | 88 | /* Clear gnvs area so uninitialized portions are defined */ |
| 89 | memset(gnvs, 0, sizeof(*gnvs)); |
| 90 | |
Martin Roth | 433659a | 2014-05-12 21:55:00 -0600 | [diff] [blame] | 91 | /* CPU core count */ |
| 92 | gnvs->pcnt = dev_count_cpu(); |
| 93 | |
| 94 | /* Top of Low Memory (start of resource allocation) */ |
| 95 | gnvs->tolm = nc_read_top_of_low_memory(); |
| 96 | |
| 97 | #if IS_ENABLED(CONFIG_CONSOLE_CBMEM) |
| 98 | /* Update the mem console pointer. */ |
| 99 | gnvs->cbmc = (u32)cbmem_find(CBMEM_ID_CONSOLE); |
| 100 | #endif |
| 101 | } |
| 102 | |
| 103 | static int acpi_sci_irq(void) |
| 104 | { |
Kevin Paul Herbert | bde6d30 | 2014-12-24 18:43:20 -0800 | [diff] [blame] | 105 | u32 *actl = (u32 *)(ILB_BASE_ADDRESS + ACTL); |
Martin Roth | 433659a | 2014-05-12 21:55:00 -0600 | [diff] [blame] | 106 | int scis; |
| 107 | static int sci_irq; |
| 108 | |
| 109 | if (sci_irq) |
| 110 | return sci_irq; |
| 111 | |
| 112 | /* Determine how SCI is routed. */ |
| 113 | scis = read32(actl) & SCIS_MASK; |
| 114 | switch (scis) { |
| 115 | case SCIS_IRQ9: |
| 116 | case SCIS_IRQ10: |
| 117 | case SCIS_IRQ11: |
| 118 | sci_irq = scis - SCIS_IRQ9 + 9; |
| 119 | break; |
| 120 | case SCIS_IRQ20: |
| 121 | case SCIS_IRQ21: |
| 122 | case SCIS_IRQ22: |
| 123 | case SCIS_IRQ23: |
| 124 | sci_irq = scis - SCIS_IRQ20 + 20; |
| 125 | break; |
| 126 | default: |
| 127 | printk(BIOS_DEBUG, "Invalid SCI route! Defaulting to IRQ9.\n"); |
| 128 | sci_irq = 9; |
| 129 | break; |
| 130 | } |
| 131 | |
| 132 | printk(BIOS_DEBUG, "SCI is IRQ%d\n", sci_irq); |
| 133 | return sci_irq; |
| 134 | } |
| 135 | |
| 136 | void acpi_create_intel_hpet(acpi_hpet_t * hpet) |
| 137 | { |
| 138 | acpi_header_t *header = &(hpet->header); |
| 139 | acpi_addr_t *addr = &(hpet->addr); |
| 140 | |
| 141 | memset((void *) hpet, 0, sizeof(acpi_hpet_t)); |
| 142 | |
| 143 | /* fill out header fields */ |
| 144 | memcpy(header->signature, "HPET", 4); |
| 145 | memcpy(header->oem_id, OEM_ID, 6); |
| 146 | memcpy(header->oem_table_id, ACPI_TABLE_CREATOR, 8); |
| 147 | memcpy(header->asl_compiler_id, ASLC, 4); |
| 148 | |
| 149 | header->length = sizeof(acpi_hpet_t); |
| 150 | header->revision = 1; |
| 151 | |
| 152 | /* fill out HPET address */ |
| 153 | addr->space_id = 0; /* Memory */ |
| 154 | addr->bit_width = 64; |
| 155 | addr->bit_offset = 0; |
| 156 | addr->addrl = (unsigned long long)HPET_BASE_ADDRESS & 0xffffffff; |
| 157 | addr->addrh = (unsigned long long)HPET_BASE_ADDRESS >> 32; |
| 158 | |
| 159 | hpet->id = 0x8086a201; /* Intel */ |
| 160 | hpet->number = 0x00; |
| 161 | hpet->min_tick = 0x0080; |
| 162 | |
| 163 | header->checksum = |
| 164 | acpi_checksum((void *) hpet, sizeof(acpi_hpet_t)); |
| 165 | } |
| 166 | |
| 167 | unsigned long acpi_fill_mcfg(unsigned long current) |
| 168 | { |
| 169 | current += acpi_create_mcfg_mmconfig((acpi_mcfg_mmconfig_t *)current, |
| 170 | MCFG_BASE_ADDRESS, 0, 0, 255); |
| 171 | return current; |
| 172 | } |
| 173 | |
| 174 | /** |
| 175 | * Fill in the fadt with generic values that can be overridden later. |
| 176 | */ |
| 177 | |
| 178 | typedef struct soc_intel_fsp_baytrail_config config_t; |
| 179 | |
| 180 | void acpi_fill_in_fadt(acpi_fadt_t * fadt, acpi_facs_t * facs, void *dsdt) |
| 181 | { |
| 182 | acpi_header_t *header = &(fadt->header); |
| 183 | struct device *lpcdev = dev_find_slot(FADT_SOC_LPC_DEV); |
| 184 | u16 pmbase = pci_read_config16(lpcdev, ABASE) & 0xfff0; |
| 185 | config_t *config = lpcdev->chip_info; |
| 186 | |
| 187 | memset((void *) fadt, 0, sizeof(acpi_fadt_t)); |
| 188 | |
| 189 | /* |
| 190 | * Reference section 5.2.9 Fixed ACPI Description Table (FADT) |
| 191 | * in the ACPI 3.0b specification. |
| 192 | */ |
| 193 | |
| 194 | /* FADT Header Structure */ |
| 195 | memcpy(header->signature, "FACP", 4); |
| 196 | header->length = sizeof(acpi_fadt_t); |
| 197 | header->revision = ACPI_FADT_REV_ACPI_3_0; |
| 198 | memcpy(header->oem_id, OEM_ID, 6); |
| 199 | memcpy(header->oem_table_id, ACPI_TABLE_CREATOR, 8); |
| 200 | memcpy(header->asl_compiler_id, ASLC, 4); |
| 201 | header->asl_compiler_revision = 1; |
| 202 | |
| 203 | /* ACPI Pointers */ |
| 204 | fadt->firmware_ctrl = (unsigned long) facs; |
| 205 | fadt->dsdt = (unsigned long) dsdt; |
| 206 | |
| 207 | fadt->model = 0; /* reserved, should be 0 ACPI 3.0 */ |
| 208 | fadt->preferred_pm_profile = config->fadt_pm_profile; /* unknown is default */ |
| 209 | |
| 210 | /* System Management */ |
| 211 | fadt->sci_int = acpi_sci_irq(); |
Martin Roth | bd88fa0 | 2015-11-26 17:46:45 -0700 | [diff] [blame] | 212 | |
Martin Roth | 433659a | 2014-05-12 21:55:00 -0600 | [diff] [blame] | 213 | fadt->smi_cmd = APM_CNT; |
| 214 | fadt->acpi_enable = APM_CNT_ACPI_ENABLE; |
| 215 | fadt->acpi_disable = APM_CNT_ACPI_DISABLE; |
Martin Roth | 433659a | 2014-05-12 21:55:00 -0600 | [diff] [blame] | 216 | |
| 217 | /* Power Control */ |
| 218 | fadt->s4bios_req = 0x00; |
| 219 | fadt->pstate_cnt = 0x00; |
| 220 | |
| 221 | /* Control Registers - Base Address */ |
| 222 | fadt->pm1a_evt_blk = pmbase + PM1_STS; |
| 223 | fadt->pm1b_evt_blk = 0x00; /* Not Used */ |
| 224 | fadt->pm1a_cnt_blk = pmbase + PM1_CNT; |
| 225 | fadt->pm1b_cnt_blk = 0x00; /* Not Used */ |
| 226 | fadt->pm2_cnt_blk = pmbase + PM2A_CNT_BLK; |
| 227 | fadt->pm_tmr_blk = pmbase + PM1_TMR; |
| 228 | fadt->gpe0_blk = pmbase + GPE0_STS; |
| 229 | fadt->gpe1_blk = 0x00; /* Not Used */ |
| 230 | |
| 231 | /* Control Registers - Length */ |
| 232 | fadt->pm1_evt_len = 4; /* 32 bits */ |
| 233 | fadt->pm1_cnt_len = 2; /* 32 bit register, 16 bits used */ |
| 234 | fadt->pm2_cnt_len = 1; /* 8 bits */ |
| 235 | fadt->pm_tmr_len = 4; /* 32 bits */ |
| 236 | fadt->gpe0_blk_len = 8; /* 64 bits */ |
| 237 | fadt->gpe1_blk_len = 0; |
| 238 | fadt->gpe1_base = 0; |
| 239 | fadt->cst_cnt = 0; |
| 240 | fadt->p_lvl2_lat = ACPI_FADT_C2_NOT_SUPPORTED; |
| 241 | fadt->p_lvl3_lat = ACPI_FADT_C3_NOT_SUPPORTED; |
| 242 | fadt->flush_size = 0; /* set to 0 if WBINVD is 1 in flags */ |
| 243 | fadt->flush_stride = 0; /* set to 0 if WBINVD is 1 in flags */ |
| 244 | fadt->duty_offset = 1; |
| 245 | fadt->duty_width = 0; |
| 246 | |
| 247 | /* RTC Registers */ |
| 248 | fadt->day_alrm = 0x0D; |
| 249 | fadt->mon_alrm = 0x00; |
| 250 | fadt->century = 0x00; |
| 251 | fadt->iapc_boot_arch = config->fadt_boot_arch; /* legacy free default */ |
| 252 | |
| 253 | fadt->flags = ACPI_FADT_WBINVD | ACPI_FADT_C1_SUPPORTED | |
| 254 | ACPI_FADT_C2_MP_SUPPORTED | ACPI_FADT_SLEEP_BUTTON | |
| 255 | ACPI_FADT_RESET_REGISTER | ACPI_FADT_SLEEP_TYPE | |
| 256 | ACPI_FADT_S4_RTC_WAKE | ACPI_FADT_PLATFORM_CLOCK; |
| 257 | |
| 258 | /* Reset Register */ |
| 259 | fadt->reset_reg.space_id = ACPI_ADDRESS_SPACE_IO; |
| 260 | fadt->reset_reg.bit_width = 8; |
| 261 | fadt->reset_reg.bit_offset = 0; |
| 262 | fadt->reset_reg.access_size = ACPI_ACCESS_SIZE_BYTE_ACCESS; |
| 263 | fadt->reset_reg.addrl = 0xCF9; |
| 264 | fadt->reset_reg.addrh = 0x00; |
| 265 | fadt->reset_value = 6; |
| 266 | |
| 267 | /* Reserved Bits */ |
| 268 | fadt->res3 = 0x00; /* reserved, MUST be 0 ACPI 3.0 */ |
| 269 | fadt->res4 = 0x00; /* reserved, MUST be 0 ACPI 3.0 */ |
| 270 | fadt->res5 = 0x00; /* reserved, MUST be 0 ACPI 3.0 */ |
| 271 | |
| 272 | /* Extended ACPI Pointers */ |
| 273 | fadt->x_firmware_ctl_l = (unsigned long)facs; |
| 274 | fadt->x_firmware_ctl_h = 0x00; |
| 275 | fadt->x_dsdt_l = (unsigned long)dsdt; |
| 276 | fadt->x_dsdt_h = 0x00; |
| 277 | |
| 278 | /* PM1 Status & PM1 Enable */ |
| 279 | fadt->x_pm1a_evt_blk.space_id = ACPI_ADDRESS_SPACE_IO; |
| 280 | fadt->x_pm1a_evt_blk.bit_width = 32; |
| 281 | fadt->x_pm1a_evt_blk.bit_offset = 0; |
| 282 | fadt->x_pm1a_evt_blk.access_size = ACPI_ACCESS_SIZE_DWORD_ACCESS; |
| 283 | fadt->x_pm1a_evt_blk.addrl = fadt->pm1a_evt_blk; |
| 284 | fadt->x_pm1a_evt_blk.addrh = 0x00; |
| 285 | |
| 286 | fadt->x_pm1b_evt_blk.space_id = ACPI_ADDRESS_SPACE_IO; |
| 287 | fadt->x_pm1b_evt_blk.bit_width = 0; |
| 288 | fadt->x_pm1b_evt_blk.bit_offset = 0; |
| 289 | fadt->x_pm1b_evt_blk.access_size = 0; |
| 290 | fadt->x_pm1b_evt_blk.addrl = fadt->pm1b_evt_blk; |
| 291 | fadt->x_pm1b_evt_blk.addrh = 0x00; |
| 292 | |
| 293 | /* PM1 Control Registers */ |
| 294 | fadt->x_pm1a_cnt_blk.space_id = ACPI_ADDRESS_SPACE_IO; |
| 295 | fadt->x_pm1a_cnt_blk.bit_width = 16; |
| 296 | fadt->x_pm1a_cnt_blk.bit_offset = 0; |
| 297 | fadt->x_pm1a_cnt_blk.access_size = ACPI_ACCESS_SIZE_WORD_ACCESS; |
| 298 | fadt->x_pm1a_cnt_blk.addrl = fadt->pm1a_cnt_blk; |
| 299 | fadt->x_pm1a_cnt_blk.addrh = 0x00; |
| 300 | |
| 301 | fadt->x_pm1b_cnt_blk.space_id = ACPI_ADDRESS_SPACE_IO; |
| 302 | fadt->x_pm1b_cnt_blk.bit_width = 0; |
| 303 | fadt->x_pm1b_cnt_blk.bit_offset = 0; |
| 304 | fadt->x_pm1b_cnt_blk.access_size = 0; |
| 305 | fadt->x_pm1b_cnt_blk.addrl = fadt->pm1b_cnt_blk; |
| 306 | fadt->x_pm1b_cnt_blk.addrh = 0x00; |
| 307 | |
| 308 | /* PM2 Control Registers */ |
| 309 | fadt->x_pm2_cnt_blk.space_id = ACPI_ADDRESS_SPACE_IO; |
| 310 | fadt->x_pm2_cnt_blk.bit_width = 8; |
| 311 | fadt->x_pm2_cnt_blk.bit_offset = 0; |
| 312 | fadt->x_pm2_cnt_blk.access_size = ACPI_ACCESS_SIZE_BYTE_ACCESS; |
| 313 | fadt->x_pm2_cnt_blk.addrl = fadt->pm2_cnt_blk; |
| 314 | fadt->x_pm2_cnt_blk.addrh = 0x00; |
| 315 | |
| 316 | /* PM1 Timer Register */ |
| 317 | fadt->x_pm_tmr_blk.space_id = ACPI_ADDRESS_SPACE_IO; |
| 318 | fadt->x_pm_tmr_blk.bit_width = 32; |
| 319 | fadt->x_pm_tmr_blk.bit_offset = 0; |
| 320 | fadt->x_pm_tmr_blk.access_size = ACPI_ACCESS_SIZE_DWORD_ACCESS; |
| 321 | fadt->x_pm_tmr_blk.addrl = fadt->pm_tmr_blk; |
| 322 | fadt->x_pm_tmr_blk.addrh = 0x00; |
| 323 | |
| 324 | /* General-Purpose Event Registers */ |
| 325 | fadt->x_gpe0_blk.space_id = ACPI_ADDRESS_SPACE_IO; |
| 326 | fadt->x_gpe0_blk.bit_width = 64; /* EventStatus + EventEnable */ |
| 327 | fadt->x_gpe0_blk.bit_offset = 0; |
| 328 | fadt->x_gpe0_blk.access_size = ACPI_ACCESS_SIZE_DWORD_ACCESS; |
| 329 | fadt->x_gpe0_blk.addrl = fadt->gpe0_blk; |
| 330 | fadt->x_gpe0_blk.addrh = 0x00; |
| 331 | |
| 332 | fadt->x_gpe1_blk.space_id = ACPI_ADDRESS_SPACE_IO; |
| 333 | fadt->x_gpe1_blk.bit_width = 0; |
| 334 | fadt->x_gpe1_blk.bit_offset = 0; |
| 335 | fadt->x_gpe1_blk.access_size = 0; |
| 336 | fadt->x_gpe1_blk.addrl = fadt->gpe1_blk; |
| 337 | fadt->x_gpe1_blk.addrh = 0x00; |
| 338 | |
| 339 | header->checksum = |
| 340 | acpi_checksum((void *) fadt, sizeof(acpi_fadt_t)); |
| 341 | } |
| 342 | static acpi_tstate_t baytrail_tss_table[] = { |
| 343 | { 100, 1000, 0, 0x00, 0 }, |
| 344 | { 88, 875, 0, 0x1e, 0 }, |
| 345 | { 75, 750, 0, 0x1c, 0 }, |
| 346 | { 63, 625, 0, 0x1a, 0 }, |
| 347 | { 50, 500, 0, 0x18, 0 }, |
| 348 | { 38, 375, 0, 0x16, 0 }, |
| 349 | { 25, 250, 0, 0x14, 0 }, |
| 350 | { 13, 125, 0, 0x12, 0 }, |
| 351 | }; |
| 352 | |
Vladimir Serbinenko | 9bb5c5c | 2014-11-09 03:51:32 +0100 | [diff] [blame] | 353 | static void generate_T_state_entries(int core, int cores_per_package) |
Martin Roth | 433659a | 2014-05-12 21:55:00 -0600 | [diff] [blame] | 354 | { |
Martin Roth | 433659a | 2014-05-12 21:55:00 -0600 | [diff] [blame] | 355 | /* Indicate SW_ALL coordination for T-states */ |
Vladimir Serbinenko | 9bb5c5c | 2014-11-09 03:51:32 +0100 | [diff] [blame] | 356 | acpigen_write_TSD_package(core, cores_per_package, SW_ALL); |
Martin Roth | 433659a | 2014-05-12 21:55:00 -0600 | [diff] [blame] | 357 | |
| 358 | /* Indicate FFixedHW so OS will use MSR */ |
Vladimir Serbinenko | 9bb5c5c | 2014-11-09 03:51:32 +0100 | [diff] [blame] | 359 | acpigen_write_empty_PTC(); |
Martin Roth | 433659a | 2014-05-12 21:55:00 -0600 | [diff] [blame] | 360 | |
| 361 | /* Set NVS controlled T-state limit */ |
Vladimir Serbinenko | 9bb5c5c | 2014-11-09 03:51:32 +0100 | [diff] [blame] | 362 | acpigen_write_TPC("\\TLVL"); |
Martin Roth | 433659a | 2014-05-12 21:55:00 -0600 | [diff] [blame] | 363 | |
| 364 | /* Write TSS table for MSR access */ |
Vladimir Serbinenko | 9bb5c5c | 2014-11-09 03:51:32 +0100 | [diff] [blame] | 365 | acpigen_write_TSS_package( |
Martin Roth | 433659a | 2014-05-12 21:55:00 -0600 | [diff] [blame] | 366 | ARRAY_SIZE(baytrail_tss_table), baytrail_tss_table); |
Martin Roth | 433659a | 2014-05-12 21:55:00 -0600 | [diff] [blame] | 367 | } |
| 368 | |
| 369 | static int calculate_power(int tdp, int p1_ratio, int ratio) |
| 370 | { |
| 371 | u32 m; |
| 372 | u32 power; |
| 373 | |
| 374 | /* |
| 375 | * M = ((1.1 - ((p1_ratio - ratio) * 0.00625)) / 1.1) ^ 2 |
| 376 | * |
| 377 | * Power = (ratio / p1_ratio) * m * tdp |
| 378 | */ |
| 379 | |
| 380 | m = (110000 - ((p1_ratio - ratio) * 625)) / 11; |
| 381 | m = (m * m) / 1000; |
| 382 | |
| 383 | power = ((ratio * 100000 / p1_ratio) / 100); |
| 384 | power *= (m / 100) * (tdp / 1000); |
| 385 | power /= 1000; |
| 386 | |
| 387 | return (int)power; |
| 388 | } |
| 389 | |
Vladimir Serbinenko | 7fb149d | 2014-10-08 22:56:27 +0200 | [diff] [blame] | 390 | static void generate_P_state_entries(int core, int cores_per_package) |
Martin Roth | 433659a | 2014-05-12 21:55:00 -0600 | [diff] [blame] | 391 | { |
Martin Roth | 433659a | 2014-05-12 21:55:00 -0600 | [diff] [blame] | 392 | int ratio_min, ratio_max, ratio_turbo, ratio_step, ratio_range_2; |
| 393 | int coord_type, power_max, power_unit, num_entries; |
| 394 | int ratio, power, clock, clock_max; |
| 395 | int vid, vid_turbo, vid_min, vid_max, vid_range_2; |
| 396 | u32 control_status; |
| 397 | const struct pattrs *pattrs = pattrs_get(); |
| 398 | msr_t msr; |
| 399 | |
| 400 | /* Inputs from CPU attributes */ |
| 401 | ratio_max = pattrs->iacore_ratios[IACORE_MAX]; |
| 402 | ratio_min = pattrs->iacore_ratios[IACORE_LFM]; |
| 403 | vid_max = pattrs->iacore_vids[IACORE_MAX]; |
| 404 | vid_min = pattrs->iacore_vids[IACORE_LFM]; |
| 405 | |
| 406 | /* Hardware coordination of P-states */ |
| 407 | coord_type = HW_ALL; |
| 408 | |
| 409 | /* Max Non-Turbo Frequency */ |
| 410 | clock_max = (ratio_max * pattrs->bclk_khz) / 1000; |
| 411 | |
| 412 | /* Calculate CPU TDP in mW */ |
| 413 | msr = rdmsr(MSR_PKG_POWER_SKU_UNIT); |
| 414 | power_unit = 1 << (msr.lo & 0xf); |
| 415 | msr = rdmsr(MSR_PKG_POWER_LIMIT); |
| 416 | power_max = ((msr.lo & 0x7fff) / power_unit) * 1000; |
| 417 | |
| 418 | /* Write _PCT indicating use of FFixedHW */ |
Vladimir Serbinenko | 7fb149d | 2014-10-08 22:56:27 +0200 | [diff] [blame] | 419 | acpigen_write_empty_PCT(); |
Martin Roth | 433659a | 2014-05-12 21:55:00 -0600 | [diff] [blame] | 420 | |
| 421 | /* Write _PPC with NVS specified limit on supported P-state */ |
Vladimir Serbinenko | 7fb149d | 2014-10-08 22:56:27 +0200 | [diff] [blame] | 422 | acpigen_write_PPC_NVS(); |
Martin Roth | 433659a | 2014-05-12 21:55:00 -0600 | [diff] [blame] | 423 | |
| 424 | /* Write PSD indicating configured coordination type */ |
Vladimir Serbinenko | 7fb149d | 2014-10-08 22:56:27 +0200 | [diff] [blame] | 425 | acpigen_write_PSD_package(core, 1, coord_type); |
Martin Roth | 433659a | 2014-05-12 21:55:00 -0600 | [diff] [blame] | 426 | |
| 427 | /* Add P-state entries in _PSS table */ |
Vladimir Serbinenko | 7fb149d | 2014-10-08 22:56:27 +0200 | [diff] [blame] | 428 | acpigen_write_name("_PSS"); |
Martin Roth | 433659a | 2014-05-12 21:55:00 -0600 | [diff] [blame] | 429 | |
| 430 | /* Determine ratio points */ |
| 431 | ratio_step = 1; |
| 432 | num_entries = (ratio_max - ratio_min) / ratio_step; |
| 433 | while (num_entries > 15) { /* ACPI max is 15 ratios */ |
| 434 | ratio_step <<= 1; |
| 435 | num_entries >>= 1; |
| 436 | } |
| 437 | |
| 438 | /* P[T] is Turbo state if enabled */ |
| 439 | if (get_turbo_state() == TURBO_ENABLED) { |
| 440 | /* _PSS package count including Turbo */ |
Vladimir Serbinenko | 7fb149d | 2014-10-08 22:56:27 +0200 | [diff] [blame] | 441 | acpigen_write_package(num_entries + 2); |
Martin Roth | 433659a | 2014-05-12 21:55:00 -0600 | [diff] [blame] | 442 | |
| 443 | ratio_turbo = pattrs->iacore_ratios[IACORE_TURBO]; |
| 444 | vid_turbo = pattrs->iacore_vids[IACORE_TURBO]; |
| 445 | control_status = (ratio_turbo << 8) | vid_turbo; |
| 446 | |
| 447 | /* Add entry for Turbo ratio */ |
Vladimir Serbinenko | 7fb149d | 2014-10-08 22:56:27 +0200 | [diff] [blame] | 448 | acpigen_write_PSS_package( |
Martin Roth | 433659a | 2014-05-12 21:55:00 -0600 | [diff] [blame] | 449 | clock_max + 1, /*MHz*/ |
| 450 | power_max, /*mW*/ |
| 451 | 10, /*lat1*/ |
| 452 | 10, /*lat2*/ |
| 453 | control_status, /*control*/ |
| 454 | control_status); /*status*/ |
| 455 | } else { |
| 456 | /* _PSS package count without Turbo */ |
Vladimir Serbinenko | 7fb149d | 2014-10-08 22:56:27 +0200 | [diff] [blame] | 457 | acpigen_write_package(num_entries + 1); |
Martin Roth | 433659a | 2014-05-12 21:55:00 -0600 | [diff] [blame] | 458 | ratio_turbo = ratio_max; |
| 459 | vid_turbo = vid_max; |
| 460 | } |
| 461 | |
| 462 | /* First regular entry is max non-turbo ratio */ |
| 463 | control_status = (ratio_max << 8) | vid_max; |
Vladimir Serbinenko | 7fb149d | 2014-10-08 22:56:27 +0200 | [diff] [blame] | 464 | acpigen_write_PSS_package( |
Martin Roth | 433659a | 2014-05-12 21:55:00 -0600 | [diff] [blame] | 465 | clock_max, /*MHz*/ |
| 466 | power_max, /*mW*/ |
| 467 | 10, /*lat1*/ |
| 468 | 10, /*lat2*/ |
| 469 | control_status, /*control */ |
| 470 | control_status); /*status*/ |
| 471 | |
| 472 | /* Set up ratio and vid ranges for VID calculation */ |
| 473 | ratio_range_2 = (ratio_turbo - ratio_min) * 2; |
| 474 | vid_range_2 = (vid_turbo - vid_min) * 2; |
| 475 | |
| 476 | /* Generate the remaining entries */ |
| 477 | for (ratio = ratio_min + ((num_entries - 1) * ratio_step); |
| 478 | ratio >= ratio_min; ratio -= ratio_step) { |
| 479 | |
| 480 | /* Calculate VID for this ratio */ |
| 481 | vid = ((ratio - ratio_min) * vid_range_2) / |
| 482 | ratio_range_2 + vid_min; |
| 483 | /* Round up if remainder */ |
| 484 | if (((ratio - ratio_min) * vid_range_2) % ratio_range_2) |
| 485 | vid++; |
| 486 | |
| 487 | /* Calculate power at this ratio */ |
| 488 | power = calculate_power(power_max, ratio_max, ratio); |
| 489 | clock = (ratio * pattrs->bclk_khz) / 1000; |
| 490 | control_status = (ratio << 8) | (vid & 0xff); |
| 491 | |
Vladimir Serbinenko | 7fb149d | 2014-10-08 22:56:27 +0200 | [diff] [blame] | 492 | acpigen_write_PSS_package( |
Martin Roth | 433659a | 2014-05-12 21:55:00 -0600 | [diff] [blame] | 493 | clock, /*MHz*/ |
| 494 | power, /*mW*/ |
| 495 | 10, /*lat1*/ |
| 496 | 10, /*lat2*/ |
| 497 | control_status, /*control*/ |
| 498 | control_status); /*status*/ |
| 499 | } |
| 500 | |
| 501 | /* Fix package length */ |
Vladimir Serbinenko | 7fb149d | 2014-10-08 22:56:27 +0200 | [diff] [blame] | 502 | acpigen_pop_len(); |
Martin Roth | 433659a | 2014-05-12 21:55:00 -0600 | [diff] [blame] | 503 | } |
| 504 | |
Alexander Couzens | 5eea458 | 2015-04-12 22:18:55 +0200 | [diff] [blame] | 505 | void generate_cpu_entries(device_t device) |
Martin Roth | 433659a | 2014-05-12 21:55:00 -0600 | [diff] [blame] | 506 | { |
Vladimir Serbinenko | 7fb149d | 2014-10-08 22:56:27 +0200 | [diff] [blame] | 507 | int core; |
Martin Roth | 433659a | 2014-05-12 21:55:00 -0600 | [diff] [blame] | 508 | int pcontrol_blk = get_pmbase(), plen = 6; |
| 509 | const struct pattrs *pattrs = pattrs_get(); |
| 510 | |
| 511 | for (core=0; core<pattrs->num_cpus; core++) { |
| 512 | if (core > 0) { |
| 513 | pcontrol_blk = 0; |
| 514 | plen = 0; |
| 515 | } |
| 516 | |
| 517 | /* Generate processor \_PR.CPUx */ |
Vladimir Serbinenko | 7fb149d | 2014-10-08 22:56:27 +0200 | [diff] [blame] | 518 | acpigen_write_processor( |
Martin Roth | 433659a | 2014-05-12 21:55:00 -0600 | [diff] [blame] | 519 | core, pcontrol_blk, plen); |
| 520 | |
| 521 | /* Generate P-state tables */ |
Vladimir Serbinenko | 7fb149d | 2014-10-08 22:56:27 +0200 | [diff] [blame] | 522 | generate_P_state_entries( |
Martin Roth | 433659a | 2014-05-12 21:55:00 -0600 | [diff] [blame] | 523 | core, pattrs->num_cpus); |
| 524 | |
| 525 | /* Generate C-state tables */ |
Vladimir Serbinenko | 7fb149d | 2014-10-08 22:56:27 +0200 | [diff] [blame] | 526 | acpigen_write_CST_package( |
Martin Roth | 433659a | 2014-05-12 21:55:00 -0600 | [diff] [blame] | 527 | cstate_map, ARRAY_SIZE(cstate_map)); |
| 528 | |
| 529 | /* Generate T-state tables */ |
Vladimir Serbinenko | 7fb149d | 2014-10-08 22:56:27 +0200 | [diff] [blame] | 530 | generate_T_state_entries( |
Martin Roth | 433659a | 2014-05-12 21:55:00 -0600 | [diff] [blame] | 531 | core, pattrs->num_cpus); |
| 532 | |
Vladimir Serbinenko | 7fb149d | 2014-10-08 22:56:27 +0200 | [diff] [blame] | 533 | acpigen_pop_len(); |
Martin Roth | 433659a | 2014-05-12 21:55:00 -0600 | [diff] [blame] | 534 | } |
| 535 | } |
| 536 | |
| 537 | unsigned long acpi_madt_irq_overrides(unsigned long current) |
| 538 | { |
| 539 | int sci_irq = acpi_sci_irq(); |
| 540 | acpi_madt_irqoverride_t *irqovr; |
| 541 | uint16_t sci_flags = MP_IRQ_TRIGGER_LEVEL; |
| 542 | |
| 543 | /* INT_SRC_OVR */ |
| 544 | irqovr = (void *)current; |
| 545 | current += acpi_create_madt_irqoverride(irqovr, 0, 0, 2, 0); |
| 546 | |
| 547 | if (sci_irq >= 20) |
| 548 | sci_flags |= MP_IRQ_POLARITY_LOW; |
| 549 | else |
| 550 | sci_flags |= MP_IRQ_POLARITY_HIGH; |
| 551 | |
| 552 | irqovr = (void *)current; |
| 553 | current += acpi_create_madt_irqoverride(irqovr, 0, sci_irq, sci_irq, |
| 554 | sci_flags); |
| 555 | |
| 556 | return current; |
| 557 | } |
Vladimir Serbinenko | 7fb149d | 2014-10-08 22:56:27 +0200 | [diff] [blame] | 558 | |
Alexander Couzens | 83fc32f | 2015-04-12 22:28:37 +0200 | [diff] [blame] | 559 | unsigned long southcluster_write_acpi_tables(device_t device, |
| 560 | unsigned long current, |
Vladimir Serbinenko | 7fb149d | 2014-10-08 22:56:27 +0200 | [diff] [blame] | 561 | struct acpi_rsdp *rsdp) |
| 562 | { |
| 563 | acpi_header_t *ssdt2; |
| 564 | |
Alexander Couzens | 83fc32f | 2015-04-12 22:28:37 +0200 | [diff] [blame] | 565 | current = acpi_write_hpet(device, current, rsdp); |
Aaron Durbin | 07a1b28 | 2015-12-10 17:07:38 -0600 | [diff] [blame] | 566 | current = acpi_align_current(current); |
Vladimir Serbinenko | 7fb149d | 2014-10-08 22:56:27 +0200 | [diff] [blame] | 567 | |
| 568 | ssdt2 = (acpi_header_t *)current; |
| 569 | memset(ssdt2, 0, sizeof(acpi_header_t)); |
| 570 | acpi_create_serialio_ssdt(ssdt2); |
| 571 | if (ssdt2->length) { |
| 572 | current += ssdt2->length; |
| 573 | acpi_add_table(rsdp, ssdt2); |
| 574 | printk(BIOS_DEBUG, "ACPI: * SSDT2 @ %p Length %x\n",ssdt2, |
| 575 | ssdt2->length); |
Aaron Durbin | 07a1b28 | 2015-12-10 17:07:38 -0600 | [diff] [blame] | 576 | current = acpi_align_current(current); |
Vladimir Serbinenko | 7fb149d | 2014-10-08 22:56:27 +0200 | [diff] [blame] | 577 | } else { |
| 578 | ssdt2 = NULL; |
| 579 | printk(BIOS_DEBUG, "ACPI: * SSDT2 not generated.\n"); |
| 580 | } |
| 581 | |
| 582 | printk(BIOS_DEBUG, "current = %lx\n", current); |
| 583 | |
| 584 | return current; |
| 585 | } |
| 586 | |
Alexander Couzens | a90dad1 | 2015-04-12 21:49:46 +0200 | [diff] [blame] | 587 | void southcluster_inject_dsdt(device_t device) |
Vladimir Serbinenko | 7fb149d | 2014-10-08 22:56:27 +0200 | [diff] [blame] | 588 | { |
| 589 | global_nvs_t *gnvs; |
| 590 | |
| 591 | gnvs = cbmem_find(CBMEM_ID_ACPI_GNVS); |
| 592 | if (!gnvs) { |
| 593 | gnvs = cbmem_add(CBMEM_ID_ACPI_GNVS, sizeof (*gnvs)); |
| 594 | if (gnvs) |
| 595 | memset(gnvs, 0, sizeof(*gnvs)); |
| 596 | } |
| 597 | |
| 598 | if (gnvs) { |
| 599 | acpi_create_gnvs(gnvs); |
| 600 | acpi_save_gnvs((unsigned long)gnvs); |
| 601 | /* And tell SMI about it */ |
| 602 | smm_setup_structures(gnvs, NULL, NULL); |
| 603 | |
| 604 | /* Add it to DSDT. */ |
| 605 | acpigen_write_scope("\\"); |
| 606 | acpigen_write_name_dword("NVSA", (u32) gnvs); |
| 607 | acpigen_pop_len(); |
| 608 | } |
| 609 | } |