Aaron Durbin | 9a7d7bc | 2013-09-07 00:41:48 -0500 | [diff] [blame] | 1 | /* |
| 2 | * This file is part of the coreboot project. |
| 3 | * |
Duncan Laurie | d8c4f2b | 2014-04-22 10:46:06 -0700 | [diff] [blame] | 4 | * Copyright (C) 2014 Google Inc. |
Aaron Durbin | 9a7d7bc | 2013-09-07 00:41:48 -0500 | [diff] [blame] | 5 | * |
| 6 | * This program is free software; you can redistribute it and/or modify |
| 7 | * it under the terms of the GNU General Public License as published by |
| 8 | * the Free Software Foundation; version 2 of the License. |
| 9 | * |
| 10 | * This program is distributed in the hope that it will be useful, |
| 11 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 12 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 13 | * GNU General Public License for more details. |
Aaron Durbin | 9a7d7bc | 2013-09-07 00:41:48 -0500 | [diff] [blame] | 14 | */ |
| 15 | |
| 16 | #include <stdint.h> |
| 17 | #include <stddef.h> |
| 18 | #include <console/console.h> |
| 19 | #include <string.h> |
| 20 | #include <spi-generic.h> |
| 21 | #include <spi_flash.h> |
Duncan Laurie | a32b6b9 | 2015-01-15 15:49:07 -0800 | [diff] [blame] | 22 | #include <soc/spi.h> |
| 23 | #if CONFIG_CHROMEOS |
| 24 | #include <vendorcode/google/chromeos/chromeos.h> |
| 25 | #endif |
Duncan Laurie | d8c4f2b | 2014-04-22 10:46:06 -0700 | [diff] [blame] | 26 | #include "nvm.h" |
Aaron Durbin | 9a7d7bc | 2013-09-07 00:41:48 -0500 | [diff] [blame] | 27 | |
| 28 | /* This module assumes the flash is memory mapped just below 4GiB in the |
| 29 | * address space for reading. Also this module assumes an area it erased |
| 30 | * when all bytes read as all 0xff's. */ |
| 31 | |
| 32 | static struct spi_flash *flash; |
| 33 | |
| 34 | static int nvm_init(void) |
| 35 | { |
| 36 | if (flash != NULL) |
| 37 | return 0; |
| 38 | |
| 39 | spi_init(); |
Gabe Black | 1e18735 | 2014-03-27 20:37:03 -0700 | [diff] [blame] | 40 | flash = spi_flash_probe(0, 0); |
Aaron Durbin | 9a7d7bc | 2013-09-07 00:41:48 -0500 | [diff] [blame] | 41 | if (!flash) { |
| 42 | printk(BIOS_DEBUG, "Could not find SPI device\n"); |
| 43 | return -1; |
| 44 | } |
| 45 | |
| 46 | return 0; |
| 47 | } |
| 48 | |
Kyösti Mälkki | 9b29aad | 2015-01-06 07:08:46 +0100 | [diff] [blame] | 49 | /* Convert memory mapped pointer to flash offset. */ |
| 50 | static inline uint32_t to_flash_offset(void *p) |
| 51 | { |
| 52 | return CONFIG_ROM_SIZE + (uintptr_t)p; |
| 53 | } |
| 54 | |
Aaron Durbin | 9a7d7bc | 2013-09-07 00:41:48 -0500 | [diff] [blame] | 55 | int nvm_is_erased(const void *start, size_t size) |
| 56 | { |
Aaron Durbin | b013fff | 2014-01-13 11:39:04 -0600 | [diff] [blame] | 57 | const uint8_t *cur = start; |
| 58 | const uint8_t erased_value = 0xff; |
Aaron Durbin | 9a7d7bc | 2013-09-07 00:41:48 -0500 | [diff] [blame] | 59 | |
| 60 | while (size > 0) { |
Aaron Durbin | b013fff | 2014-01-13 11:39:04 -0600 | [diff] [blame] | 61 | if (*cur != erased_value) |
Aaron Durbin | 9a7d7bc | 2013-09-07 00:41:48 -0500 | [diff] [blame] | 62 | return 0; |
| 63 | cur++; |
| 64 | size--; |
| 65 | } |
| 66 | return 1; |
| 67 | } |
| 68 | |
| 69 | int nvm_erase(void *start, size_t size) |
| 70 | { |
| 71 | if (nvm_init() < 0) |
| 72 | return -1; |
Kyösti Mälkki | 9b29aad | 2015-01-06 07:08:46 +0100 | [diff] [blame] | 73 | return flash->erase(flash, to_flash_offset(start), size); |
Aaron Durbin | 9a7d7bc | 2013-09-07 00:41:48 -0500 | [diff] [blame] | 74 | } |
| 75 | |
| 76 | /* Write data to NVM. Returns 0 on success < 0 on error. */ |
| 77 | int nvm_write(void *start, const void *data, size_t size) |
| 78 | { |
| 79 | if (nvm_init() < 0) |
| 80 | return -1; |
Kyösti Mälkki | 9b29aad | 2015-01-06 07:08:46 +0100 | [diff] [blame] | 81 | return flash->write(flash, to_flash_offset(start), size, data); |
Aaron Durbin | 9a7d7bc | 2013-09-07 00:41:48 -0500 | [diff] [blame] | 82 | } |
Duncan Laurie | a32b6b9 | 2015-01-15 15:49:07 -0800 | [diff] [blame] | 83 | |
| 84 | /* Read flash status register to determine if write protect is active */ |
| 85 | int nvm_is_write_protected(void) |
| 86 | { |
| 87 | u8 sr1; |
| 88 | u8 wp_gpio = 0; |
| 89 | u8 wp_spi; |
| 90 | |
| 91 | if (nvm_init() < 0) |
| 92 | return -1; |
| 93 | |
| 94 | #if IS_ENABLED(CONFIG_CHROMEOS) |
| 95 | /* Read Write Protect GPIO if available */ |
| 96 | wp_gpio = get_write_protect_state(); |
| 97 | #endif |
| 98 | |
| 99 | /* Read Status Register 1 */ |
| 100 | if (flash->status(flash, &sr1) < 0) { |
| 101 | printk(BIOS_ERR, "Failed to read SPI status register 1\n"); |
| 102 | return -1; |
| 103 | } |
| 104 | wp_spi = !!(sr1 & 0x80); |
| 105 | |
| 106 | printk(BIOS_DEBUG, "SPI flash protection: WPSW=%d SRP0=%d\n", |
| 107 | wp_gpio, wp_spi); |
| 108 | |
| 109 | return wp_gpio && wp_spi; |
| 110 | } |
| 111 | |
| 112 | /* Apply protection to a range of flash */ |
| 113 | int nvm_protect(void *start, size_t size) |
| 114 | { |
| 115 | #if IS_ENABLED(CONFIG_MRC_SETTINGS_PROTECT) |
| 116 | if (nvm_init() < 0) |
| 117 | return -1; |
| 118 | return spi_flash_protect(to_flash_offset(start), size); |
| 119 | #else |
| 120 | return -1; |
| 121 | #endif |
| 122 | } |