Aaron Durbin | 7837be6 | 2013-10-21 22:32:00 -0500 | [diff] [blame] | 1 | /* |
| 2 | * This file is part of the coreboot project. |
| 3 | * |
| 4 | * Copyright (C) 2013 Google Inc. |
| 5 | * |
| 6 | * This program is free software; you can redistribute it and/or modify |
| 7 | * it under the terms of the GNU General Public License as published by |
| 8 | * the Free Software Foundation; version 2 of the License. |
| 9 | * |
| 10 | * This program is distributed in the hope that it will be useful, |
| 11 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 12 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 13 | * GNU General Public License for more details. |
Aaron Durbin | 7837be6 | 2013-10-21 22:32:00 -0500 | [diff] [blame] | 14 | */ |
| 15 | |
| 16 | #include <stdint.h> |
| 17 | #include <stdlib.h> |
Aaron Durbin | 7837be6 | 2013-10-21 22:32:00 -0500 | [diff] [blame] | 18 | #include <arch/io.h> |
| 19 | #include <console/console.h> |
| 20 | #include <cpu/x86/cache.h> |
| 21 | #include <cpu/x86/smm.h> |
| 22 | #include <device/pci_def.h> |
| 23 | #include <elog.h> |
Patrick Georgi | 546953c | 2014-11-29 10:38:17 +0100 | [diff] [blame] | 24 | #include <halt.h> |
Aaron Durbin | 2088571 | 2014-02-09 16:04:06 -0600 | [diff] [blame] | 25 | #include <spi-generic.h> |
Aaron Durbin | 7837be6 | 2013-10-21 22:32:00 -0500 | [diff] [blame] | 26 | |
Marc Jones | 9afc5c0 | 2014-09-24 10:53:48 -0600 | [diff] [blame] | 27 | #include <soc/iosf.h> |
Julius Werner | 18ea2d3 | 2014-10-07 16:42:17 -0700 | [diff] [blame] | 28 | #include <soc/pci_devs.h> |
| 29 | #include <soc/pmc.h> |
| 30 | #include <soc/nvs.h> |
Aaron Durbin | 7837be6 | 2013-10-21 22:32:00 -0500 | [diff] [blame] | 31 | |
| 32 | /* GNVS needs to be set by coreboot initiating a software SMI. */ |
| 33 | static global_nvs_t *gnvs; |
| 34 | static int smm_initialized; |
| 35 | |
| 36 | int southbridge_io_trap_handler(int smif) |
| 37 | { |
| 38 | switch (smif) { |
| 39 | case 0x32: |
| 40 | printk(BIOS_DEBUG, "OS Init\n"); |
| 41 | /* gnvs->smif: |
| 42 | * On success, the IO Trap Handler returns 0 |
| 43 | * On failure, the IO Trap Handler returns a value != 0 |
| 44 | */ |
| 45 | gnvs->smif = 0; |
| 46 | return 1; /* IO trap handled */ |
| 47 | } |
| 48 | |
| 49 | /* Not handled */ |
| 50 | return 0; |
| 51 | } |
| 52 | |
| 53 | void southbridge_smi_set_eos(void) |
| 54 | { |
| 55 | enable_smi(EOS); |
| 56 | } |
| 57 | |
| 58 | global_nvs_t *smm_get_gnvs(void) |
| 59 | { |
| 60 | return gnvs; |
| 61 | } |
| 62 | |
| 63 | static void busmaster_disable_on_bus(int bus) |
| 64 | { |
| 65 | int slot, func; |
| 66 | unsigned int val; |
| 67 | unsigned char hdr; |
| 68 | |
| 69 | for (slot = 0; slot < 0x20; slot++) { |
| 70 | for (func = 0; func < 8; func++) { |
| 71 | u32 reg32; |
| 72 | device_t dev = PCI_DEV(bus, slot, func); |
| 73 | |
| 74 | val = pci_read_config32(dev, PCI_VENDOR_ID); |
| 75 | |
| 76 | if (val == 0xffffffff || val == 0x00000000 || |
| 77 | val == 0x0000ffff || val == 0xffff0000) |
| 78 | continue; |
| 79 | |
| 80 | /* Disable Bus Mastering for this one device */ |
| 81 | reg32 = pci_read_config32(dev, PCI_COMMAND); |
| 82 | reg32 &= ~PCI_COMMAND_MASTER; |
| 83 | pci_write_config32(dev, PCI_COMMAND, reg32); |
| 84 | |
| 85 | /* If this is a bridge, then follow it. */ |
| 86 | hdr = pci_read_config8(dev, PCI_HEADER_TYPE); |
| 87 | hdr &= 0x7f; |
| 88 | if (hdr == PCI_HEADER_TYPE_BRIDGE || |
| 89 | hdr == PCI_HEADER_TYPE_CARDBUS) { |
| 90 | unsigned int buses; |
| 91 | buses = pci_read_config32(dev, PCI_PRIMARY_BUS); |
| 92 | busmaster_disable_on_bus((buses >> 8) & 0xff); |
| 93 | } |
| 94 | } |
| 95 | } |
| 96 | } |
| 97 | |
| 98 | static void southbridge_smi_sleep(void) |
| 99 | { |
| 100 | uint32_t reg32; |
| 101 | uint8_t slp_typ; |
| 102 | uint16_t pmbase = get_pmbase(); |
| 103 | |
| 104 | /* First, disable further SMIs */ |
| 105 | disable_smi(SLP_SMI_EN); |
| 106 | |
| 107 | /* Figure out SLP_TYP */ |
| 108 | reg32 = inl(pmbase + PM1_CNT); |
| 109 | printk(BIOS_SPEW, "SMI#: SLP = 0x%08x\n", reg32); |
| 110 | slp_typ = (reg32 >> 10) & 7; |
| 111 | |
| 112 | /* Do any mainboard sleep handling */ |
| 113 | mainboard_smi_sleep(slp_typ-2); |
| 114 | |
| 115 | #if CONFIG_ELOG_GSMI |
| 116 | /* Log S3, S4, and S5 entry */ |
| 117 | if (slp_typ >= 5) |
| 118 | elog_add_event_byte(ELOG_TYPE_ACPI_ENTER, slp_typ-2); |
| 119 | #endif |
| 120 | |
| 121 | /* Next, do the deed. |
| 122 | */ |
| 123 | |
| 124 | switch (slp_typ) { |
| 125 | case SLP_TYP_S0: |
| 126 | printk(BIOS_DEBUG, "SMI#: Entering S0 (On)\n"); |
| 127 | break; |
| 128 | case SLP_TYP_S1: |
| 129 | printk(BIOS_DEBUG, "SMI#: Entering S1 (Assert STPCLK#)\n"); |
| 130 | break; |
| 131 | case SLP_TYP_S3: |
| 132 | printk(BIOS_DEBUG, "SMI#: Entering S3 (Suspend-To-RAM)\n"); |
| 133 | |
| 134 | /* Invalidate the cache before going to S3 */ |
| 135 | wbinvd(); |
| 136 | break; |
| 137 | case SLP_TYP_S4: |
| 138 | printk(BIOS_DEBUG, "SMI#: Entering S4 (Suspend-To-Disk)\n"); |
| 139 | break; |
| 140 | case SLP_TYP_S5: |
| 141 | printk(BIOS_DEBUG, "SMI#: Entering S5 (Soft Power off)\n"); |
| 142 | |
| 143 | /* Disable all GPE */ |
| 144 | disable_all_gpe(); |
| 145 | |
| 146 | /* also iterates over all bridges on bus 0 */ |
| 147 | busmaster_disable_on_bus(0); |
| 148 | break; |
| 149 | default: |
| 150 | printk(BIOS_DEBUG, "SMI#: ERROR: SLP_TYP reserved\n"); |
| 151 | break; |
| 152 | } |
| 153 | |
| 154 | /* Write back to the SLP register to cause the originally intended |
| 155 | * event again. We need to set BIT13 (SLP_EN) though to make the |
| 156 | * sleep happen. |
| 157 | */ |
| 158 | enable_pm1_control(SLP_EN); |
| 159 | |
| 160 | /* Make sure to stop executing code here for S3/S4/S5 */ |
| 161 | if (slp_typ > 1) |
Patrick Georgi | 546953c | 2014-11-29 10:38:17 +0100 | [diff] [blame] | 162 | halt(); |
Aaron Durbin | 7837be6 | 2013-10-21 22:32:00 -0500 | [diff] [blame] | 163 | |
| 164 | /* In most sleep states, the code flow of this function ends at |
| 165 | * the line above. However, if we entered sleep state S1 and wake |
| 166 | * up again, we will continue to execute code in this function. |
| 167 | */ |
| 168 | reg32 = inl(pmbase + PM1_CNT); |
| 169 | if (reg32 & SCI_EN) { |
| 170 | /* The OS is not an ACPI OS, so we set the state to S0 */ |
| 171 | disable_pm1_control(SLP_EN | SLP_TYP); |
| 172 | } |
| 173 | } |
| 174 | |
| 175 | /* |
| 176 | * Look for Synchronous IO SMI and use save state from that |
| 177 | * core in case we are not running on the same core that |
| 178 | * initiated the IO transaction. |
| 179 | */ |
| 180 | static em64t100_smm_state_save_area_t *smi_apmc_find_state_save(uint8_t cmd) |
| 181 | { |
| 182 | em64t100_smm_state_save_area_t *state; |
| 183 | int node; |
| 184 | |
| 185 | /* Check all nodes looking for the one that issued the IO */ |
| 186 | for (node = 0; node < CONFIG_MAX_CPUS; node++) { |
| 187 | state = smm_get_save_state(node); |
| 188 | |
| 189 | /* Check for Synchronous IO (bit0==1) */ |
| 190 | if (!(state->io_misc_info & (1 << 0))) |
| 191 | continue; |
| 192 | |
| 193 | /* Make sure it was a write (bit4==0) */ |
| 194 | if (state->io_misc_info & (1 << 4)) |
| 195 | continue; |
| 196 | |
| 197 | /* Check for APMC IO port */ |
| 198 | if (((state->io_misc_info >> 16) & 0xff) != APM_CNT) |
| 199 | continue; |
| 200 | |
| 201 | /* Check AX against the requested command */ |
| 202 | if ((state->rax & 0xff) != cmd) |
| 203 | continue; |
| 204 | |
| 205 | return state; |
| 206 | } |
| 207 | |
| 208 | return NULL; |
| 209 | } |
| 210 | |
| 211 | #if CONFIG_ELOG_GSMI |
| 212 | static void southbridge_smi_gsmi(void) |
| 213 | { |
| 214 | u32 *ret, *param; |
| 215 | uint8_t sub_command; |
| 216 | em64t100_smm_state_save_area_t *io_smi = |
| 217 | smi_apmc_find_state_save(ELOG_GSMI_APM_CNT); |
| 218 | |
| 219 | if (!io_smi) |
| 220 | return; |
| 221 | |
| 222 | /* Command and return value in EAX */ |
| 223 | ret = (u32*)&io_smi->rax; |
| 224 | sub_command = (uint8_t)(*ret >> 8); |
| 225 | |
| 226 | /* Parameter buffer in EBX */ |
| 227 | param = (u32*)&io_smi->rbx; |
| 228 | |
| 229 | /* drivers/elog/gsmi.c */ |
| 230 | *ret = gsmi_exec(sub_command, param); |
| 231 | } |
| 232 | #endif |
Aaron Durbin | 2088571 | 2014-02-09 16:04:06 -0600 | [diff] [blame] | 233 | |
| 234 | static void finalize(void) |
| 235 | { |
| 236 | static int finalize_done; |
| 237 | |
| 238 | if (finalize_done) { |
| 239 | printk(BIOS_DEBUG, "SMM already finalized.\n"); |
| 240 | return; |
| 241 | } |
| 242 | finalize_done = 1; |
| 243 | |
| 244 | #if CONFIG_SPI_FLASH_SMM |
| 245 | /* Re-init SPI driver to handle locked BAR */ |
| 246 | spi_init(); |
| 247 | #endif |
| 248 | } |
| 249 | |
Marc Jones | 9afc5c0 | 2014-09-24 10:53:48 -0600 | [diff] [blame] | 250 | /* |
| 251 | * soc_legacy: A payload (Depthcharge) has indicated that the |
| 252 | * legacy payload (SeaBIOS) is being loaded. Switch devices that are |
| 253 | * in ACPI mode to PCI mode so that non-ACPI drivers may work. |
| 254 | * |
| 255 | */ |
| 256 | static void soc_legacy(void) |
| 257 | { |
| 258 | u32 reg32; |
| 259 | |
| 260 | /* LPE Device */ |
| 261 | if (gnvs->dev.lpe_en) { |
| 262 | reg32 = iosf_port58_read(LPE_PCICFGCTR1); |
| 263 | reg32 &= |
| 264 | ~(LPE_PCICFGCTR1_PCI_CFG_DIS | LPE_PCICFGCTR1_ACPI_INT_EN); |
| 265 | iosf_port58_write(LPE_PCICFGCTR1, reg32); |
| 266 | } |
| 267 | |
| 268 | /* SCC Devices */ |
| 269 | #define SCC_ACPI_MODE_DISABLE(name_) \ |
| 270 | do { if (gnvs->dev.scc_en[SCC_NVS_ ## name_]) { \ |
| 271 | reg32 = iosf_scc_read(SCC_ ## name_ ## _CTL); \ |
| 272 | reg32 &= ~(SCC_CTL_PCI_CFG_DIS | SCC_CTL_ACPI_INT_EN); \ |
| 273 | iosf_scc_write(SCC_ ## name_ ## _CTL, reg32); \ |
| 274 | } } while (0) |
| 275 | |
| 276 | SCC_ACPI_MODE_DISABLE(MMC); |
| 277 | SCC_ACPI_MODE_DISABLE(SD); |
| 278 | SCC_ACPI_MODE_DISABLE(SDIO); |
| 279 | |
| 280 | /* LPSS Devices */ |
| 281 | #define LPSS_ACPI_MODE_DISABLE(name_) \ |
| 282 | do { if (gnvs->dev.lpss_en[LPSS_NVS_ ## name_]) { \ |
| 283 | reg32 = iosf_lpss_read(LPSS_ ## name_ ## _CTL); \ |
| 284 | reg32 &= ~LPSS_CTL_PCI_CFG_DIS | ~LPSS_CTL_ACPI_INT_EN; \ |
| 285 | iosf_lpss_write(LPSS_ ## name_ ## _CTL, reg32); \ |
| 286 | } } while (0) |
| 287 | |
| 288 | LPSS_ACPI_MODE_DISABLE(SIO_DMA1); |
| 289 | LPSS_ACPI_MODE_DISABLE(I2C1); |
| 290 | LPSS_ACPI_MODE_DISABLE(I2C2); |
| 291 | LPSS_ACPI_MODE_DISABLE(I2C3); |
| 292 | LPSS_ACPI_MODE_DISABLE(I2C4); |
| 293 | LPSS_ACPI_MODE_DISABLE(I2C5); |
| 294 | LPSS_ACPI_MODE_DISABLE(I2C6); |
| 295 | LPSS_ACPI_MODE_DISABLE(I2C7); |
| 296 | LPSS_ACPI_MODE_DISABLE(SIO_DMA2); |
| 297 | LPSS_ACPI_MODE_DISABLE(PWM1); |
| 298 | LPSS_ACPI_MODE_DISABLE(PWM2); |
| 299 | LPSS_ACPI_MODE_DISABLE(HSUART1); |
| 300 | LPSS_ACPI_MODE_DISABLE(HSUART2); |
| 301 | LPSS_ACPI_MODE_DISABLE(SPI); |
| 302 | } |
| 303 | |
Aaron Durbin | 7837be6 | 2013-10-21 22:32:00 -0500 | [diff] [blame] | 304 | static void southbridge_smi_apmc(void) |
| 305 | { |
| 306 | uint8_t reg8; |
| 307 | em64t100_smm_state_save_area_t *state; |
| 308 | |
| 309 | /* Emulate B2 register as the FADT / Linux expects it */ |
| 310 | |
| 311 | reg8 = inb(APM_CNT); |
| 312 | switch (reg8) { |
| 313 | case APM_CNT_CST_CONTROL: |
| 314 | /* Calling this function seems to cause |
| 315 | * some kind of race condition in Linux |
| 316 | * and causes a kernel oops |
| 317 | */ |
| 318 | printk(BIOS_DEBUG, "C-state control\n"); |
| 319 | break; |
| 320 | case APM_CNT_PST_CONTROL: |
| 321 | /* Calling this function seems to cause |
| 322 | * some kind of race condition in Linux |
| 323 | * and causes a kernel oops |
| 324 | */ |
| 325 | printk(BIOS_DEBUG, "P-state control\n"); |
| 326 | break; |
| 327 | case APM_CNT_ACPI_DISABLE: |
| 328 | disable_pm1_control(SCI_EN); |
| 329 | printk(BIOS_DEBUG, "SMI#: ACPI disabled.\n"); |
| 330 | break; |
| 331 | case APM_CNT_ACPI_ENABLE: |
| 332 | enable_pm1_control(SCI_EN); |
| 333 | printk(BIOS_DEBUG, "SMI#: ACPI enabled.\n"); |
| 334 | break; |
| 335 | case APM_CNT_GNVS_UPDATE: |
| 336 | if (smm_initialized) { |
| 337 | printk(BIOS_DEBUG, |
| 338 | "SMI#: SMM structures already initialized!\n"); |
| 339 | return; |
| 340 | } |
| 341 | state = smi_apmc_find_state_save(reg8); |
| 342 | if (state) { |
| 343 | /* EBX in the state save contains the GNVS pointer */ |
| 344 | gnvs = (global_nvs_t *)((uint32_t)state->rbx); |
| 345 | smm_initialized = 1; |
| 346 | printk(BIOS_DEBUG, "SMI#: Setting GNVS to %p\n", gnvs); |
| 347 | } |
| 348 | break; |
| 349 | #if CONFIG_ELOG_GSMI |
| 350 | case ELOG_GSMI_APM_CNT: |
| 351 | southbridge_smi_gsmi(); |
| 352 | break; |
| 353 | #endif |
Aaron Durbin | 2088571 | 2014-02-09 16:04:06 -0600 | [diff] [blame] | 354 | case APM_CNT_FINALIZE: |
| 355 | finalize(); |
| 356 | break; |
Marc Jones | 9afc5c0 | 2014-09-24 10:53:48 -0600 | [diff] [blame] | 357 | |
| 358 | case APM_CNT_LEGACY: |
| 359 | soc_legacy(); |
| 360 | break; |
Aaron Durbin | 7837be6 | 2013-10-21 22:32:00 -0500 | [diff] [blame] | 361 | } |
| 362 | |
| 363 | mainboard_smi_apmc(reg8); |
| 364 | } |
| 365 | |
| 366 | static void southbridge_smi_pm1(void) |
| 367 | { |
| 368 | uint16_t pm1_sts = clear_pm1_status(); |
| 369 | |
| 370 | /* While OSPM is not active, poweroff immediately |
| 371 | * on a power button event. |
| 372 | */ |
| 373 | if (pm1_sts & PWRBTN_STS) { |
| 374 | // power button pressed |
| 375 | #if CONFIG_ELOG_GSMI |
| 376 | elog_add_event(ELOG_TYPE_POWER_BUTTON); |
| 377 | #endif |
| 378 | disable_pm1_control(-1UL); |
Aaron Durbin | 9f83e87 | 2013-11-11 14:45:27 -0600 | [diff] [blame] | 379 | enable_pm1_control(SLP_EN | (SLP_TYP_S5 << SLP_TYP_SHIFT)); |
Aaron Durbin | 7837be6 | 2013-10-21 22:32:00 -0500 | [diff] [blame] | 380 | } |
| 381 | } |
| 382 | |
| 383 | static void southbridge_smi_gpe0(void) |
| 384 | { |
| 385 | clear_gpe_status(); |
| 386 | } |
| 387 | |
| 388 | static void southbridge_smi_tco(void) |
| 389 | { |
| 390 | uint32_t tco_sts = clear_tco_status(); |
| 391 | |
| 392 | /* Any TCO event? */ |
| 393 | if (!tco_sts) |
| 394 | return; |
| 395 | |
| 396 | if (tco_sts & TCO_TIMEOUT) { /* TIMEOUT */ |
| 397 | /* Handle TCO timeout */ |
| 398 | printk(BIOS_DEBUG, "TCO Timeout.\n"); |
| 399 | } |
| 400 | } |
| 401 | |
| 402 | static void southbridge_smi_periodic(void) |
| 403 | { |
| 404 | uint32_t reg32; |
| 405 | |
| 406 | reg32 = inl(get_pmbase() + SMI_EN); |
| 407 | |
| 408 | /* Are periodic SMIs enabled? */ |
| 409 | if ((reg32 & PERIODIC_EN) == 0) |
| 410 | return; |
| 411 | |
| 412 | printk(BIOS_DEBUG, "Periodic SMI.\n"); |
| 413 | } |
| 414 | |
| 415 | typedef void (*smi_handler_t)(void); |
| 416 | |
| 417 | static const smi_handler_t southbridge_smi[32] = { |
| 418 | NULL, // [0] reserved |
| 419 | NULL, // [1] reserved |
| 420 | NULL, // [2] BIOS_STS |
| 421 | NULL, // [3] LEGACY_USB_STS |
| 422 | southbridge_smi_sleep, // [4] SLP_SMI_STS |
| 423 | southbridge_smi_apmc, // [5] APM_STS |
| 424 | NULL, // [6] SWSMI_TMR_STS |
| 425 | NULL, // [7] reserved |
| 426 | southbridge_smi_pm1, // [8] PM1_STS |
| 427 | southbridge_smi_gpe0, // [9] GPE0_STS |
| 428 | NULL, // [10] reserved |
| 429 | NULL, // [11] reserved |
| 430 | NULL, // [12] reserved |
| 431 | southbridge_smi_tco, // [13] TCO_STS |
| 432 | southbridge_smi_periodic, // [14] PERIODIC_STS |
| 433 | NULL, // [15] SERIRQ_SMI_STS |
| 434 | NULL, // [16] SMBUS_SMI_STS |
| 435 | NULL, // [17] LEGACY_USB2_STS |
| 436 | NULL, // [18] INTEL_USB2_STS |
| 437 | NULL, // [19] reserved |
| 438 | NULL, // [20] PCI_EXP_SMI_STS |
| 439 | NULL, // [21] reserved |
| 440 | NULL, // [22] reserved |
| 441 | NULL, // [23] reserved |
| 442 | NULL, // [24] reserved |
| 443 | NULL, // [25] reserved |
| 444 | NULL, // [26] SPI_STS |
| 445 | NULL, // [27] reserved |
| 446 | NULL, // [28] PUNIT |
| 447 | NULL, // [29] GUNIT |
| 448 | NULL, // [30] reserved |
| 449 | NULL // [31] reserved |
| 450 | }; |
| 451 | |
| 452 | void southbridge_smi_handler(void) |
| 453 | { |
| 454 | int i; |
| 455 | uint32_t smi_sts; |
| 456 | |
| 457 | /* We need to clear the SMI status registers, or we won't see what's |
| 458 | * happening in the following calls. |
| 459 | */ |
| 460 | smi_sts = clear_smi_status(); |
| 461 | |
| 462 | /* Call SMI sub handler for each of the status bits */ |
| 463 | for (i = 0; i < ARRAY_SIZE(southbridge_smi); i++) { |
| 464 | if (!(smi_sts & (1 << i))) |
| 465 | continue; |
| 466 | |
| 467 | if (southbridge_smi[i] != NULL) { |
| 468 | southbridge_smi[i](); |
| 469 | } else { |
| 470 | printk(BIOS_DEBUG, |
Martin Roth | 99a3bba | 2014-12-07 14:57:26 -0700 | [diff] [blame] | 471 | "SMI_STS[%d] occurred, but no " |
Aaron Durbin | 7837be6 | 2013-10-21 22:32:00 -0500 | [diff] [blame] | 472 | "handler available.\n", i); |
| 473 | } |
| 474 | } |
Aaron Durbin | 9f83e87 | 2013-11-11 14:45:27 -0600 | [diff] [blame] | 475 | |
| 476 | /* The GPIO SMI events do not have a status bit in SMI_STS. Therefore, |
| 477 | * these events need to be cleared and checked unconditionally. */ |
| 478 | mainboard_smi_gpi(clear_alt_status()); |
Aaron Durbin | 7837be6 | 2013-10-21 22:32:00 -0500 | [diff] [blame] | 479 | } |