Aaron Durbin | 9a7d7bc | 2013-09-07 00:41:48 -0500 | [diff] [blame] | 1 | /* |
| 2 | * This file is part of the coreboot project. |
| 3 | * |
| 4 | * Copyright (C) 2013 Google, Inc. |
| 5 | * |
| 6 | * This program is free software; you can redistribute it and/or modify |
| 7 | * it under the terms of the GNU General Public License as published by |
| 8 | * the Free Software Foundation; version 2 of the License. |
| 9 | * |
| 10 | * This program is distributed in the hope that it will be useful, |
Aaron Durbin | 2c4aab3 | 2015-03-06 23:26:06 -0600 | [diff] [blame] | 11 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
Aaron Durbin | 9a7d7bc | 2013-09-07 00:41:48 -0500 | [diff] [blame] | 12 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 13 | * GNU General Public License for more details. |
Aaron Durbin | 9a7d7bc | 2013-09-07 00:41:48 -0500 | [diff] [blame] | 14 | */ |
| 15 | |
| 16 | #include <arch/io.h> |
Julius Werner | 18ea2d3 | 2014-10-07 16:42:17 -0700 | [diff] [blame] | 17 | #include <soc/iosf.h> |
Aaron Durbin | 9a7d7bc | 2013-09-07 00:41:48 -0500 | [diff] [blame] | 18 | |
| 19 | #if !defined(__PRE_RAM__) |
| 20 | #define IOSF_PCI_BASE (CONFIG_MMCONF_BASE_ADDRESS + (IOSF_PCI_DEV << 12)) |
| 21 | |
| 22 | static inline void write_iosf_reg(int reg, uint32_t value) |
| 23 | { |
Kevin Paul Herbert | bde6d30 | 2014-12-24 18:43:20 -0800 | [diff] [blame] | 24 | write32((u32 *)(IOSF_PCI_BASE + reg), value); |
Aaron Durbin | 9a7d7bc | 2013-09-07 00:41:48 -0500 | [diff] [blame] | 25 | } |
| 26 | static inline uint32_t read_iosf_reg(int reg) |
| 27 | { |
Kevin Paul Herbert | bde6d30 | 2014-12-24 18:43:20 -0800 | [diff] [blame] | 28 | return read32((u32 *)(IOSF_PCI_BASE + reg)); |
Aaron Durbin | 9a7d7bc | 2013-09-07 00:41:48 -0500 | [diff] [blame] | 29 | } |
| 30 | #else |
| 31 | static inline void write_iosf_reg(int reg, uint32_t value) |
| 32 | { |
| 33 | pci_write_config32(IOSF_PCI_DEV, reg, value); |
| 34 | } |
| 35 | static inline uint32_t read_iosf_reg(int reg) |
| 36 | { |
| 37 | return pci_read_config32(IOSF_PCI_DEV, reg); |
| 38 | } |
| 39 | #endif |
| 40 | |
Aaron Durbin | 4a082c6 | 2013-10-31 11:58:32 -0500 | [diff] [blame] | 41 | /* Common sequences for all the port accesses. */ |
| 42 | static uint32_t iosf_read_port(uint32_t cr, int reg) |
Aaron Durbin | 9a7d7bc | 2013-09-07 00:41:48 -0500 | [diff] [blame] | 43 | { |
Aaron Durbin | 4a082c6 | 2013-10-31 11:58:32 -0500 | [diff] [blame] | 44 | cr |= IOSF_REG(reg) | IOSF_BYTE_EN; |
Aaron Durbin | 67633a5 | 2013-10-29 10:57:31 -0500 | [diff] [blame] | 45 | write_iosf_reg(MCRX_REG, IOSF_REG_UPPER(reg)); |
Aaron Durbin | 9a7d7bc | 2013-09-07 00:41:48 -0500 | [diff] [blame] | 46 | write_iosf_reg(MCR_REG, cr); |
| 47 | return read_iosf_reg(MDR_REG); |
| 48 | } |
| 49 | |
Aaron Durbin | 4a082c6 | 2013-10-31 11:58:32 -0500 | [diff] [blame] | 50 | static void iosf_write_port(uint32_t cr, int reg, uint32_t val) |
Aaron Durbin | 9a7d7bc | 2013-09-07 00:41:48 -0500 | [diff] [blame] | 51 | { |
Aaron Durbin | 4a082c6 | 2013-10-31 11:58:32 -0500 | [diff] [blame] | 52 | cr |= IOSF_REG(reg) | IOSF_BYTE_EN; |
Aaron Durbin | 9a7d7bc | 2013-09-07 00:41:48 -0500 | [diff] [blame] | 53 | write_iosf_reg(MDR_REG, val); |
Aaron Durbin | 67633a5 | 2013-10-29 10:57:31 -0500 | [diff] [blame] | 54 | write_iosf_reg(MCRX_REG, IOSF_REG_UPPER(reg)); |
Duncan Laurie | e549e94 | 2013-10-28 14:18:38 -0700 | [diff] [blame] | 55 | write_iosf_reg(MCR_REG, cr); |
Aaron Durbin | 9a7d7bc | 2013-09-07 00:41:48 -0500 | [diff] [blame] | 56 | } |
Aaron Durbin | 4c53df4 | 2013-09-23 14:17:35 -0500 | [diff] [blame] | 57 | |
Aaron Durbin | 5cc3b40 | 2013-12-11 17:10:58 -0800 | [diff] [blame] | 58 | #define IOSF_READ(port) \ |
| 59 | IOSF_OPCODE(IOSF_OP_READ_##port) | IOSF_PORT(IOSF_PORT_##port) |
| 60 | #define IOSF_WRITE(port) \ |
| 61 | IOSF_OPCODE(IOSF_OP_WRITE_##port) | IOSF_PORT(IOSF_PORT_##port) |
| 62 | |
Aaron Durbin | 4a082c6 | 2013-10-31 11:58:32 -0500 | [diff] [blame] | 63 | uint32_t iosf_bunit_read(int reg) |
| 64 | { |
Aaron Durbin | 5cc3b40 | 2013-12-11 17:10:58 -0800 | [diff] [blame] | 65 | return iosf_read_port(IOSF_READ(BUNIT), reg); |
Aaron Durbin | 4a082c6 | 2013-10-31 11:58:32 -0500 | [diff] [blame] | 66 | } |
| 67 | |
| 68 | void iosf_bunit_write(int reg, uint32_t val) |
| 69 | { |
Aaron Durbin | 5cc3b40 | 2013-12-11 17:10:58 -0800 | [diff] [blame] | 70 | iosf_write_port(IOSF_WRITE(BUNIT), reg, val); |
Aaron Durbin | 4a082c6 | 2013-10-31 11:58:32 -0500 | [diff] [blame] | 71 | } |
| 72 | |
Aaron Durbin | 4c53df4 | 2013-09-23 14:17:35 -0500 | [diff] [blame] | 73 | uint32_t iosf_dunit_read(int reg) |
| 74 | { |
Aaron Durbin | 5cc3b40 | 2013-12-11 17:10:58 -0800 | [diff] [blame] | 75 | return iosf_read_port(IOSF_READ(SYSMEMC), reg); |
Aaron Durbin | 4c53df4 | 2013-09-23 14:17:35 -0500 | [diff] [blame] | 76 | } |
| 77 | |
Aaron Durbin | 3ccb3ce | 2013-10-11 00:26:04 -0500 | [diff] [blame] | 78 | uint32_t iosf_dunit_ch0_read(int reg) |
| 79 | { |
| 80 | return iosf_dunit_read(reg); |
| 81 | } |
| 82 | |
| 83 | uint32_t iosf_dunit_ch1_read(int reg) |
| 84 | { |
| 85 | uint32_t cr = IOSF_OPCODE(IOSF_OP_READ_SYSMEMC) | |
Aaron Durbin | 4a082c6 | 2013-10-31 11:58:32 -0500 | [diff] [blame] | 86 | IOSF_PORT(IOSF_PORT_DUNIT_CH1); |
| 87 | return iosf_read_port(cr, reg); |
Aaron Durbin | 3ccb3ce | 2013-10-11 00:26:04 -0500 | [diff] [blame] | 88 | } |
| 89 | |
Aaron Durbin | 4c53df4 | 2013-09-23 14:17:35 -0500 | [diff] [blame] | 90 | void iosf_dunit_write(int reg, uint32_t val) |
| 91 | { |
Aaron Durbin | 5cc3b40 | 2013-12-11 17:10:58 -0800 | [diff] [blame] | 92 | iosf_write_port(IOSF_WRITE(SYSMEMC), reg, val); |
Aaron Durbin | 3f5a1ff | 2013-10-04 15:23:31 -0500 | [diff] [blame] | 93 | } |
| 94 | |
| 95 | uint32_t iosf_punit_read(int reg) |
| 96 | { |
Aaron Durbin | 5cc3b40 | 2013-12-11 17:10:58 -0800 | [diff] [blame] | 97 | return iosf_read_port(IOSF_READ(PMC), reg); |
Aaron Durbin | 3f5a1ff | 2013-10-04 15:23:31 -0500 | [diff] [blame] | 98 | } |
| 99 | |
| 100 | void iosf_punit_write(int reg, uint32_t val) |
| 101 | { |
Aaron Durbin | 5cc3b40 | 2013-12-11 17:10:58 -0800 | [diff] [blame] | 102 | iosf_write_port(IOSF_WRITE(PMC), reg, val); |
Aaron Durbin | 4c53df4 | 2013-09-23 14:17:35 -0500 | [diff] [blame] | 103 | } |
Duncan Laurie | 0854c84 | 2013-10-31 08:20:48 -0700 | [diff] [blame] | 104 | |
| 105 | uint32_t iosf_usbphy_read(int reg) |
| 106 | { |
Aaron Durbin | 5cc3b40 | 2013-12-11 17:10:58 -0800 | [diff] [blame] | 107 | return iosf_read_port(IOSF_READ(USBPHY), reg); |
Duncan Laurie | 0854c84 | 2013-10-31 08:20:48 -0700 | [diff] [blame] | 108 | } |
| 109 | |
| 110 | void iosf_usbphy_write(int reg, uint32_t val) |
| 111 | { |
Aaron Durbin | 5cc3b40 | 2013-12-11 17:10:58 -0800 | [diff] [blame] | 112 | return iosf_write_port(IOSF_WRITE(USBPHY), reg, val); |
Duncan Laurie | 0854c84 | 2013-10-31 08:20:48 -0700 | [diff] [blame] | 113 | } |
| 114 | |
| 115 | uint32_t iosf_ushphy_read(int reg) |
| 116 | { |
Aaron Durbin | 5cc3b40 | 2013-12-11 17:10:58 -0800 | [diff] [blame] | 117 | return iosf_read_port(IOSF_READ(USHPHY), reg); |
Duncan Laurie | 0854c84 | 2013-10-31 08:20:48 -0700 | [diff] [blame] | 118 | } |
| 119 | |
| 120 | void iosf_ushphy_write(int reg, uint32_t val) |
| 121 | { |
Aaron Durbin | 5cc3b40 | 2013-12-11 17:10:58 -0800 | [diff] [blame] | 122 | return iosf_write_port(IOSF_WRITE(USHPHY), reg, val); |
Duncan Laurie | 0854c84 | 2013-10-31 08:20:48 -0700 | [diff] [blame] | 123 | } |
Aaron Durbin | bc69ae9 | 2013-10-31 10:46:56 -0500 | [diff] [blame] | 124 | |
| 125 | uint32_t iosf_lpss_read(int reg) |
| 126 | { |
Aaron Durbin | 5cc3b40 | 2013-12-11 17:10:58 -0800 | [diff] [blame] | 127 | return iosf_read_port(IOSF_READ(LPSS), reg); |
Aaron Durbin | bc69ae9 | 2013-10-31 10:46:56 -0500 | [diff] [blame] | 128 | } |
| 129 | |
| 130 | void iosf_lpss_write(int reg, uint32_t val) |
| 131 | { |
Aaron Durbin | 5cc3b40 | 2013-12-11 17:10:58 -0800 | [diff] [blame] | 132 | return iosf_write_port(IOSF_WRITE(LPSS), reg, val); |
Aaron Durbin | bc69ae9 | 2013-10-31 10:46:56 -0500 | [diff] [blame] | 133 | } |
Aaron Durbin | 65ad521 | 2013-11-01 14:19:24 -0500 | [diff] [blame] | 134 | |
| 135 | uint32_t iosf_ccu_read(int reg) |
| 136 | { |
Aaron Durbin | 5cc3b40 | 2013-12-11 17:10:58 -0800 | [diff] [blame] | 137 | return iosf_read_port(IOSF_READ(CCU), reg); |
Aaron Durbin | 65ad521 | 2013-11-01 14:19:24 -0500 | [diff] [blame] | 138 | } |
| 139 | |
| 140 | void iosf_ccu_write(int reg, uint32_t val) |
| 141 | { |
Aaron Durbin | 5cc3b40 | 2013-12-11 17:10:58 -0800 | [diff] [blame] | 142 | return iosf_write_port(IOSF_WRITE(CCU), reg, val); |
Aaron Durbin | 65ad521 | 2013-11-01 14:19:24 -0500 | [diff] [blame] | 143 | } |
Aaron Durbin | d7f0f3d | 2013-11-12 16:37:05 -0600 | [diff] [blame] | 144 | |
| 145 | uint32_t iosf_score_read(int reg) |
| 146 | { |
Aaron Durbin | 5cc3b40 | 2013-12-11 17:10:58 -0800 | [diff] [blame] | 147 | return iosf_read_port(IOSF_READ(SCORE), reg); |
Aaron Durbin | d7f0f3d | 2013-11-12 16:37:05 -0600 | [diff] [blame] | 148 | } |
| 149 | |
| 150 | void iosf_score_write(int reg, uint32_t val) |
| 151 | { |
Aaron Durbin | 5cc3b40 | 2013-12-11 17:10:58 -0800 | [diff] [blame] | 152 | return iosf_write_port(IOSF_WRITE(SCORE), reg, val); |
Aaron Durbin | d7f0f3d | 2013-11-12 16:37:05 -0600 | [diff] [blame] | 153 | } |
| 154 | |
| 155 | uint32_t iosf_scc_read(int reg) |
| 156 | { |
Aaron Durbin | 5cc3b40 | 2013-12-11 17:10:58 -0800 | [diff] [blame] | 157 | return iosf_read_port(IOSF_READ(SCC), reg); |
Aaron Durbin | d7f0f3d | 2013-11-12 16:37:05 -0600 | [diff] [blame] | 158 | } |
| 159 | |
| 160 | void iosf_scc_write(int reg, uint32_t val) |
| 161 | { |
Aaron Durbin | 5cc3b40 | 2013-12-11 17:10:58 -0800 | [diff] [blame] | 162 | return iosf_write_port(IOSF_WRITE(SCC), reg, val); |
Aaron Durbin | d7f0f3d | 2013-11-12 16:37:05 -0600 | [diff] [blame] | 163 | } |
Aaron Durbin | bc5b557 | 2013-12-11 17:13:10 -0800 | [diff] [blame] | 164 | |
| 165 | uint32_t iosf_aunit_read(int reg) |
| 166 | { |
| 167 | return iosf_read_port(IOSF_READ(AUNIT), reg); |
| 168 | } |
| 169 | |
| 170 | void iosf_aunit_write(int reg, uint32_t val) |
| 171 | { |
| 172 | return iosf_write_port(IOSF_WRITE(AUNIT), reg, val); |
| 173 | } |
| 174 | |
| 175 | uint32_t iosf_cpu_bus_read(int reg) |
| 176 | { |
| 177 | return iosf_read_port(IOSF_READ(CPU_BUS), reg); |
| 178 | } |
| 179 | |
| 180 | void iosf_cpu_bus_write(int reg, uint32_t val) |
| 181 | { |
| 182 | return iosf_write_port(IOSF_WRITE(CPU_BUS), reg, val); |
| 183 | } |
| 184 | |
| 185 | uint32_t iosf_sec_read(int reg) |
| 186 | { |
| 187 | return iosf_read_port(IOSF_READ(SEC), reg); |
| 188 | } |
| 189 | |
| 190 | void iosf_sec_write(int reg, uint32_t val) |
| 191 | { |
| 192 | return iosf_write_port(IOSF_WRITE(SEC), reg, val); |
| 193 | } |
| 194 | |
| 195 | uint32_t iosf_port45_read(int reg) |
| 196 | { |
| 197 | return iosf_read_port(IOSF_READ(0x45), reg); |
| 198 | } |
| 199 | |
| 200 | void iosf_port45_write(int reg, uint32_t val) |
| 201 | { |
| 202 | return iosf_write_port(IOSF_WRITE(0x45), reg, val); |
| 203 | } |
| 204 | |
| 205 | uint32_t iosf_port46_read(int reg) |
| 206 | { |
| 207 | return iosf_read_port(IOSF_READ(0x46), reg); |
| 208 | } |
| 209 | |
| 210 | void iosf_port46_write(int reg, uint32_t val) |
| 211 | { |
| 212 | return iosf_write_port(IOSF_WRITE(0x46), reg, val); |
| 213 | } |
| 214 | |
| 215 | uint32_t iosf_port47_read(int reg) |
| 216 | { |
| 217 | return iosf_read_port(IOSF_READ(0x47), reg); |
| 218 | } |
| 219 | |
| 220 | void iosf_port47_write(int reg, uint32_t val) |
| 221 | { |
| 222 | return iosf_write_port(IOSF_WRITE(0x47), reg, val); |
| 223 | } |
| 224 | |
| 225 | uint32_t iosf_port55_read(int reg) |
| 226 | { |
| 227 | return iosf_read_port(IOSF_READ(0x55), reg); |
| 228 | } |
| 229 | |
| 230 | void iosf_port55_write(int reg, uint32_t val) |
| 231 | { |
| 232 | return iosf_write_port(IOSF_WRITE(0x55), reg, val); |
| 233 | } |
| 234 | |
| 235 | uint32_t iosf_port58_read(int reg) |
| 236 | { |
| 237 | return iosf_read_port(IOSF_READ(0x58), reg); |
| 238 | } |
| 239 | |
| 240 | void iosf_port58_write(int reg, uint32_t val) |
| 241 | { |
| 242 | return iosf_write_port(IOSF_WRITE(0x58), reg, val); |
| 243 | } |
| 244 | |
| 245 | uint32_t iosf_port59_read(int reg) |
| 246 | { |
| 247 | return iosf_read_port(IOSF_READ(0x59), reg); |
| 248 | } |
| 249 | |
| 250 | void iosf_port59_write(int reg, uint32_t val) |
| 251 | { |
| 252 | return iosf_write_port(IOSF_WRITE(0x59), reg, val); |
| 253 | } |
| 254 | |
| 255 | uint32_t iosf_port5a_read(int reg) |
| 256 | { |
| 257 | return iosf_read_port(IOSF_READ(0x5a), reg); |
| 258 | } |
| 259 | |
| 260 | void iosf_port5a_write(int reg, uint32_t val) |
| 261 | { |
| 262 | return iosf_write_port(IOSF_WRITE(0x5a), reg, val); |
| 263 | } |
| 264 | |
| 265 | uint32_t iosf_porta2_read(int reg) |
| 266 | { |
| 267 | return iosf_read_port(IOSF_READ(0xa2), reg); |
| 268 | } |
| 269 | |
| 270 | void iosf_porta2_write(int reg, uint32_t val) |
| 271 | { |
| 272 | return iosf_write_port(IOSF_WRITE(0xa2), reg, val); |
| 273 | } |
| 274 | |
| 275 | uint32_t iosf_ssus_read(int reg) |
| 276 | { |
| 277 | return iosf_read_port(IOSF_READ(SSUS), reg); |
| 278 | } |
| 279 | |
| 280 | void iosf_ssus_write(int reg, uint32_t val) |
| 281 | { |
| 282 | return iosf_write_port(IOSF_WRITE(SSUS), reg, val); |
| 283 | } |