Aaron Durbin | 302cbd6 | 2013-10-21 12:36:17 -0500 | [diff] [blame] | 1 | /* |
| 2 | * This file is part of the coreboot project. |
| 3 | * |
| 4 | * Copyright (C) 2013 Google Inc. |
| 5 | * |
| 6 | * This program is free software; you can redistribute it and/or modify |
| 7 | * it under the terms of the GNU General Public License as published by |
| 8 | * the Free Software Foundation; version 2 of the License. |
| 9 | * |
| 10 | * This program is distributed in the hope that it will be useful, |
| 11 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 12 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 13 | * GNU General Public License for more details. |
Aaron Durbin | 302cbd6 | 2013-10-21 12:36:17 -0500 | [diff] [blame] | 14 | */ |
| 15 | |
| 16 | #include <stdlib.h> |
| 17 | #include <console/console.h> |
| 18 | #include <cpu/cpu.h> |
| 19 | #include <cpu/intel/microcode.h> |
Duncan Laurie | 05a3393 | 2013-11-05 12:59:50 -0800 | [diff] [blame] | 20 | #include <cpu/intel/turbo.h> |
Aaron Durbin | 7837be6 | 2013-10-21 22:32:00 -0500 | [diff] [blame] | 21 | #include <cpu/x86/cache.h> |
| 22 | #include <cpu/x86/lapic.h> |
Aaron Durbin | 302cbd6 | 2013-10-21 12:36:17 -0500 | [diff] [blame] | 23 | #include <cpu/x86/mp.h> |
Aaron Durbin | 7837be6 | 2013-10-21 22:32:00 -0500 | [diff] [blame] | 24 | #include <cpu/x86/msr.h> |
| 25 | #include <cpu/x86/mtrr.h> |
| 26 | #include <cpu/x86/smm.h> |
Duncan Laurie | 05a3393 | 2013-11-05 12:59:50 -0800 | [diff] [blame] | 27 | #include <reg_script.h> |
Aaron Durbin | 302cbd6 | 2013-10-21 12:36:17 -0500 | [diff] [blame] | 28 | |
Julius Werner | 18ea2d3 | 2014-10-07 16:42:17 -0700 | [diff] [blame] | 29 | #include <soc/iosf.h> |
| 30 | #include <soc/msr.h> |
| 31 | #include <soc/pattrs.h> |
| 32 | #include <soc/ramstage.h> |
| 33 | #include <soc/smm.h> |
Aaron Durbin | 7837be6 | 2013-10-21 22:32:00 -0500 | [diff] [blame] | 34 | |
Aaron Durbin | 7837be6 | 2013-10-21 22:32:00 -0500 | [diff] [blame] | 35 | static void smm_relocate(void *unused); |
| 36 | static void enable_smis(void *unused); |
Aaron Durbin | 302cbd6 | 2013-10-21 12:36:17 -0500 | [diff] [blame] | 37 | |
| 38 | static struct mp_flight_record mp_steps[] = { |
Aaron Durbin | 7837be6 | 2013-10-21 22:32:00 -0500 | [diff] [blame] | 39 | MP_FR_BLOCK_APS(smm_relocate, NULL, smm_relocate, NULL), |
Aaron Durbin | 302cbd6 | 2013-10-21 12:36:17 -0500 | [diff] [blame] | 40 | MP_FR_BLOCK_APS(mp_initialize_cpu, NULL, mp_initialize_cpu, NULL), |
Aaron Durbin | 7837be6 | 2013-10-21 22:32:00 -0500 | [diff] [blame] | 41 | /* Wait for APs to finish initialization before proceeding. */ |
| 42 | MP_FR_BLOCK_APS(NULL, NULL, enable_smis, NULL), |
Aaron Durbin | 302cbd6 | 2013-10-21 12:36:17 -0500 | [diff] [blame] | 43 | }; |
| 44 | |
| 45 | /* The APIC id space on Bay Trail is sparse. Each id is separated by 2. */ |
| 46 | static int adjust_apic_id(int index, int apic_id) |
| 47 | { |
| 48 | return 2 * index; |
| 49 | } |
| 50 | |
Duncan Laurie | 05a3393 | 2013-11-05 12:59:50 -0800 | [diff] [blame] | 51 | /* Package level MSRs */ |
| 52 | const struct reg_script package_msr_script[] = { |
| 53 | /* Set Package TDP to ~7W */ |
| 54 | REG_MSR_WRITE(MSR_PKG_POWER_LIMIT, 0x3880fa), |
Aaron Durbin | 4177db5 | 2014-02-05 14:55:26 -0600 | [diff] [blame] | 55 | REG_MSR_RMW(MSR_PP1_POWER_LIMIT, ~(0x7f << 17), 0), |
Duncan Laurie | 05a3393 | 2013-11-05 12:59:50 -0800 | [diff] [blame] | 56 | REG_MSR_WRITE(MSR_PKG_TURBO_CFG1, 0x702), |
| 57 | REG_MSR_WRITE(MSR_CPU_TURBO_WKLD_CFG1, 0x200b), |
| 58 | REG_MSR_WRITE(MSR_CPU_TURBO_WKLD_CFG2, 0), |
Aaron Durbin | 4177db5 | 2014-02-05 14:55:26 -0600 | [diff] [blame] | 59 | REG_MSR_WRITE(MSR_CPU_THERM_CFG1, 0x00000305), |
| 60 | REG_MSR_WRITE(MSR_CPU_THERM_CFG2, 0x0405500d), |
| 61 | REG_MSR_WRITE(MSR_CPU_THERM_SENS_CFG, 0x27), |
Duncan Laurie | 05a3393 | 2013-11-05 12:59:50 -0800 | [diff] [blame] | 62 | REG_SCRIPT_END |
| 63 | }; |
| 64 | |
| 65 | /* Core level MSRs */ |
| 66 | const struct reg_script core_msr_script[] = { |
Duncan Laurie | 31ac9e3 | 2014-03-28 10:52:13 -0700 | [diff] [blame] | 67 | /* Dynamic L2 shrink enable and threshold, clear SINGLE_PCTL bit 11 */ |
| 68 | REG_MSR_RMW(MSR_PMG_CST_CONFIG_CONTROL, ~0x3f080f, 0xe0008), |
| 69 | REG_MSR_RMW(MSR_POWER_MISC, |
| 70 | ~(ENABLE_ULFM_AUTOCM_MASK | ENABLE_INDP_AUTOCM_MASK), 0), |
Duncan Laurie | 05a3393 | 2013-11-05 12:59:50 -0800 | [diff] [blame] | 71 | /* Disable C1E */ |
| 72 | REG_MSR_RMW(MSR_POWER_CTL, ~0x2, 0), |
| 73 | REG_MSR_OR(MSR_POWER_MISC, 0x44), |
| 74 | REG_SCRIPT_END |
| 75 | }; |
| 76 | |
Aaron Durbin | 302cbd6 | 2013-10-21 12:36:17 -0500 | [diff] [blame] | 77 | void baytrail_init_cpus(device_t dev) |
| 78 | { |
| 79 | struct bus *cpu_bus = dev->link_list; |
| 80 | const struct pattrs *pattrs = pattrs_get(); |
| 81 | struct mp_params mp_params; |
Kein Yuan | 3511023 | 2014-02-22 12:26:55 -0800 | [diff] [blame] | 82 | uint32_t bsmrwac; |
| 83 | void *default_smm_area; |
Aaron Durbin | 302cbd6 | 2013-10-21 12:36:17 -0500 | [diff] [blame] | 84 | |
| 85 | /* Set up MTRRs based on physical address size. */ |
| 86 | x86_setup_fixed_mtrrs(); |
| 87 | x86_setup_var_mtrrs(pattrs->address_bits, 2); |
| 88 | x86_mtrr_check(); |
| 89 | |
| 90 | mp_params.num_cpus = pattrs->num_cpus, |
| 91 | mp_params.parallel_microcode_load = 1, |
| 92 | mp_params.adjust_apic_id = adjust_apic_id; |
| 93 | mp_params.flight_plan = &mp_steps[0]; |
| 94 | mp_params.num_records = ARRAY_SIZE(mp_steps); |
Aaron Durbin | 315bb30 | 2013-10-24 14:55:42 -0500 | [diff] [blame] | 95 | mp_params.microcode_pointer = pattrs->microcode_patch; |
Aaron Durbin | 302cbd6 | 2013-10-21 12:36:17 -0500 | [diff] [blame] | 96 | |
Kein Yuan | 3511023 | 2014-02-22 12:26:55 -0800 | [diff] [blame] | 97 | default_smm_area = backup_default_smm_area(); |
| 98 | |
| 99 | /* |
| 100 | * Configure the BUNIT to allow dirty cache line evictions in non-SMM |
| 101 | * mode for the lines that were dirtied while in SMM mode. Otherwise |
| 102 | * the writes would be silently dropped. |
| 103 | */ |
| 104 | bsmrwac = iosf_bunit_read(BUNIT_SMRWAC) | SAI_IA_UNTRUSTED; |
| 105 | iosf_bunit_write(BUNIT_SMRWAC, bsmrwac); |
| 106 | |
Duncan Laurie | 05a3393 | 2013-11-05 12:59:50 -0800 | [diff] [blame] | 107 | /* Set package MSRs */ |
| 108 | reg_script_run(package_msr_script); |
| 109 | |
Aaron Durbin | 59d1d87 | 2014-01-14 17:34:10 -0600 | [diff] [blame] | 110 | /* Enable Turbo Mode on BSP and siblings of the BSP's building block. */ |
Duncan Laurie | 05a3393 | 2013-11-05 12:59:50 -0800 | [diff] [blame] | 111 | enable_turbo(); |
| 112 | |
Aaron Durbin | 302cbd6 | 2013-10-21 12:36:17 -0500 | [diff] [blame] | 113 | if (mp_init(cpu_bus, &mp_params)) { |
| 114 | printk(BIOS_ERR, "MP initialization failure.\n"); |
| 115 | } |
Kein Yuan | 3511023 | 2014-02-22 12:26:55 -0800 | [diff] [blame] | 116 | |
| 117 | restore_default_smm_area(default_smm_area); |
Aaron Durbin | 302cbd6 | 2013-10-21 12:36:17 -0500 | [diff] [blame] | 118 | } |
| 119 | |
| 120 | static void baytrail_core_init(device_t cpu) |
| 121 | { |
| 122 | printk(BIOS_DEBUG, "Init BayTrail core.\n"); |
Duncan Laurie | 05a3393 | 2013-11-05 12:59:50 -0800 | [diff] [blame] | 123 | |
Aaron Durbin | 59d1d87 | 2014-01-14 17:34:10 -0600 | [diff] [blame] | 124 | /* On bay trail the turbo disable bit is actually scoped at building |
| 125 | * block level -- not package. For non-bsp cores that are within a |
| 126 | * building block enable turbo. The cores within the BSP's building |
| 127 | * block will just see it already enabled and move on. */ |
| 128 | if (lapicid()) |
| 129 | enable_turbo(); |
| 130 | |
Duncan Laurie | 05a3393 | 2013-11-05 12:59:50 -0800 | [diff] [blame] | 131 | /* Set core MSRs */ |
| 132 | reg_script_run(core_msr_script); |
| 133 | |
| 134 | /* Set this core to max frequency ratio */ |
| 135 | set_max_freq(); |
Aaron Durbin | 302cbd6 | 2013-10-21 12:36:17 -0500 | [diff] [blame] | 136 | } |
| 137 | |
| 138 | static struct device_operations cpu_dev_ops = { |
| 139 | .init = baytrail_core_init, |
| 140 | }; |
| 141 | |
| 142 | static struct cpu_device_id cpu_table[] = { |
| 143 | { X86_VENDOR_INTEL, 0x30673 }, |
Aaron Durbin | 1ea9bde | 2014-01-08 17:33:05 -0600 | [diff] [blame] | 144 | { X86_VENDOR_INTEL, 0x30678 }, |
Aaron Durbin | 302cbd6 | 2013-10-21 12:36:17 -0500 | [diff] [blame] | 145 | { 0, 0 }, |
| 146 | }; |
| 147 | |
| 148 | static const struct cpu_driver driver __cpu_driver = { |
| 149 | .ops = &cpu_dev_ops, |
| 150 | .id_table = cpu_table, |
| 151 | }; |
| 152 | |
Aaron Durbin | 7837be6 | 2013-10-21 22:32:00 -0500 | [diff] [blame] | 153 | |
| 154 | /* |
| 155 | * SMM loading and initialization. |
| 156 | */ |
| 157 | |
| 158 | struct smm_relocation_attrs { |
| 159 | uint32_t smbase; |
| 160 | uint32_t smrr_base; |
| 161 | uint32_t smrr_mask; |
| 162 | }; |
| 163 | |
| 164 | static struct smm_relocation_attrs relo_attrs; |
| 165 | |
| 166 | static void adjust_apic_id_map(struct smm_loader_params *smm_params) |
| 167 | { |
| 168 | int i; |
| 169 | struct smm_runtime *runtime = smm_params->runtime; |
| 170 | |
| 171 | for (i = 0; i < CONFIG_MAX_CPUS; i++) |
| 172 | runtime->apic_id_to_cpu[i] = mp_get_apic_id(i); |
| 173 | } |
| 174 | |
Aaron Durbin | 3eb8eb7 | 2014-03-10 16:13:58 -0500 | [diff] [blame] | 175 | static void asmlinkage cpu_smm_do_relocation(void *arg) |
Aaron Durbin | 7837be6 | 2013-10-21 22:32:00 -0500 | [diff] [blame] | 176 | { |
| 177 | msr_t smrr; |
| 178 | em64t100_smm_state_save_area_t *smm_state; |
Aaron Durbin | 3eb8eb7 | 2014-03-10 16:13:58 -0500 | [diff] [blame] | 179 | const struct smm_module_params *p; |
| 180 | const struct smm_runtime *runtime; |
| 181 | int cpu; |
| 182 | |
| 183 | p = arg; |
| 184 | runtime = p->runtime; |
| 185 | cpu = p->cpu; |
Aaron Durbin | 7837be6 | 2013-10-21 22:32:00 -0500 | [diff] [blame] | 186 | |
| 187 | if (cpu >= CONFIG_MAX_CPUS) { |
| 188 | printk(BIOS_CRIT, |
| 189 | "Invalid CPU number assigned in SMM stub: %d\n", cpu); |
| 190 | return; |
| 191 | } |
| 192 | |
| 193 | /* Set up SMRR. */ |
| 194 | smrr.lo = relo_attrs.smrr_base; |
| 195 | smrr.hi = 0; |
Alexandru Gagniuc | 86091f9 | 2015-09-30 20:23:09 -0700 | [diff] [blame] | 196 | wrmsr(SMRR_PHYS_BASE, smrr); |
Aaron Durbin | 7837be6 | 2013-10-21 22:32:00 -0500 | [diff] [blame] | 197 | smrr.lo = relo_attrs.smrr_mask; |
| 198 | smrr.hi = 0; |
Alexandru Gagniuc | 86091f9 | 2015-09-30 20:23:09 -0700 | [diff] [blame] | 199 | wrmsr(SMRR_PHYS_MASK, smrr); |
Aaron Durbin | 7837be6 | 2013-10-21 22:32:00 -0500 | [diff] [blame] | 200 | |
| 201 | /* The relocated handler runs with all CPUs concurrently. Therefore |
| 202 | * stagger the entry points adjusting SMBASE downwards by save state |
| 203 | * size * CPU num. */ |
| 204 | smm_state = (void *)(SMM_EM64T100_SAVE_STATE_OFFSET + runtime->smbase); |
| 205 | smm_state->smbase = relo_attrs.smbase - cpu * runtime->save_state_size; |
| 206 | printk(BIOS_DEBUG, "New SMBASE 0x%08x\n", smm_state->smbase); |
| 207 | } |
| 208 | |
| 209 | static int install_relocation_handler(int num_cpus) |
| 210 | { |
| 211 | const int save_state_size = sizeof(em64t100_smm_state_save_area_t); |
| 212 | |
| 213 | struct smm_loader_params smm_params = { |
| 214 | .per_cpu_stack_size = save_state_size, |
| 215 | .num_concurrent_stacks = num_cpus, |
| 216 | .per_cpu_save_state_size = save_state_size, |
| 217 | .num_concurrent_save_states = 1, |
| 218 | .handler = (smm_handler_t)&cpu_smm_do_relocation, |
| 219 | }; |
| 220 | |
| 221 | if (smm_setup_relocation_handler(&smm_params)) |
| 222 | return -1; |
| 223 | |
| 224 | adjust_apic_id_map(&smm_params); |
| 225 | |
| 226 | return 0; |
| 227 | } |
| 228 | |
| 229 | static int install_permanent_handler(int num_cpus) |
| 230 | { |
| 231 | /* There are num_cpus concurrent stacks and num_cpus concurrent save |
| 232 | * state areas. Lastly, set the stack size to the save state size. */ |
| 233 | int save_state_size = sizeof(em64t100_smm_state_save_area_t); |
| 234 | struct smm_loader_params smm_params = { |
| 235 | .per_cpu_stack_size = save_state_size, |
| 236 | .num_concurrent_stacks = num_cpus, |
| 237 | .per_cpu_save_state_size = save_state_size, |
| 238 | .num_concurrent_save_states = num_cpus, |
| 239 | }; |
| 240 | const int tseg_size = smm_region_size() - CONFIG_SMM_RESERVED_SIZE; |
| 241 | |
| 242 | printk(BIOS_DEBUG, "Installing SMM handler to 0x%08x\n", |
| 243 | relo_attrs.smbase); |
| 244 | |
| 245 | if (smm_load_module((void *)relo_attrs.smbase, tseg_size, &smm_params)) |
| 246 | return -1; |
| 247 | |
| 248 | adjust_apic_id_map(&smm_params); |
| 249 | |
| 250 | return 0; |
| 251 | } |
| 252 | |
| 253 | static int smm_load_handlers(void) |
| 254 | { |
| 255 | /* All range registers are aligned to 4KiB */ |
| 256 | const uint32_t rmask = ~((1 << 12) - 1); |
| 257 | const struct pattrs *pattrs = pattrs_get(); |
| 258 | |
| 259 | /* Initialize global tracking state. */ |
| 260 | relo_attrs.smbase = (uint32_t)smm_region_start(); |
| 261 | relo_attrs.smrr_base = relo_attrs.smbase | MTRR_TYPE_WRBACK; |
| 262 | relo_attrs.smrr_mask = ~(smm_region_size() - 1) & rmask; |
Alexandru Gagniuc | 86091f9 | 2015-09-30 20:23:09 -0700 | [diff] [blame] | 263 | relo_attrs.smrr_mask |= MTRR_PHYS_MASK_VALID; |
Aaron Durbin | 7837be6 | 2013-10-21 22:32:00 -0500 | [diff] [blame] | 264 | |
| 265 | /* Install handlers. */ |
| 266 | if (install_relocation_handler(pattrs->num_cpus) < 0) { |
| 267 | printk(BIOS_ERR, "Unable to install SMM relocation handler.\n"); |
| 268 | return -1; |
| 269 | } |
| 270 | |
| 271 | if (install_permanent_handler(pattrs->num_cpus) < 0) { |
| 272 | printk(BIOS_ERR, "Unable to install SMM permanent handler.\n"); |
| 273 | return -1; |
| 274 | } |
| 275 | |
| 276 | /* Ensure the SMM handlers hit DRAM before performing first SMI. */ |
| 277 | wbinvd(); |
| 278 | |
| 279 | return 0; |
| 280 | } |
| 281 | |
| 282 | static void smm_relocate(void *unused) |
| 283 | { |
Aaron Durbin | 315bb30 | 2013-10-24 14:55:42 -0500 | [diff] [blame] | 284 | const struct pattrs *pattrs = pattrs_get(); |
| 285 | |
Aaron Durbin | 7837be6 | 2013-10-21 22:32:00 -0500 | [diff] [blame] | 286 | /* Load relocation and permanent handler. */ |
| 287 | if (boot_cpu()) { |
| 288 | if (smm_load_handlers() < 0) { |
| 289 | printk(BIOS_ERR, "Error loading SMM handlers.\n"); |
| 290 | return; |
| 291 | } |
| 292 | southcluster_smm_clear_state(); |
| 293 | } |
| 294 | |
| 295 | /* Relocate SMM space. */ |
| 296 | smm_initiate_relocation(); |
| 297 | |
| 298 | /* Load microcode after SMM relocation. */ |
Aaron Durbin | 315bb30 | 2013-10-24 14:55:42 -0500 | [diff] [blame] | 299 | intel_microcode_load_unlocked(pattrs->microcode_patch); |
Aaron Durbin | 7837be6 | 2013-10-21 22:32:00 -0500 | [diff] [blame] | 300 | } |
| 301 | |
| 302 | static void enable_smis(void *unused) |
| 303 | { |
| 304 | southcluster_smm_enable_smi(); |
| 305 | } |