Alexandru Gagniuc | 7d31e7c | 2013-06-08 11:49:10 -0500 | [diff] [blame] | 1 | /* |
| 2 | * This file is part of the coreboot project. |
| 3 | * |
| 4 | * Copyright (C) 2011-2012 Alexandru Gagniuc <mr.nuke.me@gmail.com> |
| 5 | * |
| 6 | * This program is free software: you can redistribute it and/or modify |
| 7 | * it under the terms of the GNU General Public License as published by |
| 8 | * the Free Software Foundation, either version 2 of the License, or |
| 9 | * (at your option) any later version. |
| 10 | * |
| 11 | * This program is distributed in the hope that it will be useful, |
| 12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 14 | * GNU General Public License for more details. |
Alexandru Gagniuc | 7d31e7c | 2013-06-08 11:49:10 -0500 | [diff] [blame] | 15 | */ |
| 16 | |
| 17 | #include "early_vx900.h" |
| 18 | #include "raminit.h" |
| 19 | #include <arch/io.h> |
| 20 | #include <arch/io.h> |
| 21 | #include <console/console.h> |
| 22 | #include <device/pci_ids.h> |
| 23 | #include <delay.h> |
| 24 | #include <lib.h> |
| 25 | #include <string.h> |
| 26 | |
| 27 | /** |
| 28 | * @file raminit_ddr3.c |
| 29 | * |
| 30 | * \brief DDR3 initialization for VIA VX900 chipset |
| 31 | * |
| 32 | * Rather than explain the DDR3 init algorithm, it is better to focus on what |
| 33 | * works and what doesn't. Familiarity with the DDR3 spec does not hurt. |
| 34 | * |
| 35 | * 1 DIMMs and 2 DIMMs with one rank each works. |
| 36 | * 1 rank DIMM with 2 rank DIMM works, but the odd ranks are disabled. |
| 37 | * (2) 2-rank DIMMs will not work. |
| 38 | * |
| 39 | * It is not yet clear if odd ranks do not work because of faulty timing |
| 40 | * calibration, or a misconfiguration of the MCU. I have seen this with DIMMS |
| 41 | * which mirror pins on the odd rank. That could also be the issue. |
| 42 | * |
| 43 | * The capture window is not calibrated, but preset. Whether that preset is |
| 44 | * universal or frequency dependent, and whether it is board-specific or not is |
| 45 | * not yet clear. @see vx900_dram_calibrate_recieve_delays(). |
| 46 | * |
| 47 | * 4GBit and 8GBit modules may not work. This is untested. Modules with 11 |
| 48 | * column address bits are not tested. @see vx900_dram_map_row_col_bank() |
| 49 | * |
| 50 | * Everything else should be in a more or less usable state. FIXME s are placed |
| 51 | * all over as a reminder that either something really needs fixing, or as a |
| 52 | * reminder to double-check. |
| 53 | */ |
| 54 | |
| 55 | /* Map BA0 <-> A17, BA1 <-> A18 */ |
| 56 | /* Map BA2 <-> A19, RA0/RA1 must not overlap BA[0:2] */ |
| 57 | #define VX900_MRS_MA_MAP 0x4b33 /* MA Pin Mapping for MRS commands */ |
| 58 | #define VX900_CALIB_MA_MAP 0x5911 /* MA Pin mapping for calibrations */ |
| 59 | |
| 60 | /* |
| 61 | * Registers 0x78 -> 0x7f contain the calibration settings for DRAM IO timing |
| 62 | * The dataset in these registers is selected from 0x70. |
| 63 | * Once the correct dataset is selected the delays can be altered. |
| 64 | * delay_type refers to TxDQS, TxDQ, RxDQS, or RxCR |
| 65 | * bound refers to either manual, average, upper bound, or lower bound |
| 66 | */ |
| 67 | #define CALIB_TxDQS 0 |
| 68 | #define CALIB_TxDQ 1 |
| 69 | #define CALIB_RxDQS 2 |
| 70 | #define CALIB_RxDQ_CR 3 |
| 71 | |
| 72 | #define CALIB_AVERAGE 0 |
| 73 | #define CALIB_LOWER 1 |
| 74 | #define CALIB_UPPER 2 |
| 75 | #define CALIB_MANUAL 4 /* We want this & 3 to overflow to 0 */ |
| 76 | |
| 77 | static void vx900_delay_calib_mode_select(u8 delay_type, u8 bound) |
| 78 | { |
| 79 | /* Which calibration setting */ |
| 80 | u8 reg8 = (delay_type & 0x03) << 2; |
| 81 | /* Upper, lower, average, or manual setting */ |
| 82 | reg8 |= (bound & 0x03); |
| 83 | pci_write_config8(MCU, 0x70, reg8); |
| 84 | } |
| 85 | |
| 86 | /* |
| 87 | * The vendor BIOS does something similar to vx900_delay_calib_mode_select(), |
| 88 | * then reads or write a byte, and repeats the process for all 8 bytes. This is |
| 89 | * annoyingly inefficient, and we can achieve the same result in a much more |
| 90 | * elegant manner. |
| 91 | */ |
| 92 | static void vx900_read_0x78_0x7f(timing_dly dly) |
| 93 | { |
| 94 | *((u32 *) (&(dly[0]))) = pci_read_config32(MCU, 0x78); |
| 95 | *((u32 *) (&(dly[4]))) = pci_read_config32(MCU, 0x7c); |
| 96 | } |
| 97 | |
| 98 | static void vx900_write_0x78_0x7f(const timing_dly dly) |
| 99 | { |
| 100 | pci_write_config32(MCU, 0x78, *((u32 *) (&(dly[0])))); |
| 101 | pci_write_config32(MCU, 0x7c, *((u32 *) (&(dly[4])))); |
| 102 | } |
| 103 | |
| 104 | static void vx900_read_delay_range(delay_range * d_range, u8 mode) |
| 105 | { |
| 106 | vx900_delay_calib_mode_select(mode, CALIB_LOWER); |
| 107 | vx900_read_0x78_0x7f(d_range->low); |
| 108 | vx900_delay_calib_mode_select(mode, CALIB_AVERAGE); |
| 109 | vx900_read_0x78_0x7f(d_range->avg); |
| 110 | vx900_delay_calib_mode_select(mode, CALIB_UPPER); |
| 111 | vx900_read_0x78_0x7f(d_range->high); |
| 112 | } |
| 113 | |
| 114 | static void dump_delay(const timing_dly dly) |
| 115 | { |
| 116 | u8 i; |
| 117 | for (i = 0; i < 8; i++) { |
| 118 | printram(" %.2x", dly[i]); |
| 119 | } |
| 120 | printram("\n"); |
| 121 | } |
| 122 | |
| 123 | static void dump_delay_range(const delay_range d_range) |
| 124 | { |
| 125 | printram("Lower limit: "); |
| 126 | dump_delay(d_range.low); |
| 127 | printram("Average: "); |
| 128 | dump_delay(d_range.avg); |
| 129 | printram("Upper limit: "); |
| 130 | dump_delay(d_range.high); |
| 131 | } |
| 132 | |
| 133 | /* |
| 134 | * These are some "safe" values that can be used for memory initialization. |
| 135 | * Some will stay untouched, and others will be overwritten later on |
| 136 | */ |
| 137 | static pci_reg8 mcu_init_config[] = { |
| 138 | {0x40, 0x01}, /* Virtual rank 0 ending address = 64M - 1 */ |
| 139 | {0x41, 0x00}, {0x42, 0x00}, {0x43, 0x00}, /* Virtual Ranks ending */ |
| 140 | {0x48, 0x00}, /* Virtual rank 0 starting address = 0 */ |
| 141 | {0x49, 0x00}, {0x4a, 0x00}, {0x4b, 0x00}, /* Virtual Ranks beginning */ |
| 142 | {0x50, 0xd8}, /* Set ranks 0-3 to 11 col bits, 16 row bits */ |
| 143 | /* Disable all virtual ranks */ |
| 144 | {0x54, 0x00}, {0x55, 0x00}, {0x56, 0x00}, {0x57, 0x00}, |
| 145 | /* Disable rank interleaving in ranks 0-3 */ |
| 146 | {0x58, 0x00}, {0x59, 0x00}, {0x5a, 0x00}, {0x5b, 0x00}, |
| 147 | {0x6c, 0xA0}, /* Memory type: DDR3, VDIMM: 1.5V, 64-bit DRAM */ |
| 148 | {0xc4, 0x80}, /* Enable 8 memory banks */ |
| 149 | {0xc6, 0x80}, /* Minimum latency from self-refresh. Bit [7] must be 1 */ |
| 150 | /* FIXME: do it here or in Final config? */ |
| 151 | {0xc8, 0x80}, /* Enable automatic triggering of short ZQ calibration */ |
| 152 | {0x99, 0xf0}, /* Power Management and Bypass Reorder Queue */ |
| 153 | /* Enable differential DQS; MODT assertion values suggested in DS */ |
| 154 | {0x9e, 0xa1}, {0x9f, 0x51}, |
| 155 | /* DQ/DQM Duty Control - Do not put any extra delays */ |
| 156 | {0xe9, 0x00}, {0xea, 0x00}, {0xeb, 0x00}, {0xec, 0x00}, |
| 157 | {0xed, 0x00}, {0xee, 0x00}, {0xef, 0x00}, |
| 158 | {0xfc, 0x00}, {0xfd, 0x00}, {0xfe, 0x00}, {0xff, 0x00}, |
| 159 | /* The following parameters we may or may not change */ |
| 160 | {0x61, 0x2e}, /* DRAMC Pipeline Control */ |
| 161 | {0x77, 0x10}, /* MDQS Output Control */ |
| 162 | |
| 163 | /* The following are parameters we'll most likely never change again */ |
| 164 | {0x60, 0xf4}, /* DRAM Pipeline Turn-Around Setting */ |
| 165 | {0x65, 0x49}, /* DRAM Arbitration Bandwidth Timer - I */ |
| 166 | {0x66, 0x80}, /* DRAM Queue / Arbitration */ |
| 167 | {0x69, 0xc6}, /* Bank Control: 8 banks, high priority refresh */ |
| 168 | {0x6a, 0xfc}, /* DRAMC Request Reorder Control */ |
| 169 | {0x6e, 0x38}, /* Burst lenght: 8, burst-chop: enable */ |
| 170 | {0x73, 0x04}, /* Close All Pages Threshold */ |
| 171 | |
| 172 | /* The following need to be dynamically asserted */ |
| 173 | /* See: check_special_registers.c */ |
| 174 | {0x74, 0xa0}, /* Yes, same 0x74; add one more T */ |
| 175 | {0x76, 0x60}, /* Write Data Phase Control */ |
| 176 | |
| 177 | }; |
| 178 | |
| 179 | /* |
| 180 | * This table keeps the driving strength control setting that we can safely use |
| 181 | * during initialization. This settings come in part from SerialICE, and in part |
| 182 | * from code provided by VIA. |
| 183 | */ |
| 184 | static pci_reg8 mcu_drv_ctrl_config[] = { |
| 185 | {0xd3, 0x03}, /* Enable auto-compensation circuit for ODT strength */ |
| 186 | {0xd4, 0x80}, /* Set internal ODT to dynamically turn on or off */ |
| 187 | {0xd6, 0x20}, /* Enable strong driving for MA and DRAM commands */ |
| 188 | {0xd0, 0x88}, /* (ODT) Strength ?has effect? */ |
| 189 | {0xe0, 0x88}, /* DRAM Driving – Group DQS (MDQS) */ |
| 190 | {0xe1, 0x00}, /* Disable offset mode for driving strength control */ |
| 191 | {0xe2, 0x88}, /* DRAM Driving – Group DQ (MD, MDQM) */ |
| 192 | {0xe4, 0xcc}, /* DRAM Driving – Group CSA (MCS, MCKE, MODT) */ |
| 193 | {0xe8, 0x88}, /* DRAM Driving – Group MA (MA, MBA, MSRAS, MSCAS, MSWE) */ |
| 194 | {0xe6, 0xff}, /* DRAM Driving – Group DCLK0 (DCLK[2:0] for DIMM0) */ |
| 195 | {0xe7, 0xff}, /* DRAM Driving – Group DCLK1 (DCLK[5:3] for DIMM1) */ |
| 196 | {0xe4, 0xcc}, /* DRAM Driving – Group CSA (MCS, MCKE, MODT) */ |
| 197 | {0x91, 0x08}, /* MCLKO Output Phase Delay - I */ |
| 198 | {0x92, 0x08}, /* MCLKO Output Phase Delay - II */ |
| 199 | {0x93, 0x16}, /* CS/CKE Output Phase Delay */ |
| 200 | {0x95, 0x16}, /* SCMD/MA Output Phase Delay */ |
| 201 | {0x9b, 0x3f}, /* Memory Clock Output Enable */ |
| 202 | }; |
| 203 | |
| 204 | static void vx900_dram_set_ma_pin_map(u16 map) |
| 205 | { |
| 206 | pci_write_config16(MCU, 0x52, map); |
| 207 | } |
| 208 | |
| 209 | /* |
| 210 | * FIXME: This function is a complete waste of space. All we really need is a |
| 211 | * MA MAP table based on either row address bits or column address bits. |
| 212 | * The problem is, I do not know if this mapping is applied during the column |
| 213 | * access or during the row access. At least the religiously verbose output |
| 214 | * makes pretty console output. |
| 215 | */ |
| 216 | static void vx900_dram_map_pins(u8 ba0, u8 ba1, u8 ba2, u8 ra0, u8 ra1) |
| 217 | { |
| 218 | u16 map = 0; |
| 219 | |
| 220 | printram("Mapping address pins to DRAM pins:\n"); |
| 221 | printram(" BA0 -> A%u\n", ba0); |
| 222 | printram(" BA1 -> A%u\n", ba1); |
| 223 | printram(" BA2 -> A%u\n", ba2); |
| 224 | printram(" RA0 -> A%u\n", ra0); |
| 225 | printram(" RA1 -> A%u\n", ra1); |
| 226 | /* Make sure BA2 is enabled */ |
| 227 | map |= (1 << 11); |
| 228 | |
| 229 | /* |
| 230 | * Find RA1 (15:14) |
| 231 | * 00: A14 |
| 232 | * 01: A16 |
| 233 | * 10: A18 |
| 234 | * 11: A20 |
| 235 | */ |
| 236 | if ((ra1 & 0x01) || (ra1 < 14) || (ra1 > 20)) { |
| 237 | printram("Illegal mapping RA1 -> A%u\n", ra1); |
| 238 | return; |
| 239 | } |
| 240 | map |= (((ra1 - 14) >> 1) & 0x03) << 14; |
| 241 | |
| 242 | /* |
| 243 | * Find RA0 (13:12) |
| 244 | * 00: A15 |
| 245 | * 01: A17 |
| 246 | * 10: A19 |
| 247 | * 11: A21 |
| 248 | */ |
| 249 | if ((!(ra0 & 0x01)) || (ra0 < 15) || (ra0 > 21)) { |
| 250 | printram("Illegal mapping RA0 -> A%u\n", ra0); |
| 251 | return; |
| 252 | } |
| 253 | map |= (((ra0 - 15) >> 1) & 0x03) << 12; |
| 254 | |
| 255 | /* |
| 256 | * Find BA2 (10:8) |
| 257 | * x00: A14 |
| 258 | * x01: A15 |
| 259 | * x10: A18 |
| 260 | * x11: A19 |
| 261 | */ |
| 262 | switch (ba2) { |
| 263 | case 14: |
| 264 | map |= (0 << 8); |
| 265 | break; |
| 266 | case 15: |
| 267 | map |= (1 << 8); |
| 268 | break; |
| 269 | case 18: |
| 270 | map |= (2 << 8); |
| 271 | break; |
| 272 | case 19: |
| 273 | map |= (3 << 8); |
| 274 | break; |
| 275 | default: |
| 276 | printram("Illegal mapping BA2 -> A%u\n", ba2); |
| 277 | break; |
| 278 | } |
| 279 | |
| 280 | /* |
| 281 | * Find BA1 (6:4) |
| 282 | * 000: A12 |
| 283 | * 001: A14 |
| 284 | * 010: A16 |
| 285 | * 011: A18 |
| 286 | * 1xx: A20 |
| 287 | */ |
| 288 | if (((ba1 & 0x01)) || (ba1 < 12) || (ba1 > 20)) { |
| 289 | printram("Illegal mapping BA1 -> A%u\n", ba1); |
| 290 | return; |
| 291 | } |
| 292 | map |= (((ba1 - 12) >> 1) & 0x07) << 4; |
| 293 | |
| 294 | /* |
| 295 | * Find BA0 (2:0) |
| 296 | * 000: A11 |
| 297 | * 001: A13 |
| 298 | * 010: A15 |
| 299 | * 011: A17 |
| 300 | * 1xx: A19 |
| 301 | */ |
| 302 | if ((!(ba0 & 0x01)) || (ba0 < 11) || (ba0 > 19)) { |
| 303 | printram("Illegal mapping BA0 -> A%u\n", ba0); |
| 304 | return; |
| 305 | } |
| 306 | map |= (((ba0 - 11) >> 1) & 0x07) << 0; |
| 307 | |
| 308 | printram("Setting map mask (rx52) to %.4x\n", map); |
| 309 | vx900_dram_set_ma_pin_map(map); |
| 310 | } |
| 311 | |
| 312 | static void vx900_dram_write_init_config(void) |
| 313 | { |
| 314 | /* Keep our RAM space free of legacy stuff */ |
| 315 | vx900_disable_legacy_rom_shadow(); |
| 316 | |
| 317 | /* Now worry about the real RAM init */ |
| 318 | size_t i; |
| 319 | for (i = 0; i < (sizeof(mcu_init_config) / sizeof(pci_reg8)); i++) { |
| 320 | pci_write_config8(MCU, mcu_init_config[i].addr, |
| 321 | mcu_init_config[i].val); |
| 322 | } |
| 323 | vx900_dram_set_ma_pin_map(VX900_CALIB_MA_MAP); |
| 324 | |
| 325 | /* FIXME: Slowing stuff down. Does this really help? */ |
| 326 | |
| 327 | /* Fast cycle control for CPU-to-DRAM Read Cycle 0:Disabled. |
| 328 | * This CPU bus controller will wait for all data */ |
| 329 | ////pci_mod_config8(HOST_BUS, 0x51, (1 << 7), 0); |
| 330 | /* Memory to CPU bus Controller Conversion Mode 1: Synchronous mode */ |
| 331 | ////pci_mod_config8(HOST_BUS, 0x54, 0, (1 << 1)); |
| 332 | } |
| 333 | |
| 334 | static void dram_find_spds_ddr3(const dimm_layout * addr, dimm_info * dimm) |
| 335 | { |
| 336 | size_t i = 0; |
| 337 | int dimms = 0; |
| 338 | do { |
| 339 | spd_raw_data spd; |
| 340 | spd_read(addr->spd_addr[i], spd); |
| 341 | spd_decode_ddr3(&dimm->dimm[i], spd); |
| 342 | if (dimm->dimm[i].dram_type != SPD_MEMORY_TYPE_SDRAM_DDR3) |
| 343 | continue; |
| 344 | dimms++; |
| 345 | dram_print_spd_ddr3(&dimm->dimm[i]); |
| 346 | } while (addr->spd_addr[++i] != SPD_END_LIST |
| 347 | && i < VX900_MAX_DIMM_SLOTS); |
| 348 | |
| 349 | if (!dimms) |
| 350 | die("No DIMMs were found"); |
| 351 | } |
| 352 | |
| 353 | static void dram_find_common_params(const dimm_info * dimms, |
| 354 | ramctr_timing * ctrl) |
| 355 | { |
| 356 | size_t i, valid_dimms; |
| 357 | memset(ctrl, 0, sizeof(ramctr_timing)); |
| 358 | ctrl->cas_supported = 0xff; |
| 359 | valid_dimms = 0; |
| 360 | for (i = 0; i < VX900_MAX_DIMM_SLOTS; i++) { |
| 361 | const dimm_attr *dimm = &dimms->dimm[i]; |
| 362 | if (dimm->dram_type == SPD_MEMORY_TYPE_UNDEFINED) |
| 363 | continue; |
| 364 | valid_dimms++; |
| 365 | |
| 366 | if (valid_dimms == 1) { |
| 367 | /* First DIMM defines the type of DIMM */ |
| 368 | ctrl->dram_type = dimm->dram_type; |
Vladimir Serbinenko | daf7680 | 2014-12-07 13:58:15 +0100 | [diff] [blame] | 369 | ctrl->dimm_type = dimm->dimm_type; |
Alexandru Gagniuc | 7d31e7c | 2013-06-08 11:49:10 -0500 | [diff] [blame] | 370 | } else { |
| 371 | /* Check if we have mismatched DIMMs */ |
Vladimir Serbinenko | daf7680 | 2014-12-07 13:58:15 +0100 | [diff] [blame] | 372 | if (ctrl->dram_type != dimm->dram_type |
| 373 | || ctrl->dimm_type != dimm->dimm_type) |
Alexandru Gagniuc | 7d31e7c | 2013-06-08 11:49:10 -0500 | [diff] [blame] | 374 | die("Mismatched DIMM Types"); |
| 375 | } |
| 376 | /* Find all possible CAS combinations */ |
| 377 | ctrl->cas_supported &= dimm->cas_supported; |
| 378 | |
| 379 | /* Find the smallest common latencies supported by all DIMMs */ |
Alexandru Gagniuc | 560433b | 2013-06-10 15:47:25 -0500 | [diff] [blame] | 380 | ctrl->tCK = MAX(ctrl->tCK, dimm->tCK); |
| 381 | ctrl->tAA = MAX(ctrl->tAA, dimm->tAA); |
| 382 | ctrl->tWR = MAX(ctrl->tWR, dimm->tWR); |
| 383 | ctrl->tRCD = MAX(ctrl->tRCD, dimm->tRCD); |
| 384 | ctrl->tRRD = MAX(ctrl->tRRD, dimm->tRRD); |
| 385 | ctrl->tRP = MAX(ctrl->tRP, dimm->tRP); |
| 386 | ctrl->tRAS = MAX(ctrl->tRAS, dimm->tRAS); |
| 387 | ctrl->tRC = MAX(ctrl->tRC, dimm->tRC); |
| 388 | ctrl->tRFC = MAX(ctrl->tRFC, dimm->tRFC); |
| 389 | ctrl->tWTR = MAX(ctrl->tWTR, dimm->tWTR); |
| 390 | ctrl->tRTP = MAX(ctrl->tRTP, dimm->tRTP); |
| 391 | ctrl->tFAW = MAX(ctrl->tFAW, dimm->tFAW); |
Alexandru Gagniuc | 7d31e7c | 2013-06-08 11:49:10 -0500 | [diff] [blame] | 392 | |
| 393 | } |
| 394 | |
| 395 | ctrl->n_dimms = valid_dimms; |
| 396 | if (!ctrl->cas_supported) |
| 397 | die("Unsupported DIMM combination. " |
| 398 | "DIMMS do not support common CAS latency"); |
| 399 | if (!valid_dimms) |
| 400 | die("No valid DIMMs found"); |
| 401 | } |
| 402 | |
| 403 | static void vx900_dram_phys_bank_range(const dimm_info * dimms, |
| 404 | rank_layout * ranks) |
| 405 | { |
| 406 | size_t i; |
| 407 | for (i = 0; i < VX900_MAX_DIMM_SLOTS; i++) { |
| 408 | if (dimms->dimm[i].dram_type == SPD_MEMORY_TYPE_UNDEFINED) |
| 409 | continue; |
| 410 | u8 nranks = dimms->dimm[i].ranks; |
| 411 | /* Make sure we save the flags */ |
| 412 | ranks->flags[i * 2 + 1] = ranks->flags[i * 2] = |
| 413 | dimms->dimm[i].flags; |
| 414 | /* Only Rank1 has a mirrored pin mapping */ |
| 415 | ranks->flags[i * 2].pins_mirrored = 0; |
| 416 | if (nranks > 2) |
| 417 | die("Found DIMM with more than two ranks, which is not " |
| 418 | "supported by this chipset"); |
| 419 | u32 size = dimms->dimm[i].size_mb; |
| 420 | if (nranks == 2) { |
| 421 | /* Each rank holds half the capacity of the DIMM */ |
| 422 | size >>= 1; |
| 423 | ranks->phys_rank_size_mb[i << 1] = size; |
| 424 | ranks->phys_rank_size_mb[(i << 1) | 1] = size; |
| 425 | } else { |
| 426 | /* Otherwise, everything is held in the first bank */ |
| 427 | ranks->phys_rank_size_mb[i << 1] = size; |
Idwer Vollering | d26da9c | 2013-12-22 21:38:18 +0000 | [diff] [blame] | 428 | ranks->phys_rank_size_mb[(i << 1) | 1] = 0; |
Alexandru Gagniuc | 7d31e7c | 2013-06-08 11:49:10 -0500 | [diff] [blame] | 429 | } |
| 430 | } |
| 431 | } |
| 432 | |
| 433 | #define ODT_R0 0 |
| 434 | #define ODT_R1 1 |
| 435 | #define ODT_R2 2 |
| 436 | #define ODT_R3 3 |
| 437 | /* |
| 438 | * This is the table that tells us which MODT pin to map to which rank. |
| 439 | * |
| 440 | * This table is taken from code provided by VIA, but no explanation was |
| 441 | * provided as to why it is done this way. It may be possible that this table is |
| 442 | * not suitable for the way we map ranks later on. |
| 443 | */ |
| 444 | static const u8 odt_lookup_table[][2] = { |
| 445 | /* RankMAP Rank 3 Rank 2 Rank 1 Rank 0 */ |
| 446 | {0x01, (ODT_R3 << 6) | (ODT_R2 << 4) | (ODT_R1 << 2) | (ODT_R0 << 0)}, |
| 447 | {0x03, (ODT_R3 << 6) | (ODT_R2 << 4) | (ODT_R0 << 2) | (ODT_R1 << 0)}, |
| 448 | {0x04, (ODT_R3 << 6) | (ODT_R2 << 4) | (ODT_R1 << 2) | (ODT_R0 << 0)}, |
| 449 | {0x05, (ODT_R3 << 6) | (ODT_R0 << 4) | (ODT_R1 << 2) | (ODT_R2 << 0)}, |
| 450 | {0x07, (ODT_R3 << 6) | (ODT_R0 << 4) | (ODT_R2 << 2) | (ODT_R2 << 0)}, |
| 451 | {0x0c, (ODT_R2 << 6) | (ODT_R3 << 4) | (ODT_R1 << 2) | (ODT_R0 << 0)}, |
| 452 | {0x0d, (ODT_R0 << 6) | (ODT_R0 << 4) | (ODT_R1 << 2) | (ODT_R2 << 0)}, |
| 453 | {0x0f, (ODT_R0 << 6) | (ODT_R0 << 4) | (ODT_R2 << 2) | (ODT_R2 << 0)}, |
| 454 | {0, 0}, |
| 455 | }; |
| 456 | |
| 457 | static void vx900_dram_driving_ctrl(const dimm_info * dimm) |
| 458 | { |
| 459 | size_t i, ndimms; |
| 460 | u8 reg8, regxd5, rank_mask; |
| 461 | |
| 462 | rank_mask = 0; |
| 463 | /* For ODT range selection, datasheet recommends |
| 464 | * when 1 DIMM present: 60 Ohm |
| 465 | * when 2 DIMMs present: 120 Ohm */ |
| 466 | ndimms = 0; |
| 467 | for (i = 0; i < VX900_MAX_DIMM_SLOTS; i++) { |
| 468 | if (dimm->dimm[i].dram_type != SPD_MEMORY_TYPE_SDRAM_DDR3) |
| 469 | continue; |
| 470 | ndimms++; |
| 471 | rank_mask |= (1 << (i * 2)); |
| 472 | if (dimm->dimm[i].ranks > 1) |
| 473 | rank_mask |= (2 << (i * 2)); |
| 474 | } |
| 475 | /* ODT strength and MD/MDQM/MDQS driving strength */ |
| 476 | if (ndimms > 1) { |
| 477 | /* Enable 1 ODT block (120 Ohm ODT) */ |
| 478 | regxd5 = 0 << 2; |
| 479 | /* Enable strong driving for MD/MDQM/MDQS */ |
| 480 | regxd5 |= (1 << 7); |
| 481 | } else { |
| 482 | /* Enable 2 ODT blocks (60 Ohm ODT) */ |
| 483 | regxd5 = 1 << 2; |
| 484 | /* Leave MD/MDQM/MDQS driving weak */ |
| 485 | } |
| 486 | pci_write_config8(MCU, 0xd5, regxd5); |
| 487 | |
| 488 | /* Enable strong CLK driving for DIMMs with more than one rank */ |
| 489 | if (dimm->dimm[0].ranks > 1) |
| 490 | pci_mod_config8(MCU, 0xd6, 0, (1 << 7)); |
| 491 | if (dimm->dimm[1].ranks > 1) |
| 492 | pci_mod_config8(MCU, 0xd6, 0, (1 << 6)); |
| 493 | |
| 494 | /* DRAM ODT Lookup Table */ |
| 495 | for (i = 0;; i++) { |
| 496 | if (odt_lookup_table[i][0] == 0) { |
| 497 | printram("No ODT entry for rank mask %x\n", rank_mask); |
| 498 | die("Aborting"); |
| 499 | } |
| 500 | if (odt_lookup_table[i][0] != rank_mask) |
| 501 | continue; |
| 502 | |
| 503 | reg8 = odt_lookup_table[i][1]; |
| 504 | break; |
| 505 | } |
| 506 | |
| 507 | printram("Mapping rank mask %x to ODT entry %.2x\n", rank_mask, reg8); |
| 508 | pci_write_config8(MCU, 0x9c, reg8); |
| 509 | |
| 510 | for (i = 0; i < (sizeof(mcu_drv_ctrl_config) / sizeof(pci_reg8)); i++) { |
| 511 | pci_write_config8(MCU, mcu_drv_ctrl_config[i].addr, |
| 512 | mcu_drv_ctrl_config[i].val); |
| 513 | } |
| 514 | } |
| 515 | |
| 516 | static void vx900_pr_map_all_vr3(void) |
| 517 | { |
| 518 | /* Enable all ranks and set them to VR3 */ |
| 519 | pci_write_config16(MCU, 0x54, 0xbbbb); |
| 520 | } |
| 521 | |
| 522 | /* Map physical rank pr to virtual rank vr */ |
| 523 | static void vx900_map_pr_vr(u8 pr, u8 vr) |
| 524 | { |
| 525 | u16 val; |
| 526 | |
| 527 | pr &= 0x3; |
| 528 | vr &= 0x3; |
| 529 | /* Enable rank (bit [3], and set the VR number bits [1:0] */ |
| 530 | val = 0x8 | vr; |
| 531 | /* Now move the value to the appropriate PR */ |
| 532 | val <<= (pr * 4); |
| 533 | pci_mod_config16(MCU, 0x54, 0xf << (pr * 4), val); |
| 534 | printram("Mapping PR %u to VR %u\n", pr, vr); |
| 535 | } |
| 536 | |
| 537 | static u8 vx900_get_CWL(u8 CAS) |
| 538 | { |
| 539 | /* Get CWL based on CAS using the following rule: |
| 540 | * _________________________________________ |
| 541 | * CAS: | 4T | 5T | 6T | 7T | 8T | 9T | 10T | 11T | |
| 542 | * CWL: | 5T | 5T | 5T | 6T | 6T | 7T | 7T | 8T | |
| 543 | */ |
| 544 | static const u8 cas_cwl_map[] = { 5, 5, 5, 6, 6, 7, 7, 8 }; |
| 545 | if (CAS > 11) |
| 546 | return 8; |
| 547 | return cas_cwl_map[CAS - 4]; |
| 548 | } |
| 549 | |
| 550 | /* |
| 551 | * Here we are calculating latencies, and writing them to the appropriate |
| 552 | * registers. Note that some registers do not take latencies from 0 = 0T, |
| 553 | * 1 = 1T, so each register gets its own math formula. |
| 554 | */ |
| 555 | static void vx900_dram_timing(ramctr_timing * ctrl) |
| 556 | { |
| 557 | u8 reg8, val, tFAW, tRRD; |
| 558 | u32 val32; |
| 559 | |
| 560 | /* Maximum supported DDR3 frequency is 533MHz (DDR3 1066) so make sure |
| 561 | * we cap it if we have faster DIMMs. |
| 562 | * Then, align it to the closest JEDEC standard frequency */ |
| 563 | if (ctrl->tCK <= TCK_533MHZ) { |
| 564 | ctrl->tCK = TCK_533MHZ; |
| 565 | } else if (ctrl->tCK <= TCK_400MHZ) { |
| 566 | ctrl->tCK = TCK_400MHZ; |
| 567 | } else if (ctrl->tCK <= TCK_333MHZ) { |
| 568 | ctrl->tCK = TCK_333MHZ; |
| 569 | } else { |
| 570 | ctrl->tCK = TCK_266MHZ; |
| 571 | } |
| 572 | |
| 573 | val32 = (1000 << 8) / ctrl->tCK; |
| 574 | printram("Selected DRAM frequency: %u MHz\n", val32); |
| 575 | |
| 576 | /* Find CAS and CWL latencies */ |
Edward O'Callaghan | 7116ac8 | 2014-07-08 01:53:24 +1000 | [diff] [blame] | 577 | val = CEIL_DIV(ctrl->tAA, ctrl->tCK); |
Alexandru Gagniuc | 7d31e7c | 2013-06-08 11:49:10 -0500 | [diff] [blame] | 578 | printram("Minimum CAS latency : %uT\n", val); |
| 579 | /* Find lowest supported CAS latency that satisfies the minimum value */ |
| 580 | while (!((ctrl->cas_supported >> (val - 4)) & 1) |
| 581 | && (ctrl->cas_supported >> (val - 4))) { |
| 582 | val++; |
| 583 | } |
| 584 | /* Is CAS supported */ |
| 585 | if (!(ctrl->cas_supported & (1 << (val - 4)))) |
| 586 | printram("CAS not supported\n"); |
| 587 | printram("Selected CAS latency : %uT\n", val); |
| 588 | ctrl->CAS = val; |
| 589 | ctrl->CWL = vx900_get_CWL(ctrl->CAS); |
| 590 | printram("Selected CWL latency : %uT\n", ctrl->CWL); |
| 591 | /* Write CAS and CWL */ |
| 592 | reg8 = (((ctrl->CWL - 4) & 0x07) << 4) | ((ctrl->CAS - 4) & 0x07); |
| 593 | pci_write_config8(MCU, 0xc0, reg8); |
| 594 | |
| 595 | /* Find tRCD */ |
Edward O'Callaghan | 7116ac8 | 2014-07-08 01:53:24 +1000 | [diff] [blame] | 596 | val = CEIL_DIV(ctrl->tRCD, ctrl->tCK); |
Alexandru Gagniuc | 7d31e7c | 2013-06-08 11:49:10 -0500 | [diff] [blame] | 597 | printram("Selected tRCD : %uT\n", val); |
| 598 | reg8 = ((val - 4) & 0x7) << 4; |
| 599 | /* Find tRP */ |
Edward O'Callaghan | 7116ac8 | 2014-07-08 01:53:24 +1000 | [diff] [blame] | 600 | val = CEIL_DIV(ctrl->tRP, ctrl->tCK); |
Alexandru Gagniuc | 7d31e7c | 2013-06-08 11:49:10 -0500 | [diff] [blame] | 601 | printram("Selected tRP : %uT\n", val); |
| 602 | reg8 |= ((val - 4) & 0x7); |
| 603 | pci_write_config8(MCU, 0xc1, reg8); |
| 604 | |
| 605 | /* Find tRAS */ |
Edward O'Callaghan | 7116ac8 | 2014-07-08 01:53:24 +1000 | [diff] [blame] | 606 | val = CEIL_DIV(ctrl->tRAS, ctrl->tCK); |
Alexandru Gagniuc | 7d31e7c | 2013-06-08 11:49:10 -0500 | [diff] [blame] | 607 | printram("Selected tRAS : %uT\n", val); |
| 608 | reg8 = ((val - 15) & 0x7) << 4; |
| 609 | /* Find tWR */ |
Edward O'Callaghan | 7116ac8 | 2014-07-08 01:53:24 +1000 | [diff] [blame] | 610 | ctrl->WR = CEIL_DIV(ctrl->tWR, ctrl->tCK); |
Alexandru Gagniuc | 7d31e7c | 2013-06-08 11:49:10 -0500 | [diff] [blame] | 611 | printram("Selected tWR : %uT\n", ctrl->WR); |
| 612 | reg8 |= ((ctrl->WR - 4) & 0x7); |
| 613 | pci_write_config8(MCU, 0xc2, reg8); |
| 614 | |
| 615 | /* Find tFAW */ |
Edward O'Callaghan | 7116ac8 | 2014-07-08 01:53:24 +1000 | [diff] [blame] | 616 | tFAW = CEIL_DIV(ctrl->tFAW, ctrl->tCK); |
Alexandru Gagniuc | 7d31e7c | 2013-06-08 11:49:10 -0500 | [diff] [blame] | 617 | printram("Selected tFAW : %uT\n", tFAW); |
| 618 | /* Find tRRD */ |
Edward O'Callaghan | 7116ac8 | 2014-07-08 01:53:24 +1000 | [diff] [blame] | 619 | tRRD = CEIL_DIV(ctrl->tRRD, ctrl->tCK); |
Alexandru Gagniuc | 7d31e7c | 2013-06-08 11:49:10 -0500 | [diff] [blame] | 620 | printram("Selected tRRD : %uT\n", tRRD); |
| 621 | val = tFAW - 4 * tRRD; /* number of cycles above 4*tRRD */ |
| 622 | reg8 = ((val - 0) & 0x7) << 4; |
| 623 | reg8 |= ((tRRD - 2) & 0x7); |
| 624 | pci_write_config8(MCU, 0xc3, reg8); |
| 625 | |
| 626 | /* Find tRTP */ |
Edward O'Callaghan | 7116ac8 | 2014-07-08 01:53:24 +1000 | [diff] [blame] | 627 | val = CEIL_DIV(ctrl->tRTP, ctrl->tCK); |
Alexandru Gagniuc | 7d31e7c | 2013-06-08 11:49:10 -0500 | [diff] [blame] | 628 | printram("Selected tRTP : %uT\n", val); |
| 629 | reg8 = ((val & 0x3) << 4); |
| 630 | /* Find tWTR */ |
Edward O'Callaghan | 7116ac8 | 2014-07-08 01:53:24 +1000 | [diff] [blame] | 631 | val = CEIL_DIV(ctrl->tWTR, ctrl->tCK); |
Alexandru Gagniuc | 7d31e7c | 2013-06-08 11:49:10 -0500 | [diff] [blame] | 632 | printram("Selected tWTR : %uT\n", val); |
| 633 | reg8 |= ((val - 2) & 0x7); |
| 634 | pci_mod_config8(MCU, 0xc4, 0x3f, reg8); |
| 635 | |
| 636 | /* DRAM Timing for All Ranks - VI |
| 637 | * [7:6] CKE Assertion Minimum Pulse Width |
| 638 | * We probably don't want to mess with this just yet. |
| 639 | * [5:0] Refresh-to-Active or Refresh-to-Refresh (tRFC) |
| 640 | * tRFC = (30 + 2 * [5:0])T |
| 641 | * Since we previously set RxC4[7] |
| 642 | */ |
| 643 | reg8 = pci_read_config8(MCU, 0xc5); |
Edward O'Callaghan | 7116ac8 | 2014-07-08 01:53:24 +1000 | [diff] [blame] | 644 | val = CEIL_DIV(ctrl->tRFC, ctrl->tCK); |
Alexandru Gagniuc | 7d31e7c | 2013-06-08 11:49:10 -0500 | [diff] [blame] | 645 | printram("Minimum tRFC : %uT\n", val); |
| 646 | if (val < 30) { |
| 647 | val = 0; |
| 648 | } else { |
| 649 | val = (val - 30 + 1) / 2; |
| 650 | } |
| 651 | ; |
| 652 | printram("Selected tRFC : %uT\n", 30 + 2 * val); |
| 653 | reg8 |= (val & 0x3f); |
| 654 | pci_write_config8(MCU, 0xc5, reg8); |
| 655 | |
| 656 | /* Where does this go??? */ |
Edward O'Callaghan | 7116ac8 | 2014-07-08 01:53:24 +1000 | [diff] [blame] | 657 | val = CEIL_DIV(ctrl->tRC, ctrl->tCK); |
Alexandru Gagniuc | 7d31e7c | 2013-06-08 11:49:10 -0500 | [diff] [blame] | 658 | printram("Required tRC : %uT\n", val); |
| 659 | } |
| 660 | |
| 661 | /* Program the DRAM frequency */ |
| 662 | static void vx900_dram_freq(ramctr_timing * ctrl) |
| 663 | { |
| 664 | u8 val; |
| 665 | |
| 666 | /* Step 1 - Reset the PLL */ |
| 667 | pci_mod_config8(MCU, 0x90, 0x00, 0x0f); |
| 668 | /* Wait at least 10 ns; VIA code delays by 640us */ |
| 669 | udelay(640); |
| 670 | |
| 671 | /* Step 2 - Set target frequency */ |
| 672 | if (ctrl->tCK <= TCK_533MHZ) { |
| 673 | val = 0x07; |
| 674 | ctrl->tCK = TCK_533MHZ; |
| 675 | } else if (ctrl->tCK <= TCK_400MHZ) { |
| 676 | val = 0x06; |
| 677 | ctrl->tCK = TCK_400MHZ; |
| 678 | } else if (ctrl->tCK <= TCK_333MHZ) { |
| 679 | val = 0x05; |
| 680 | ctrl->tCK = TCK_333MHZ; |
| 681 | } else { /*ctrl->tCK <= TCK_266MHZ */ |
| 682 | val = 0x04; |
| 683 | ctrl->tCK = TCK_266MHZ; |
| 684 | } |
| 685 | /* Restart the PLL with the desired frequency */ |
| 686 | pci_mod_config8(MCU, 0x90, 0x0f, val); |
| 687 | |
| 688 | /* Step 3 - Wait for PLL to stabilize */ |
| 689 | udelay(2000); |
| 690 | |
| 691 | /* Step 4 - Reset the DLL - Clear [7,4] */ |
| 692 | pci_mod_config8(MCU, 0x6b, 0x90, 0x00); |
| 693 | udelay(2000); |
| 694 | |
| 695 | /* Step 5 - Enable the DLL - Set bits [7,4] to 01b */ |
| 696 | pci_mod_config8(MCU, 0x6b, 0x00, 0x10); |
| 697 | udelay(2000); |
| 698 | |
| 699 | /* Step 6 - Start DLL Calibration - Set bit [7] */ |
| 700 | pci_mod_config8(MCU, 0x6b, 0x00, 0x80); |
| 701 | udelay(5); |
| 702 | |
| 703 | /* Step 7 - Finish DLL Calibration - Clear bit [7] */ |
| 704 | pci_mod_config8(MCU, 0x6b, 0x80, 0x00); |
| 705 | |
| 706 | /* Step 8 - If we have registered DIMMs, we need to set bit[0] */ |
Vladimir Serbinenko | daf7680 | 2014-12-07 13:58:15 +0100 | [diff] [blame] | 707 | if (dimm_is_registered(ctrl->dimm_type)) { |
Alexandru Gagniuc | 7d31e7c | 2013-06-08 11:49:10 -0500 | [diff] [blame] | 708 | printram("Enabling RDIMM support in memory controller\n"); |
| 709 | pci_mod_config8(MCU, 0x6c, 0x00, 0x01); |
| 710 | } |
| 711 | } |
| 712 | |
| 713 | /* |
| 714 | * The VX900 can send the MRS commands directly through hardware |
| 715 | * It does the MR2->MR3->MR1->MR0->LongZQ JEDEC dance |
| 716 | * The parameters that we don't worry about are extracted from the timing |
| 717 | * registers we have programmed earlier. |
| 718 | */ |
| 719 | static void vx900_dram_ddr3_do_hw_mrs(u8 ma_swap, u8 rtt_nom, |
| 720 | u8 ods, u8 rtt_wr, u8 srt, u8 asr) |
| 721 | { |
| 722 | u16 reg16 = 0; |
| 723 | |
| 724 | printram("Using Hardware method for DRAM MRS commands.\n"); |
| 725 | |
| 726 | reg16 |= ((rtt_wr & 0x03) << 12); |
| 727 | if (srt) |
| 728 | reg16 |= (1 << 9); |
| 729 | if (asr) |
| 730 | reg16 |= (1 << 8); |
| 731 | reg16 |= ((rtt_nom & 0x7) << 4); |
| 732 | reg16 |= ((ods & 0x03) << 2); |
| 733 | if (ma_swap) |
| 734 | reg16 |= (1 << 1); |
| 735 | reg16 |= (1 << 14); |
| 736 | reg16 |= (1 << 0); /* This is the trigger bit */ |
| 737 | printram("Hw MRS set is 0x%4x\n", reg16); |
| 738 | pci_write_config16(MCU, 0xcc, reg16); |
| 739 | /* Wait for MRS commands to be sent */ |
| 740 | while (pci_read_config8(MCU, 0xcc) & 1) ; |
| 741 | } |
| 742 | |
| 743 | /* |
| 744 | * Translate the MRS command into an address on the CPU bus |
| 745 | * |
| 746 | * Take an MRS command (mrs_cmd_t) and translate it to a read address on the CPU |
| 747 | * bus. Thus, reading from the returned address, will issue the correct MRS |
| 748 | * command, assuming we are in MRS mode, of course. |
| 749 | * |
| 750 | * A read from the returned address will produce the correct MRS command |
| 751 | * provided the following conditions are met: |
| 752 | * - The MA pin mapping is set to VX900_MRS_MA_MAP |
| 753 | * - The memory controller's Fun3_RX6B[2:0] is set to 011b (MSR Enable) |
| 754 | */ |
| 755 | static u32 vx900_get_mrs_addr(mrs_cmd_t cmd) |
| 756 | { |
| 757 | u32 addr = 0; |
| 758 | u8 mrs_type = (cmd >> 16) & 0x07; |
| 759 | /* MA[9:0] <-> A[12:3] */ |
| 760 | addr |= ((cmd & 0x3ff) << 3); |
| 761 | /* MA10 <-> A20 */ |
| 762 | addr |= (((cmd >> 10) & 0x1) << 20); |
| 763 | /* MA[12:11] <-> A[14:13] */ |
| 764 | addr |= (((cmd >> 11) & 0x3) << 13); |
| 765 | /* BA[2:0] <-> A[19:17] */ |
| 766 | addr |= mrs_type << 17; |
| 767 | return addr; |
| 768 | } |
| 769 | |
| 770 | /* |
| 771 | * Here, we do the MR2->MR3->MR1->MR0->LongZQ JEDEC dance manually |
| 772 | * |
| 773 | * Why would we do this in software, when the VX900 can do it in hardware? The |
| 774 | * problem is the hardware sequence seems to be buggy on ranks with mirrored |
| 775 | * pins. Is this a hardware bug or a misconfigured MCU? No idea. |
| 776 | * |
| 777 | * To maintain API compatibility with the function that implements the hardware |
| 778 | * sequence, we don't ask for all parameters. To keep an overall cleaner code |
| 779 | * structure, we don't try to pass down all that information. Instead, we |
| 780 | * extract the extra parameters from the timing registers we have programmed |
| 781 | * earlier. |
| 782 | */ |
| 783 | static void vx900_dram_ddr3_do_sw_mrs(u8 ma_swap, enum ddr3_mr1_rtt_nom rtt_nom, |
| 784 | enum ddr3_mr1_ods ods, |
| 785 | enum ddr3_mr2_rttwr rtt_wr, |
| 786 | enum ddr3_mr2_srt_range srt, |
| 787 | enum ddr3_mr2_asr asr) |
| 788 | { |
| 789 | mrs_cmd_t mrs; |
| 790 | u8 reg8, cas, cwl, twr; |
| 791 | |
| 792 | printram("Using Software method for DRAM MRS commands.\n"); |
| 793 | |
| 794 | /* Get CAS, CWL, and tWR that we programmed earlier */ |
| 795 | reg8 = pci_read_config8(MCU, 0xc0); |
| 796 | cas = (reg8 & 0x07) + 4; |
| 797 | cwl = ((reg8 >> 4) & 0x07) + 4; |
| 798 | reg8 = pci_read_config8(MCU, 0xc2); |
| 799 | twr = (reg8 & 0x07) + 4; |
| 800 | |
| 801 | /* Step 06 - Set Fun3_RX6B[2:0] to 001b (NOP Command Enable). */ |
| 802 | /* Was already done for us before calling us */ |
| 803 | |
| 804 | /* Step 07 - Read a double word from any address of the DIMM. */ |
| 805 | /* Was already done for us before calling us */ |
| 806 | |
| 807 | /* Step 08 - Set Fun3_RX6B[2:0] to 011b (MSR Enable). */ |
| 808 | pci_mod_config8(MCU, 0x6b, 0x07, 0x03); /* MSR Enable */ |
| 809 | |
| 810 | /* Step 09 – Issue MR2 cycle. Read a double word from the address |
| 811 | * depended on DRAM’s Rtt_WR and CWL settings. */ |
| 812 | mrs = ddr3_get_mr2(rtt_wr, srt, asr, cwl); |
| 813 | if (ma_swap) |
| 814 | mrs = ddr3_mrs_mirror_pins(mrs); |
| 815 | volatile_read(vx900_get_mrs_addr(mrs)); |
| 816 | printram("MR2: %.5x\n", mrs); |
| 817 | udelay(1000); |
| 818 | |
| 819 | /* Step 10 – Issue MR3 cycle. Read a double word from the address 60000h |
| 820 | * to set DRAM to normal operation mode. */ |
| 821 | mrs = ddr3_get_mr3(0); |
| 822 | if (ma_swap) |
| 823 | mrs = ddr3_mrs_mirror_pins(mrs); |
| 824 | volatile_read(vx900_get_mrs_addr(mrs)); |
| 825 | printram("MR3: %.5x\n", mrs); |
| 826 | udelay(1000); |
| 827 | |
| 828 | /* Step 11 –Issue MR1 cycle. Read a double word from the address |
| 829 | * depended on DRAM’s output driver impedance and Rtt_Nom settings. |
| 830 | * The DLL enable field, TDQS field, write leveling enable field, |
| 831 | * additive latency field and Qoff field should be set to 0. */ |
| 832 | mrs = ddr3_get_mr1(DDR3_MR1_QOFF_ENABLE, DDR3_MR1_TQDS_DISABLE, rtt_nom, |
| 833 | DDR3_MR1_WRLVL_DISABLE, ods, DDR3_MR1_AL_DISABLE, |
| 834 | DDR3_MR1_DLL_ENABLE); |
| 835 | if (ma_swap) |
| 836 | mrs = ddr3_mrs_mirror_pins(mrs); |
| 837 | volatile_read(vx900_get_mrs_addr(mrs)); |
| 838 | printram("MR1: %.5x\n", mrs); |
| 839 | udelay(1000); |
| 840 | |
| 841 | /* Step 12 - Issue MR0 cycle. Read a double word from the address |
| 842 | * depended on DRAM’s burst length, CAS latency and write recovery time |
| 843 | * settings. |
| 844 | * The read burst type field should be set to interleave. |
| 845 | * The mode field should be set to normal mode. |
| 846 | * The DLL reset field should be set to No. |
| 847 | * The DLL control for precharge PD field should be set to Fast exit. |
| 848 | */ |
| 849 | mrs = ddr3_get_mr0(DDR3_MR0_PRECHARGE_FAST, twr, |
| 850 | DDR3_MR0_DLL_RESET_NO, DDR3_MR0_MODE_NORMAL, cas, |
| 851 | DDR3_MR0_BURST_TYPE_INTERLEAVED, |
| 852 | DDR3_MR0_BURST_LENGTH_CHOP); |
| 853 | volatile_read(vx900_get_mrs_addr(mrs)); |
| 854 | printram("MR0: %.5x\n", mrs); |
| 855 | udelay(1000); |
| 856 | |
| 857 | /* Step 13 - Set Fun3_RX6B[2:0] to 110b (Long ZQ calibration cmd) */ |
| 858 | pci_mod_config8(MCU, 0x6b, 0x07, 0x06); /* Long ZQ */ |
| 859 | /* Step 14 - Read a double word from any address of the DIMM. */ |
| 860 | volatile_read(0); |
| 861 | udelay(1000); |
| 862 | } |
| 863 | |
| 864 | /* |
| 865 | * This is where we take the DIMMs out of reset and do the JEDEC dance for each |
| 866 | * individual physical rank. |
| 867 | */ |
| 868 | static void vx900_dram_ddr3_dimm_init(const ramctr_timing * ctrl, |
| 869 | const rank_layout * ranks) |
| 870 | { |
| 871 | size_t i; |
| 872 | u8 rtt_nom, rtt_wr, ods, pinswap; |
| 873 | |
| 874 | /* Set BA[0/1/2] to [A17/18/19] */ |
| 875 | vx900_dram_set_ma_pin_map(VX900_MRS_MA_MAP); |
| 876 | |
| 877 | /* Step 01 - Set Fun3_Rx6E[5] to 1b to support burst length. */ |
| 878 | pci_mod_config8(MCU, 0x6e, 0, 1 << 5); |
| 879 | /* Step 02 - Set Fun3_RX69[0] to 0b (Disable Multiple Page Mode). */ |
| 880 | pci_mod_config8(MCU, 0x69, (1 << 0), 0x00); |
| 881 | /* And set [7:6] to 10b ? */ |
| 882 | pci_write_config8(MCU, 0x69, 0x87); |
| 883 | |
| 884 | /* Step 03 - Set the target physical rank to virtual rank0 and other |
| 885 | * ranks to virtual rank3. */ |
| 886 | vx900_pr_map_all_vr3(); |
| 887 | |
| 888 | /* Step 04 - Set Fun3_Rx50 to D8h. */ |
| 889 | pci_write_config8(MCU, 0x50, 0xd8); |
| 890 | /* Step 05 - Set Fun3_RX6B[5] to 1b to de-assert RESET# and wait for at |
| 891 | * least 500 us. */ |
| 892 | pci_mod_config8(MCU, 0x6b, 0x00, (1 << 5)); |
| 893 | udelay(500); |
| 894 | |
| 895 | /* Step 6 -> 15 - Set the target physical rank to virtual rank 0 and |
| 896 | * other ranks to virtual rank 3. |
| 897 | * Repeat Step 6 to 14 for every rank present, then jump to Step 16. */ |
| 898 | for (i = 0; i < VX900_MAX_MEM_RANKS; i++) { |
| 899 | if (ranks->phys_rank_size_mb[i] == 0) |
| 900 | continue; |
| 901 | printram("Initializing rank %lu\n", i); |
| 902 | |
| 903 | /* Set target physical rank to virtual rank 0 |
| 904 | * other ranks to virtual rank 3*/ |
| 905 | vx900_map_pr_vr(i, 0); |
| 906 | |
| 907 | /* FIXME: Is this needed on HW init? */ |
| 908 | pci_mod_config8(MCU, 0x6b, 0x07, 0x01); /* Enable NOP */ |
| 909 | volatile_read(0x0); /* Do NOP */ |
| 910 | pci_mod_config8(MCU, 0x6b, 0x07, 0x03); /* MSR Enable */ |
| 911 | |
| 912 | /* See init_dram_by_rank.c and get_basic_information.c |
| 913 | * in the VIA provided code */ |
| 914 | if (ctrl->n_dimms == 1) { |
| 915 | rtt_nom = DDR3_MR1_RTT_NOM_RZQ2; |
| 916 | rtt_wr = DDR3_MR2_RTTWR_OFF; |
| 917 | } else { |
| 918 | rtt_nom = DDR3_MR1_RTT_NOM_RZQ8; |
| 919 | rtt_wr = DDR3_MR2_RTTWR_RZQ2; |
| 920 | } |
| 921 | ods = ranks->flags[i].rzq7_supported ? |
| 922 | DDR3_MR1_ODS_RZQ7 : DDR3_MR1_ODS_RZQ6; |
| 923 | |
| 924 | pinswap = (ranks->flags[i].pins_mirrored); |
| 925 | if (pinswap) |
| 926 | printram("Pins mirrored\n"); |
| 927 | printram(" Swap : %x\n", pinswap); |
| 928 | printram(" rtt_nom : %x\n", rtt_nom); |
| 929 | printram(" ods : %x\n", ods); |
| 930 | printram(" rtt_wr : %x\n", rtt_wr); |
| 931 | if (RAMINIT_USE_HW_MRS_SEQ) |
| 932 | vx900_dram_ddr3_do_hw_mrs(pinswap, rtt_nom, ods, rtt_wr, |
| 933 | 0, 0); |
| 934 | else |
| 935 | vx900_dram_ddr3_do_sw_mrs(pinswap, rtt_nom, ods, rtt_wr, |
| 936 | 0, 0); |
| 937 | |
| 938 | /* Normal SDRAM Mode */ |
| 939 | pci_mod_config8(MCU, 0x6b, 0x07, 0x00); |
| 940 | |
| 941 | /* Step 15, set the rank to virtual rank 3 */ |
| 942 | vx900_map_pr_vr(i, 3); |
| 943 | } |
| 944 | |
| 945 | /* Step 16 – Set Fun3_Rx6B[2:0] to 000b (Normal SDRAM Mode). */ |
| 946 | pci_mod_config8(MCU, 0x6b, 0x07, 0x00); |
| 947 | |
| 948 | /* Set BA[0/1/2] to [A13/14/15] */ |
| 949 | vx900_dram_set_ma_pin_map(VX900_CALIB_MA_MAP); |
| 950 | |
| 951 | /* Step 17 – Set Fun3_Rx69[0] to 1b (Enable Multiple Page Mode). */ |
| 952 | pci_mod_config8(MCU, 0x69, 0x00, (1 << 0)); |
| 953 | |
| 954 | printram("DIMM initialization sequence complete\n"); |
| 955 | } |
| 956 | |
| 957 | /* |
| 958 | * This a small utility to send a single MRS command, but where we don't want to |
| 959 | * have to worry about changing the MCU mode. It gives the MCU back to us in |
| 960 | * normal operating mode. |
| 961 | */ |
| 962 | static void vx900_dram_send_soft_mrs(mrs_cmd_t cmd, u8 pin_swap) |
| 963 | { |
| 964 | u32 addr; |
| 965 | /* Set Fun3_RX6B[2:0] to 011b (MSR Enable). */ |
| 966 | pci_mod_config8(MCU, 0x6b, 0x07, (3 << 0)); |
| 967 | /* Is this a funky rank with Address pins swapped? */ |
| 968 | if (pin_swap) |
| 969 | cmd = ddr3_mrs_mirror_pins(cmd); |
| 970 | /* Find the address corresponding to the MRS */ |
| 971 | addr = vx900_get_mrs_addr(cmd); |
| 972 | /* Execute the MRS */ |
| 973 | volatile_read(addr); |
| 974 | /* Set Fun3_Rx6B[2:0] to 000b (Normal SDRAM Mode). */ |
| 975 | pci_mod_config8(MCU, 0x6b, 0x07, 0x00); |
| 976 | } |
| 977 | |
| 978 | static void vx900_dram_enter_read_leveling(u8 pinswap) |
| 979 | { |
| 980 | /* Precharge all before issuing read leveling MRS to DRAM */ |
| 981 | pci_mod_config8(MCU, 0x06b, 0x07, 0x02); |
| 982 | volatile_read(0x0); |
| 983 | udelay(1000); |
| 984 | |
| 985 | /* Enable read leveling: Set D0F3Rx71[7]=1 */ |
| 986 | pci_mod_config8(MCU, 0x71, 0, (1 << 7)); |
| 987 | |
| 988 | /* Put DRAM in read leveling mode */ |
| 989 | mrs_cmd_t cmd = ddr3_get_mr3(1); |
| 990 | vx900_dram_send_soft_mrs(cmd, pinswap); |
| 991 | } |
| 992 | |
| 993 | static void vx900_dram_exit_read_leveling(u8 pinswap) |
| 994 | { |
| 995 | /* Disable read leveling, and put dram in normal operation mode */ |
| 996 | mrs_cmd_t cmd = ddr3_get_mr3(0); |
| 997 | vx900_dram_send_soft_mrs(cmd, pinswap); |
| 998 | |
| 999 | /* Disable read leveling: Set D0F3Rx71[7]=0 */ |
| 1000 | pci_mod_config8(MCU, 0x71, (1 << 7), 0); |
| 1001 | } |
| 1002 | |
| 1003 | /* |
| 1004 | * We need to see if the delay window (difference between minimum and maximum) |
| 1005 | * is large enough so that we actually have a valid window. The signal should be |
| 1006 | * valid for at least 1/2T in general. If the window is significantly smaller, |
| 1007 | * then chances are our window does not latch at the correct time, and the |
| 1008 | * calibration will not work. |
| 1009 | */ |
| 1010 | #define DQSI_THRESHOLD 0x10 |
| 1011 | #define DQO_THRESHOLD 0x09 |
| 1012 | #define DQSO_THRESHOLD 0x12 |
| 1013 | #define DELAY_RANGE_GOOD 0 |
| 1014 | #define DELAY_RANGE_BAD -1 |
| 1015 | static u8 vx900_dram_check_calib_range(const delay_range * dly, u8 window) |
| 1016 | { |
| 1017 | size_t i; |
| 1018 | for (i = 0; i < 8; i++) { |
| 1019 | if (dly->high[i] - dly->low[i] < window) |
| 1020 | return DELAY_RANGE_BAD; |
| 1021 | /* When our maximum value is lower than our min, both values |
| 1022 | * have overshot, and the window is definitely invalid */ |
| 1023 | if (dly->high[i] < dly->low[i]) |
| 1024 | return DELAY_RANGE_BAD; |
| 1025 | } |
| 1026 | return DELAY_RANGE_GOOD; |
| 1027 | } |
| 1028 | |
| 1029 | static void vx900_dram_find_avg_delays(vx900_delay_calib * delays) |
| 1030 | { |
| 1031 | size_t i; |
| 1032 | u16 dq_low, dq_high, dqs_low, dqs_high, dq_final, dqs_final; |
| 1033 | /* |
| 1034 | * At this point, we have transmit delays for both DIMMA and DIMMB, each |
| 1035 | * with a slightly different window We want to find the intersection of |
| 1036 | * those windows, so that we have a constrained window which both |
| 1037 | * DIMMA and DIMMB can use. The center of our constrained window will |
| 1038 | * also be the safest setting for the transmit delays |
| 1039 | * |
| 1040 | * DIMMA window t:|xxxxxxxxxxxxxx---------------xxxxxxxxxxxxxxxxxxxxxxx| |
| 1041 | * DIMMB window t:|xxxxxxxxxxxxxxxxxxx---------------xxxxxxxxxxxxxxxxxx| |
| 1042 | * Safe window t:|xxxxxxxxxxxxxxxxxxx----------xxxxxxxxxxxxxxxxxxxxxxx| |
| 1043 | */ |
| 1044 | delay_range *tx_dq_a = &(delays->tx_dq[0]); |
| 1045 | delay_range *tx_dq_b = &(delays->tx_dq[1]); |
| 1046 | delay_range *tx_dqs_a = &(delays->tx_dqs[0]); |
| 1047 | delay_range *tx_dqs_b = &(delays->tx_dqs[1]); |
| 1048 | |
| 1049 | for (i = 0; i < 8; i++) { |
Alexandru Gagniuc | 560433b | 2013-06-10 15:47:25 -0500 | [diff] [blame] | 1050 | dq_low = MAX(tx_dq_a->low[i], tx_dq_b->low[i]); |
| 1051 | dq_high = MIN(tx_dq_a->high[i], tx_dq_b->high[i]); |
| 1052 | dqs_low = MAX(tx_dqs_a->low[i], tx_dqs_b->low[i]); |
| 1053 | dqs_high = MIN(tx_dqs_a->high[i], tx_dqs_b->high[i]); |
Alexandru Gagniuc | 7d31e7c | 2013-06-08 11:49:10 -0500 | [diff] [blame] | 1054 | |
| 1055 | /* Find the average */ |
| 1056 | dq_final = ((dq_low + dq_high) / 2); |
| 1057 | dqs_final = ((dqs_low + dqs_high) / 2); |
| 1058 | |
| 1059 | /* |
| 1060 | * These adjustments are done in code provided by VIA. |
| 1061 | * There is no explanation as to why this is done. |
| 1062 | * |
| 1063 | * We can get away without doing the DQS adjustment, but doing |
| 1064 | * it, brings the values closer to what the vendor BIOS |
| 1065 | * calibrates to. |
| 1066 | */ |
| 1067 | if ((dqs_final & 0x1f) >= 0x1c) |
| 1068 | dqs_final -= 0x1c; |
| 1069 | else |
| 1070 | dqs_final += 0x04; |
| 1071 | /* |
| 1072 | * The DQ adjustment is more critical. If we don't do this |
| 1073 | * adjustment our MCU won't be configured properly, and |
| 1074 | * ram_check() will fail. |
| 1075 | */ |
| 1076 | if ((dq_final & 0x1f) >= 0x14) |
| 1077 | dq_final -= 0x14; |
| 1078 | else |
| 1079 | dq_final += 0x0c; |
| 1080 | |
| 1081 | /* Store our values in the first delay */ |
| 1082 | delays->tx_dq[0].avg[i] = dq_final; |
| 1083 | delays->tx_dqs[0].avg[i] = dqs_final; |
| 1084 | |
| 1085 | } |
| 1086 | } |
| 1087 | |
| 1088 | /* |
| 1089 | * First calibration: When to receive data from the DRAM |
| 1090 | * (MD and MDQS input delay) |
| 1091 | * |
| 1092 | * This calibration unfortunately does not seem to work. Whether this is due to |
| 1093 | * a misconfigured MCU or hardware bug is unknown. |
| 1094 | */ |
| 1095 | static void vx900_rx_capture_range_calib(u8 pinswap) |
| 1096 | { |
| 1097 | u8 reg8; |
| 1098 | const u32 cal_addr = 0x20; |
| 1099 | |
| 1100 | /* Set IO calibration address */ |
| 1101 | pci_mod_config16(MCU, 0x8c, 0xfff0, cal_addr & (0xfff0)); |
| 1102 | /* Data pattern must be 0x00 for this calibration |
| 1103 | * See paragraph describing Rx8e */ |
| 1104 | pci_write_config8(MCU, 0x8e, 0x00); |
| 1105 | |
| 1106 | /* Need to put DRAM and MCU in read leveling */ |
| 1107 | vx900_dram_enter_read_leveling(pinswap); |
| 1108 | |
| 1109 | /* Data pattern must be 0x00 for this calibration |
| 1110 | * See paragraph describing Rx8e */ |
| 1111 | pci_write_config8(MCU, 0x8e, 0x00); |
| 1112 | /* Trigger calibration */ |
| 1113 | reg8 = 0xa0; |
| 1114 | pci_write_config8(MCU, 0x71, reg8); |
| 1115 | |
| 1116 | /* Wait for it */ |
| 1117 | while (pci_read_config8(MCU, 0x71) & 0x10) ; |
| 1118 | vx900_dram_exit_read_leveling(pinswap); |
| 1119 | } |
| 1120 | |
| 1121 | /* |
| 1122 | * Second calibration: How much to delay DQS signal by |
| 1123 | * (MDQS input delay) |
| 1124 | */ |
| 1125 | static void vx900_rx_dqs_delay_calib(u8 pinswap) |
| 1126 | { |
| 1127 | const u32 cal_addr = 0x30; |
| 1128 | |
| 1129 | /* We need to disable refresh commands so that they don't interfere */ |
| 1130 | const u8 ref_cnt = pci_read_config8(MCU, 0xc7); |
| 1131 | pci_write_config8(MCU, 0xc7, 0); |
| 1132 | /* Set IO calibration address */ |
| 1133 | pci_mod_config16(MCU, 0x8c, 0xfff0, cal_addr & (0xfff0)); |
| 1134 | /* Data pattern must be 0x00 for this calibration |
| 1135 | * See paragraph describing Rx8e */ |
| 1136 | pci_write_config8(MCU, 0x8e, 0x00); |
| 1137 | |
| 1138 | /* Need to put DRAM and MCU in read leveling */ |
| 1139 | vx900_dram_enter_read_leveling(pinswap); |
| 1140 | |
| 1141 | /* From VIA code; Undocumented |
| 1142 | * In theory this enables MODT[3:0] to be asserted */ |
| 1143 | pci_mod_config8(MCU, 0x9e, 0, 0x80); |
| 1144 | |
| 1145 | /* Trigger calibration: Set D0F3Rx71[1:0]=10b */ |
| 1146 | pci_mod_config8(MCU, 0x71, 0x03, 0x02); |
| 1147 | |
| 1148 | /* Wait for calibration to complete */ |
| 1149 | while (pci_read_config8(MCU, 0x71) & 0x02) ; |
| 1150 | vx900_dram_exit_read_leveling(pinswap); |
| 1151 | |
| 1152 | /* Restore the refresh counter */ |
| 1153 | pci_write_config8(MCU, 0xc7, ref_cnt); |
| 1154 | |
| 1155 | /* FIXME: should we save it before, or should we just set it as is */ |
| 1156 | vx900_dram_set_ma_pin_map(VX900_CALIB_MA_MAP); |
| 1157 | } |
| 1158 | |
| 1159 | static void vx900_tx_dqs_trigger_calib(u8 pattern) |
| 1160 | { |
| 1161 | /* Data pattern for calibration */ |
| 1162 | pci_write_config8(MCU, 0x8e, pattern); |
| 1163 | /* Trigger calibration */ |
| 1164 | pci_mod_config8(MCU, 0x75, 0, 0x20); |
| 1165 | /* Wait for calibration */ |
| 1166 | while (pci_read_config8(MCU, 0x75) & 0x20) ; |
| 1167 | } |
| 1168 | |
| 1169 | /* |
| 1170 | * Third calibration: How much to wait before asserting DQS |
| 1171 | */ |
| 1172 | static void vx900_tx_dqs_delay_calib(void) |
| 1173 | { |
| 1174 | const u32 cal_addr = 0x00; |
| 1175 | /* Set IO calibration address */ |
| 1176 | pci_mod_config16(MCU, 0x8c, 0xfff0, cal_addr & (0xfff0)); |
| 1177 | /* Set circuit to use calibration results - Clear Rx75[0] */ |
| 1178 | pci_mod_config8(MCU, 0x75, 0x01, 0); |
| 1179 | /* Run calibration with first data pattern */ |
| 1180 | vx900_tx_dqs_trigger_calib(0x5a); |
| 1181 | /* Run again with different pattern */ |
| 1182 | vx900_tx_dqs_trigger_calib(0xa5); |
| 1183 | } |
| 1184 | |
| 1185 | /* |
| 1186 | * Fourt calibration: How much to wait before putting data on DQ lines |
| 1187 | */ |
| 1188 | static void vx900_tx_dq_delay_calib(void) |
| 1189 | { |
| 1190 | /* Data pattern for calibration */ |
| 1191 | pci_write_config8(MCU, 0x8e, 0x5a); |
| 1192 | /* Trigger calibration */ |
| 1193 | pci_mod_config8(MCU, 0x75, 0, 0x02); |
| 1194 | /* Wait for calibration */ |
| 1195 | while (pci_read_config8(MCU, 0x75) & 0x02) ; |
| 1196 | } |
| 1197 | |
| 1198 | static void vx900_rxdqs_adjust(delay_range * dly) |
| 1199 | { |
| 1200 | /* Adjust Rx DQS delay after calibration has been run. This is |
| 1201 | * recommended by VIA, but no explanation was provided as to why */ |
| 1202 | size_t i; |
| 1203 | for (i = 0; i < 8; i++) { |
| 1204 | if (dly->low[i] < 3) { |
| 1205 | if (i == 2 || i == 4) |
| 1206 | dly->avg[i] += 4; |
| 1207 | else |
| 1208 | dly->avg[i] += 3; |
| 1209 | |
| 1210 | } |
| 1211 | |
| 1212 | if (dly->high[i] > 0x38) |
| 1213 | dly->avg[i] -= 6; |
| 1214 | else if (dly->high[i] > 0x30) |
| 1215 | dly->avg[i] -= 4; |
| 1216 | |
| 1217 | if (dly->avg[i] > 0x20) |
| 1218 | dly->avg[i] = 0x20; |
| 1219 | } |
| 1220 | |
| 1221 | /* Put Rx DQS delay into manual mode (Set Rx[2,0] to 01) */ |
| 1222 | pci_mod_config8(MCU, 0x71, 0x05, 0x01); |
| 1223 | /* Now write the new settings */ |
| 1224 | vx900_delay_calib_mode_select(CALIB_RxDQS, CALIB_MANUAL); |
| 1225 | vx900_write_0x78_0x7f(dly->avg); |
| 1226 | } |
| 1227 | |
| 1228 | static void vx900_dram_calibrate_recieve_delays(vx900_delay_calib * delays, |
| 1229 | u8 pinswap) |
| 1230 | { |
| 1231 | size_t n_tries = 0; |
| 1232 | delay_range *rx_dq_cr = &(delays->rx_dq_cr); |
| 1233 | delay_range *rx_dqs = &(delays->rx_dqs); |
| 1234 | /* We really should be able to finish this in a single pass, but it may |
| 1235 | * in very rare circumstances not work the first time. We define a limit |
| 1236 | * on the number of tries so that we have a way of warning the user */ |
| 1237 | const size_t max_tries = 100; |
| 1238 | for (;;) { |
| 1239 | if (n_tries++ >= max_tries) { |
| 1240 | die("Could not calibrate receive delays. Giving up"); |
| 1241 | } |
| 1242 | u8 result; |
| 1243 | /* Run calibrations */ |
| 1244 | if (RAMINIT_USE_HW_RXCR_CALIB) { |
| 1245 | vx900_rx_capture_range_calib(pinswap); |
| 1246 | vx900_read_delay_range(rx_dq_cr, CALIB_RxDQ_CR); |
| 1247 | dump_delay_range(*rx_dq_cr); |
| 1248 | |
| 1249 | } else { |
| 1250 | /*FIXME: Cheating with Rx CR setting\ |
| 1251 | * We need to either use Rx CR calibration |
| 1252 | * or set up a table for the calibration */ |
| 1253 | u8 *override = &(rx_dq_cr->avg[0]); |
| 1254 | override[0] = 0x28; |
| 1255 | override[1] = 0x1c; |
| 1256 | override[2] = 0x28; |
| 1257 | override[3] = 0x28; |
| 1258 | override[4] = 0x2c; |
| 1259 | override[5] = 0x30; |
| 1260 | override[6] = 0x30; |
| 1261 | override[7] = 0x34; |
| 1262 | printram("Bypassing RxCR 78-7f calibration with:\n"); |
| 1263 | dump_delay(rx_dq_cr->avg); |
| 1264 | } |
| 1265 | /* We need to put the setting on manual mode */ |
| 1266 | pci_mod_config8(MCU, 0x71, 0, 1 << 4); |
| 1267 | vx900_delay_calib_mode_select(CALIB_RxDQ_CR, CALIB_MANUAL); |
| 1268 | vx900_write_0x78_0x7f(rx_dq_cr->avg); |
| 1269 | |
| 1270 | /************* RxDQS *************/ |
| 1271 | vx900_rx_dqs_delay_calib(pinswap); |
| 1272 | vx900_read_delay_range(rx_dqs, CALIB_RxDQS); |
| 1273 | vx900_rxdqs_adjust(rx_dqs); |
| 1274 | |
| 1275 | result = vx900_dram_check_calib_range(rx_dqs, DQSI_THRESHOLD); |
| 1276 | if (result != DELAY_RANGE_GOOD) |
| 1277 | continue; |
| 1278 | |
| 1279 | /* We're good to go. Switch to manual and write the manual |
| 1280 | * setting */ |
| 1281 | pci_mod_config8(MCU, 0x71, 0, 1 << 0); |
| 1282 | vx900_delay_calib_mode_select(CALIB_RxDQS, CALIB_MANUAL); |
| 1283 | vx900_write_0x78_0x7f(rx_dqs->avg); |
| 1284 | break; |
| 1285 | } |
| 1286 | if (n_tries > 1) |
| 1287 | printram("Hmm, we had to try %lu times before our calibration " |
| 1288 | "was good.\n", n_tries); |
| 1289 | } |
| 1290 | |
| 1291 | static void vx900_dram_calibrate_transmit_delays(delay_range * tx_dq, |
| 1292 | delay_range * tx_dqs) |
| 1293 | { |
| 1294 | /* Same timeout reasoning as in receive delays */ |
| 1295 | size_t n_tries = 0; |
Idwer Vollering | d26da9c | 2013-12-22 21:38:18 +0000 | [diff] [blame] | 1296 | int dq_tries = 0, dqs_tries = 0; |
Alexandru Gagniuc | 7d31e7c | 2013-06-08 11:49:10 -0500 | [diff] [blame] | 1297 | const size_t max_tries = 100; |
| 1298 | for (;;) { |
| 1299 | if (n_tries++ >= max_tries) { |
| 1300 | printram("Tried DQS %i times and DQ %i times\n", |
| 1301 | dqs_tries, dq_tries); |
| 1302 | printram("Tx DQS calibration results\n"); |
| 1303 | dump_delay_range(*tx_dqs); |
| 1304 | printram("TX DQ delay calibration results:\n"); |
| 1305 | dump_delay_range(*tx_dq); |
| 1306 | die("Could not calibrate transmit delays. Giving up"); |
| 1307 | } |
| 1308 | u8 result; |
| 1309 | /************* TxDQS *************/ |
| 1310 | dqs_tries++; |
| 1311 | vx900_tx_dqs_delay_calib(); |
| 1312 | vx900_read_delay_range(tx_dqs, CALIB_TxDQS); |
| 1313 | |
| 1314 | result = vx900_dram_check_calib_range(tx_dqs, DQSO_THRESHOLD); |
| 1315 | if (result != DELAY_RANGE_GOOD) |
| 1316 | continue; |
| 1317 | |
| 1318 | /************* TxDQ *************/ |
| 1319 | /* FIXME: not sure if multiple page mode should be enabled here |
| 1320 | * Vendor BIOS does it */ |
| 1321 | pci_mod_config8(MCU, 0x69, 0, 0x01); |
| 1322 | |
| 1323 | dq_tries++; |
| 1324 | vx900_tx_dq_delay_calib(); |
| 1325 | vx900_read_delay_range(tx_dq, CALIB_TxDQ); |
| 1326 | |
| 1327 | result = vx900_dram_check_calib_range(tx_dq, DQO_THRESHOLD); |
| 1328 | if (result != DELAY_RANGE_GOOD) |
| 1329 | continue; |
| 1330 | |
| 1331 | /* At this point, our RAM should give correct read-backs for |
| 1332 | * addresses under 64 MB. If it doesn't, it won't work */ |
| 1333 | if (ram_check_noprint_nodie(1 << 20, 1 << 20)) { |
| 1334 | /* No, our RAM is not working, try again */ |
| 1335 | /* FIXME: Except that we have not yet told the MCU what |
| 1336 | * the geometry of the DIMM is, hence we don't trust |
| 1337 | * this test for now */ |
| 1338 | ////continue; |
| 1339 | } |
| 1340 | /* Good. We should be able to use this DIMM */ |
| 1341 | /* That's it. We're done */ |
| 1342 | break; |
| 1343 | } |
| 1344 | if (n_tries > 1) |
| 1345 | printram("Hmm, we had to try %lu times before our calibration " |
| 1346 | "was good.\n", n_tries); |
| 1347 | } |
| 1348 | |
| 1349 | /* |
| 1350 | * The meat and potatoes of getting our MCU to operate the DIMMs properly. |
| 1351 | * |
| 1352 | * Thank you JEDEC for making us need configurable delays for each set of MD |
| 1353 | * signals. |
| 1354 | */ |
| 1355 | static void vx900_dram_calibrate_delays(const ramctr_timing * ctrl, |
| 1356 | const rank_layout * ranks) |
| 1357 | { |
| 1358 | size_t i; |
| 1359 | u8 val; |
| 1360 | u8 dimm; |
| 1361 | vx900_delay_calib delay_cal; |
| 1362 | memset(&delay_cal, 0, sizeof(delay_cal)); |
| 1363 | printram("Starting delay calibration\n"); |
| 1364 | |
| 1365 | /**** Read delay control ****/ |
| 1366 | /* MD Input Data Push Timing Control; |
| 1367 | * use values recommended in datasheet |
| 1368 | * Setting this too low causes the Rx window to move below the range we |
| 1369 | * need it so we can capture it with Rx_78_7f |
| 1370 | * This causes Rx calibrations to be too close to 0, and Tx |
| 1371 | * calibrations will fail. |
| 1372 | * Setting this too high causes the window to move above the range. |
| 1373 | */ |
| 1374 | if (ctrl->tCK <= TCK_533MHZ) |
| 1375 | val = 2; |
| 1376 | else if (ctrl->tCK <= TCK_333MHZ) |
| 1377 | val = 1; |
| 1378 | else |
| 1379 | val = 0; |
| 1380 | val++; /* FIXME: vendor BIOS sets this to 3 */ |
| 1381 | pci_mod_config8(MCU, 0x74, (0x03 << 1), ((val & 0x03) << 1)); |
| 1382 | |
| 1383 | /* FIXME: The vendor BIOS increases the MD input delay - WHY ? */ |
| 1384 | pci_mod_config8(MCU, 0xef, (3 << 4), 3 << 4); |
| 1385 | |
| 1386 | /**** Write delay control ****/ |
| 1387 | /* FIXME: The vendor BIOS does this, but WHY? |
| 1388 | * See check_special_registers in VIA provided code. This value seems |
| 1389 | * to depend on the DRAM frequency. |
| 1390 | */ |
| 1391 | /* Early DQ/DQS for write cycles */ |
| 1392 | pci_mod_config8(MCU, 0x76, (3 << 2), 2 << 2); |
| 1393 | /* FIXME: The vendor BIOS does this - Output preamble ? */ |
| 1394 | pci_write_config8(MCU, 0x77, 0x10); |
| 1395 | |
| 1396 | /* Set BA[0/1/2] to [A17/18/19] */ |
| 1397 | vx900_dram_set_ma_pin_map(VX900_MRS_MA_MAP); |
| 1398 | /* Disable Multiple Page Mode - Set Rx69[0] to 0 */ |
| 1399 | pci_mod_config8(MCU, 0x69, (1 << 0), 0x00); |
| 1400 | |
| 1401 | /* It's very important that we keep all ranks which are not calibrated |
| 1402 | * mapped to VR3. Even if we disable them, if they are mapped to VR0 |
| 1403 | * (the rank we use for calibrations), the calibrations may fail in |
| 1404 | * unexpected ways. */ |
| 1405 | vx900_pr_map_all_vr3(); |
| 1406 | |
| 1407 | /* We only really need to run the receive calibrations once. They are |
| 1408 | * meant to account for signal travel differences in the internal paths |
| 1409 | * of the MCU, so it doesn't really matter which rank we use for this. |
| 1410 | * Differences between ranks will be accounted for in the transmit |
| 1411 | * calibration. */ |
| 1412 | for (i = 0; i < VX900_MAX_DIMM_SLOTS; i += 2) { |
| 1413 | /* Do we have a valid DIMM? */ |
| 1414 | if (ranks->phys_rank_size_mb[i] + |
| 1415 | ranks->phys_rank_size_mb[i + 1] == 0) |
| 1416 | continue; |
| 1417 | /* Map the first rank of the DIMM to VR0 */ |
| 1418 | vx900_map_pr_vr(2 * i, 0); |
| 1419 | /* Only run on first rank, remember? */ |
| 1420 | break; |
| 1421 | } |
| 1422 | vx900_dram_calibrate_recieve_delays(&delay_cal, |
| 1423 | ranks->flags[i].pins_mirrored); |
| 1424 | printram("RX DQS calibration results\n"); |
| 1425 | dump_delay_range(delay_cal.rx_dqs); |
| 1426 | |
| 1427 | /* Enable multiple page mode for when calibrating transmit delays */ |
| 1428 | pci_mod_config8(MCU, 0x69, 0, 1 << 1); |
| 1429 | |
| 1430 | /* |
| 1431 | * Unlike the receive delays, we need to run the transmit calibration |
| 1432 | * for each DIMM (not rank). We run the calibration on the even rank. |
| 1433 | * The odd rank may have memory pins swapped, and this, it seems, |
| 1434 | * confuses the calibration circuit. |
| 1435 | */ |
| 1436 | dimm = 0; |
| 1437 | for (i = 0; i < VX900_MAX_DIMM_SLOTS; i++) { |
| 1438 | /* Do we have a valid DIMM? */ |
| 1439 | u32 dimm_size_mb = ranks->phys_rank_size_mb[2 * i] |
| 1440 | + ranks->phys_rank_size_mb[2 * i + 1]; |
| 1441 | if (dimm_size_mb == 0) |
| 1442 | continue; |
| 1443 | /* Map the first rank of the DIMM to VR0 */ |
| 1444 | vx900_map_pr_vr(2 * i, 0); |
| 1445 | vx900_dram_calibrate_transmit_delays(&(delay_cal.tx_dq[dimm]), |
| 1446 | &(delay_cal.tx_dqs[dimm])); |
| 1447 | /* We run this more than once, so dump delays for each DIMM */ |
| 1448 | printram("Tx DQS calibration results\n"); |
| 1449 | dump_delay_range(delay_cal.tx_dqs[dimm]); |
| 1450 | printram("TX DQ delay calibration results:\n"); |
| 1451 | dump_delay_range(delay_cal.tx_dq[dimm]); |
| 1452 | /* Now move the DIMM back to VR3 */ |
| 1453 | vx900_map_pr_vr(2 * i, 3); |
| 1454 | /* We use dimm as a counter so that we fill tx_dq[] and tx_dqs[] |
| 1455 | * results in order from 0, and do not leave any gaps */ |
| 1456 | dimm++; |
| 1457 | } |
| 1458 | |
| 1459 | /* When we have more dimms, we need to find a tx window with which all |
| 1460 | * dimms can safely work */ |
| 1461 | if (dimm > 1) { |
| 1462 | vx900_dram_find_avg_delays(&delay_cal); |
| 1463 | printram("Final delay values\n"); |
| 1464 | printram("Tx DQS: "); |
| 1465 | dump_delay(delay_cal.tx_dqs[0].avg); |
| 1466 | printram("Tx DQ: "); |
| 1467 | dump_delay(delay_cal.tx_dq[0].avg); |
| 1468 | } |
| 1469 | /* Write manual settings */ |
| 1470 | pci_mod_config8(MCU, 0x75, 0, 0x01); |
| 1471 | vx900_delay_calib_mode_select(CALIB_TxDQS, CALIB_MANUAL); |
| 1472 | vx900_write_0x78_0x7f(delay_cal.tx_dqs[0].avg); |
| 1473 | vx900_delay_calib_mode_select(CALIB_TxDQ, CALIB_MANUAL); |
| 1474 | vx900_write_0x78_0x7f(delay_cal.tx_dq[0].avg); |
| 1475 | } |
| 1476 | |
| 1477 | static void vx900_dram_set_refresh_counter(ramctr_timing * ctrl) |
| 1478 | { |
| 1479 | u8 reg8; |
| 1480 | /* Set DRAM refresh counter |
| 1481 | * Based on a refresh counter of 0x61 at 400MHz */ |
| 1482 | reg8 = (TCK_400MHZ * 0x61) / ctrl->tCK; |
| 1483 | pci_write_config8(MCU, 0xc7, reg8); |
| 1484 | } |
| 1485 | |
| 1486 | /* |
| 1487 | * Here, we map each rank somewhere in our address space. We don't really care |
| 1488 | * at this point if this will overlap the PCI config space. If needed, remapping |
| 1489 | * is done in ramstage, where we actually know how much PCI space we actually |
| 1490 | * need. |
| 1491 | */ |
| 1492 | static void vx900_dram_range(ramctr_timing * ctrl, rank_layout * ranks) |
| 1493 | { |
| 1494 | size_t i, vrank = 0; |
| 1495 | u8 reg8; |
| 1496 | u32 ramsize_mb = 0, tolm_mb; |
| 1497 | const u32 TOLM_3_5G = (7 << 29); |
| 1498 | /* All unused physical ranks go to VR3. Otherwise, the MCU might be |
| 1499 | * trying to read or write from unused ranks, or even worse, write some |
| 1500 | * bits to the rank we want, and some to the unused ranks, even though |
| 1501 | * they are disabled. Since VR3 is the last virtual rank to be used, we |
| 1502 | * eliminate any ambiguities that the MCU may face. */ |
| 1503 | vx900_pr_map_all_vr3(); |
| 1504 | for (i = 0; i < VX900_MAX_MEM_RANKS; i++) { |
| 1505 | u32 rank_size_mb = ranks->phys_rank_size_mb[i]; |
| 1506 | if (!rank_size_mb) |
| 1507 | continue; |
| 1508 | |
| 1509 | /* vvvvvvvvvv FIXME: Fix odd rank init vvvvvvvvvv */ |
| 1510 | if ((i & 1)) { |
Patrick Georgi | 6f7e4b2 | 2014-05-19 09:18:11 +0200 | [diff] [blame] | 1511 | printk(BIOS_EMERG, "I cannot initialize rank %zu\n", i); |
Stefan Reinauer | 65b72ab | 2015-01-05 12:59:54 -0800 | [diff] [blame] | 1512 | printk(BIOS_EMERG, "I have to disable it\n"); |
Alexandru Gagniuc | 7d31e7c | 2013-06-08 11:49:10 -0500 | [diff] [blame] | 1513 | continue; |
| 1514 | } |
| 1515 | /* ^^^^^^^^^^ FIXME: Fix odd rank init ^^^^^^^^^^ */ |
| 1516 | |
| 1517 | ranks->virt[vrank].start_addr = ramsize_mb; |
| 1518 | ramsize_mb += rank_size_mb; |
| 1519 | ranks->virt[vrank].end_addr = ramsize_mb; |
| 1520 | |
| 1521 | /* Rank memory range */ |
| 1522 | reg8 = (ranks->virt[vrank].start_addr >> 6); |
| 1523 | pci_write_config8(MCU, 0x48 + vrank, reg8); |
| 1524 | reg8 = (ranks->virt[vrank].end_addr >> 6); |
| 1525 | pci_write_config8(MCU, 0x40 + vrank, reg8); |
| 1526 | |
| 1527 | vx900_map_pr_vr(i, vrank); |
| 1528 | |
| 1529 | printram("Mapped Physical rank %u, to virtual rank %u\n" |
| 1530 | " Start address: 0x%.10llx\n" |
| 1531 | " End address: 0x%.10llx\n", |
| 1532 | (int)i, (int)vrank, |
| 1533 | (u64) ranks->virt[vrank].start_addr << 20, |
| 1534 | (u64) ranks->virt[vrank].end_addr << 20); |
| 1535 | /* Move on to next virtual rank */ |
| 1536 | vrank++; |
| 1537 | } |
| 1538 | |
| 1539 | /* Limit the Top of Low memory at 3.5G |
| 1540 | * Not to worry, we'll set tolm in ramstage, once we have initialized |
| 1541 | * all devices and know pci_tolm. */ |
Alexandru Gagniuc | 560433b | 2013-06-10 15:47:25 -0500 | [diff] [blame] | 1542 | tolm_mb = MIN(ramsize_mb, TOLM_3_5G >> 20); |
Alexandru Gagniuc | 7d31e7c | 2013-06-08 11:49:10 -0500 | [diff] [blame] | 1543 | u16 reg_tolm = (tolm_mb << 4) & 0xfff0; |
| 1544 | pci_mod_config16(MCU, 0x84, 0xfff0, reg_tolm); |
| 1545 | |
| 1546 | printram("Initialized %u virtual ranks, with a total size of %u MB\n", |
| 1547 | (int)vrank, ramsize_mb); |
| 1548 | } |
| 1549 | |
| 1550 | /* |
| 1551 | * Here, we tell the memory controller how to treat a DIMM. This is an extremely |
| 1552 | * important step. It tells the MCU how many address bits we have in each DIMM, |
| 1553 | * and how to use them. This information is essential for the controller to |
| 1554 | * understand the DIMM addressing, and write and read data in the correct place. |
| 1555 | */ |
| 1556 | static void vx900_dram_map_row_col_bank(dimm_info * dimms) |
| 1557 | { |
| 1558 | u8 reg8, rcb_val, col_bits, max_row_bits; |
| 1559 | size_t i; |
| 1560 | /* Do we have 4Gbit chips? */ |
| 1561 | /* FIXME: Implement this */ |
| 1562 | |
| 1563 | /* Do we have 8Gbit chips? */ |
| 1564 | /* FIXME: Implement this */ |
| 1565 | |
| 1566 | max_row_bits = rcb_val = reg8 = 0; |
| 1567 | for (i = 0; i < VX900_MAX_DIMM_SLOTS; i++) { |
| 1568 | if (dimms->dimm[i].dram_type == SPD_MEMORY_TYPE_UNDEFINED) |
| 1569 | continue; |
| 1570 | |
| 1571 | col_bits = dimms->dimm[i].col_bits; |
| 1572 | |
| 1573 | /* |
| 1574 | * DDR3 always uses 3 bank address bits, and MA type 111b cannot |
| 1575 | * be used due to chipset limitation. We are left with only two |
| 1576 | * options, which we can choose based solely on the number of |
| 1577 | * column address bits. |
| 1578 | */ |
| 1579 | if ((col_bits < 10) || (col_bits > 11)) { |
| 1580 | printram("DIMM %ld has %d column address bits.\n", |
| 1581 | i, col_bits); |
| 1582 | die("Unsupported DIMM. Try booting without this DIMM"); |
| 1583 | } |
| 1584 | |
| 1585 | rcb_val = col_bits - 5; |
| 1586 | reg8 |= (rcb_val << ((i * 3) + 2)); |
| 1587 | |
| 1588 | /* */ |
Alexandru Gagniuc | 560433b | 2013-06-10 15:47:25 -0500 | [diff] [blame] | 1589 | max_row_bits = MAX(max_row_bits, dimms->dimm[i].row_bits); |
Alexandru Gagniuc | 7d31e7c | 2013-06-08 11:49:10 -0500 | [diff] [blame] | 1590 | } |
| 1591 | |
| 1592 | printram("RCBA map (rx50) <- %.2x\n", reg8); |
| 1593 | pci_write_config8(MCU, 0x50, reg8); |
| 1594 | |
| 1595 | printram("Houston, we have %d row address bits\n", max_row_bits); |
| 1596 | /* FIXME: Do this properly */ |
| 1597 | vx900_dram_map_pins(13, 14, 15, 17, 16); |
| 1598 | |
| 1599 | } |
| 1600 | |
| 1601 | /* |
| 1602 | * Here, we set some final configuration bits, which should improve the |
| 1603 | * performance of the memory slightly (arbitration, expiration counters, etc.) |
| 1604 | * |
| 1605 | * FIXME: We don't really do much else than the minimum to get the MCU properly |
| 1606 | * configured. We don't yet do set the "performance-enhancing" bits referenced |
| 1607 | * in the comment above. |
| 1608 | */ |
| 1609 | static void vx900_dram_write_final_config(ramctr_timing * ctrl) |
| 1610 | { |
| 1611 | /* FIXME: These are quick cheats */ |
| 1612 | |
| 1613 | /* FIXME: Why are we doing this? */ |
| 1614 | /* Tri-state MCSi# when rank is in self-refresh */ |
| 1615 | pci_mod_config8(MCU, 0x99, 0, 0x0f); |
| 1616 | |
| 1617 | ////pci_write_config8(MCU, 0x69, 0xe7); |
| 1618 | /* Enable paging mode and 8 page registers */ |
| 1619 | pci_mod_config8(MCU, 0x69, 0, 0xe5); |
| 1620 | ////pci_write_config8(MCU, 0x72, 0x0f); |
| 1621 | |
| 1622 | ////pci_write_config8(MCU, 0x97, 0xa4); /* self-refresh */ |
| 1623 | ////pci_write_config8(MCU, 0x98, 0xba); /* self-refresh II */ |
| 1624 | ////pci_write_config8(MCU, 0x9a, 0x80); /* self-refresh III */ |
| 1625 | |
| 1626 | /* Enable automatic triggering of short ZQ calibration */ |
| 1627 | pci_write_config8(MCU, 0xc8, 0x80); |
| 1628 | |
| 1629 | /* And last but not least, Enable A20 line */ |
| 1630 | outb(inb(0x92) | (1 << 1), 0x92); |
| 1631 | } |
| 1632 | |
| 1633 | void vx900_init_dram_ddr3(const dimm_layout * dimm_addr) |
| 1634 | { |
| 1635 | dimm_info dimm_prop; |
| 1636 | ramctr_timing ctrl_prop; |
| 1637 | rank_layout ranks; |
| 1638 | device_t mcu; |
| 1639 | |
| 1640 | if (!ram_check_noprint_nodie(1 << 20, 1 << 20)) { |
| 1641 | printram("RAM is already initialized. Skipping init\n"); |
| 1642 | return; |
| 1643 | } |
| 1644 | /* Locate the Memory controller */ |
| 1645 | mcu = pci_locate_device(PCI_ID(PCI_VENDOR_ID_VIA, |
| 1646 | PCI_DEVICE_ID_VIA_VX900_MEMCTRL), 0); |
| 1647 | |
| 1648 | if (mcu == PCI_DEV_INVALID) { |
| 1649 | die("Memory Controller not found\n"); |
| 1650 | } |
| 1651 | memset(&dimm_prop, 0, sizeof(dimm_prop)); |
| 1652 | memset(&ctrl_prop, 0, sizeof(ctrl_prop)); |
| 1653 | memset(&ranks, 0, sizeof(ranks)); |
| 1654 | /* 1) Write some initial "safe" parameters */ |
| 1655 | vx900_dram_write_init_config(); |
| 1656 | /* 2) Get timing information from SPDs */ |
| 1657 | dram_find_spds_ddr3(dimm_addr, &dimm_prop); |
| 1658 | /* 3) Find lowest common denominator for all modules */ |
| 1659 | dram_find_common_params(&dimm_prop, &ctrl_prop); |
| 1660 | /* 4) Find the size of each memory rank */ |
| 1661 | vx900_dram_phys_bank_range(&dimm_prop, &ranks); |
| 1662 | /* 5) Set DRAM driving strength */ |
| 1663 | vx900_dram_driving_ctrl(&dimm_prop); |
| 1664 | /* 6) Set DRAM frequency and latencies */ |
| 1665 | vx900_dram_timing(&ctrl_prop); |
| 1666 | vx900_dram_freq(&ctrl_prop); |
| 1667 | /* 7) Initialize the modules themselves */ |
| 1668 | vx900_dram_ddr3_dimm_init(&ctrl_prop, &ranks); |
| 1669 | /* 8) Set refresh counter based on DRAM frequency */ |
| 1670 | vx900_dram_set_refresh_counter(&ctrl_prop); |
| 1671 | /* 9) Calibrate receive and transmit delays */ |
| 1672 | vx900_dram_calibrate_delays(&ctrl_prop, &ranks); |
| 1673 | /* 10) Enable Physical to Virtual Rank mapping */ |
| 1674 | vx900_dram_range(&ctrl_prop, &ranks); |
| 1675 | /* 11) Map address bits to DRAM pins */ |
| 1676 | vx900_dram_map_row_col_bank(&dimm_prop); |
| 1677 | /* 99) Some final adjustments */ |
| 1678 | vx900_dram_write_final_config(&ctrl_prop); |
| 1679 | /* Take a dump */ |
| 1680 | dump_pci_device(mcu); |
| 1681 | } |