Alexandru Gagniuc | 88a3023 | 2013-06-04 23:37:56 -0500 | [diff] [blame] | 1 | /* |
| 2 | * This file is part of the coreboot project. |
| 3 | * |
| 4 | * Copyright (C) 2012 Alexandru Gagniuc <mr.nuke.me@gmail.com> |
| 5 | * |
| 6 | * This program is free software: you can redistribute it and/or modify |
| 7 | * it under the terms of the GNU General Public License as published by |
| 8 | * the Free Software Foundation, either version 2 of the License, or |
| 9 | * (at your option) any later version. |
| 10 | * |
| 11 | * This program is distributed in the hope that it will be useful, |
| 12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 14 | * GNU General Public License for more details. |
Alexandru Gagniuc | 88a3023 | 2013-06-04 23:37:56 -0500 | [diff] [blame] | 15 | */ |
| 16 | |
| 17 | #include "early_vx900.h" |
| 18 | #include <arch/io.h> |
| 19 | #include <console/console.h> |
| 20 | |
| 21 | unsigned long get_top_of_ram(void) |
| 22 | { |
| 23 | u16 reg_tom = pci_read_config8(MCU, 0x88); |
| 24 | return (((unsigned long)reg_tom) << 24) - (256 << 20); |
| 25 | } |
| 26 | |
Alexandru Gagniuc | 88a3023 | 2013-06-04 23:37:56 -0500 | [diff] [blame] | 27 | /** |
| 28 | * \brief Enable accessing of PCI configuration space for all devices. |
| 29 | * |
| 30 | * Enable accessing of D0F1 through D0F7, which would otherwise not be |
| 31 | * accessible. If MMCONF is enabled, configure it here. This is the first |
| 32 | * function that should be called in romstage. |
| 33 | */ |
| 34 | void vx900_enable_pci_config_space(void) |
| 35 | { |
| 36 | /* MMCONF is not yet enabled, so we'll need to specify we want to do |
| 37 | * pci_io. We don't want to do pci_mmio until we enable it */ |
| 38 | /* Enable multifunction bit for northbridge. |
| 39 | * This enables the PCI configuration spaces of D0F1 to D0F7 to be |
| 40 | * accessed */ |
| 41 | pci_io_write_config8(HOST_CTR, 0x4f, 0x01); |
| 42 | |
| 43 | #if CONFIG_MMCONF_SUPPORT |
| 44 | /* COOL, now enable MMCONF */ |
| 45 | u8 reg8 = pci_io_read_config8(TRAF_CTR, 0x60); |
| 46 | reg8 |= 3; |
| 47 | pci_io_write_config8(TRAF_CTR, 0x60, reg8); |
| 48 | reg8 = CONFIG_MMCONF_BASE_ADDRESS >> 28; |
| 49 | pci_io_write_config8(TRAF_CTR, 0x61, reg8); |
| 50 | #endif |
| 51 | } |
| 52 | |
| 53 | /** |
| 54 | *\brief Prints information regarding the hardware strapping on VX900 |
| 55 | * |
| 56 | * Certain features on the VX900 are controlled by strapping pins which are |
| 57 | * hardwired on the mainboard. These values determine whether the ROM is on the |
| 58 | * SPI or LPC bus, or whether auto-reset is enabled. |
| 59 | * \n |
| 60 | * Having a feel for these values is important when trying to fix obscure |
| 61 | * problems found when porting a mainboard based on the VX900. |
| 62 | * \n |
| 63 | * These values are decoded and printed to the terminal. |
| 64 | */ |
| 65 | void vx900_print_strapping_info(void) |
| 66 | { |
| 67 | u8 strap = pci_read_config8(SNMIC, 0x56); |
| 68 | |
Stefan Reinauer | 65b72ab | 2015-01-05 12:59:54 -0800 | [diff] [blame] | 69 | printk(BIOS_DEBUG, "VX900 strapping pins indicate that:\n"); |
Alexandru Gagniuc | 88a3023 | 2013-06-04 23:37:56 -0500 | [diff] [blame] | 70 | printk(BIOS_DEBUG, " ROM is on %s bus\n", |
| 71 | (strap & (1 << 0)) ? "SPI" : "LPC"); |
| 72 | printk(BIOS_DEBUG, " Auto reset is %s\n", |
| 73 | (strap & (1 << 1)) ? "disabled" : "enabled"); |
| 74 | printk(BIOS_DEBUG, " LPC FWH command is %s\n", |
| 75 | (strap & (1 << 2)) ? "enabled" : "disabled"); |
| 76 | printk(BIOS_DEBUG, " Debug link is is %s\n", |
| 77 | (strap & (1 << 4)) ? "enabled" : "disabled"); |
| 78 | printk(BIOS_DEBUG, " PCI master mode is %s\n", |
| 79 | (strap & (1 << 5)) ? "enabled" : "disabled"); |
| 80 | } |
| 81 | |
| 82 | /** |
| 83 | *\brief Disables the auto-reboot mechanism on VX900 |
| 84 | * |
| 85 | * The VX900 has an auto-reboot mechanism that can be enabled by a hardware |
| 86 | * strap. This mechanism can make development annoying, since we don't know if |
| 87 | * the reset was caused by a bug in coreboot, or by this mechanism. |
| 88 | */ |
| 89 | void vx900_disable_auto_reboot(void) |
| 90 | { |
| 91 | if (pci_read_config8(SNMIC, 0x56) & (1 << 1)) { |
Stefan Reinauer | 65b72ab | 2015-01-05 12:59:54 -0800 | [diff] [blame] | 92 | printk(BIOS_DEBUG, "Auto-reboot is disabled in hardware\n"); |
Alexandru Gagniuc | 88a3023 | 2013-06-04 23:37:56 -0500 | [diff] [blame] | 93 | return; |
| 94 | } |
| 95 | /* Disable the GP3 timer, which is the root of all evil */ |
| 96 | pci_write_config8(LPC, 0x98, 0); |
| 97 | /* Yep, that's all it takes */ |
Stefan Reinauer | 65b72ab | 2015-01-05 12:59:54 -0800 | [diff] [blame] | 98 | printk(BIOS_DEBUG, "GP3 timer disabled." |
Alexandru Gagniuc | 88a3023 | 2013-06-04 23:37:56 -0500 | [diff] [blame] | 99 | " Auto-reboot should not give you any more trouble.\n"); |
| 100 | } |
| 101 | |
| 102 | /** |
| 103 | * \brief Disables 'shadowing' of system ROM |
| 104 | * |
| 105 | * Disable unnecessary shadowing of the ROM in the first 1MB of address space. |
| 106 | * Coreboot runs in 32-bit mode from the start. Shadowing only gets in the way. |
| 107 | * This function frees the entire 640k-1M range for DRAM. VGA may still use |
| 108 | * the 640k-768k range, if enabled later. |
| 109 | */ |
| 110 | void vx900_disable_legacy_rom_shadow(void) |
| 111 | { |
| 112 | pci_write_config8(MCU, 0x80, 0xff); /* LPC ROM 768k - 832k */ |
| 113 | pci_write_config8(MCU, 0x81, 0xff); /* LPC ROM 832k - 896k */ |
| 114 | pci_write_config8(MCU, 0x82, 0xff); /* LPC ROM 896k - 960k */ |
| 115 | /* LPC ROM 960k - 1M * SMRAM: 640k - 768k */ |
| 116 | pci_write_config8(MCU, 0x83, 0x31); |
| 117 | |
| 118 | /* Bits 6:0 are the ROM shadow on top of 4G, so leave those untouched */ |
| 119 | pci_mod_config8(LPC, 0x41, 1 << 7, 0); /* LPC ROM 896k - 960k */ |
| 120 | |
| 121 | pci_write_config8(SNMIC, 0x61, 0); /* 768k - 832k */ |
| 122 | pci_write_config8(SNMIC, 0x62, 0); /* 832k - 896k */ |
| 123 | pci_write_config8(SNMIC, 0x63, 0); /* 896k - 1M */ |
| 124 | pci_write_config8(SNMIC, 0x64, 0); /* 896k - 960k */ |
| 125 | } |
| 126 | |
| 127 | /** |
| 128 | * \brief Disables the VX900 integrated graphics controller |
| 129 | * |
| 130 | * Disable the graphics controller entirely. It will no longer be visible as a |
| 131 | * PCI device. |
| 132 | */ |
| 133 | void vx900_disable_gfx(void) |
| 134 | { |
| 135 | /* Disable GFX */ |
| 136 | pci_mod_config8(MCU, 0xa1, 1 << 7, 0); |
| 137 | } |