Alexandru Gagniuc | 88a3023 | 2013-06-04 23:37:56 -0500 | [diff] [blame] | 1 | /* |
| 2 | * This file is part of the coreboot project. |
| 3 | * |
| 4 | * Copyright (C) 2012 Alexandru Gagniuc <mr.nuke.me@gmail.com> |
| 5 | * |
| 6 | * This program is free software: you can redistribute it and/or modify |
| 7 | * it under the terms of the GNU General Public License as published by |
| 8 | * the Free Software Foundation, either version 2 of the License, or |
| 9 | * (at your option) any later version. |
| 10 | * |
| 11 | * This program is distributed in the hope that it will be useful, |
| 12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 14 | * GNU General Public License for more details. |
Alexandru Gagniuc | 88a3023 | 2013-06-04 23:37:56 -0500 | [diff] [blame] | 15 | */ |
| 16 | |
| 17 | #include "early_vx900.h" |
| 18 | |
| 19 | static void vx900_cpu_bus_preram_setup(void) |
| 20 | { |
| 21 | /* Faster CPU to DRAM Cycle */ |
| 22 | pci_mod_config8(HOST_BUS, 0x50, 0x0f, 0x08); |
| 23 | /* CPU Interface Control – Basic Options */ |
| 24 | pci_mod_config8(HOST_BUS, 0x51, 0, 0x6c); |
| 25 | /*CPU Interface Control – Advanced Options */ |
| 26 | pci_write_config8(HOST_BUS, 0x52, 0xc7); |
| 27 | /* Enable 8QW burst and 4QW request merging [4] and [2] |
| 28 | * and special mode for read cycles bit[3] */ |
| 29 | pci_mod_config8(HOST_BUS, 0x54, 0, (1 << 4) | (1 << 2) | (1 << 3)); |
| 30 | /* High priority upstream requests on V4 bus */ |
| 31 | pci_write_config8(HOST_BUS, 0x56, 0x03); |
| 32 | /* CPU to DRAM extra 1T access control */ |
| 33 | pci_mod_config8(HOST_BUS, 0x59, 0x00, (1 << 2)); |
| 34 | /* Queue reordering */ |
| 35 | pci_mod_config8(HOST_BUS, 0x5f, 0x00, (1 << 6)); |
| 36 | /* Only Write cycle of CPU->GFXCTL will flush the CPU->Memory FIFO */ |
| 37 | pci_mod_config8(HOST_BUS, 0x98, 0x00, 0x60); |
| 38 | /* 1T delay for data on CPU bus */ |
| 39 | pci_write_config8(HOST_BUS, 0x9e, 0x0e); |
| 40 | /* Arbitrate ownership of DRAM controller a few cycles earlier */ |
| 41 | pci_mod_config8(HOST_BUS, 0x9f, 0x00, (1 << 7)); |
| 42 | /* Write retire policy */ |
| 43 | pci_write_config8(HOST_BUS, 0x5d, 0xa2); |
| 44 | /* Occupancy timer */ |
| 45 | pci_write_config8(HOST_BUS, 0x53, 0x44); |
| 46 | /* Medium Threshold for Write Retire Policy - 6 requests */ |
| 47 | pci_mod_config8(HOST_BUS, 0x56, 0x00, 0x60); |
| 48 | /* Bandwidth timer */ |
| 49 | pci_write_config8(HOST_BUS, 0x5e, 0x44); |
| 50 | } |
| 51 | |
| 52 | /** |
| 53 | * \brief Configure the CPU to northbridge bus (formerly, FSB) |
| 54 | * |
| 55 | * Configure the CPU <-> host interface. This interface is complex and needs to |
| 56 | * be set up to operate properly. Configured parameters include bandwidth |
| 57 | * arbitration. This function does not, however, change the physical interface |
| 58 | * parameters, such as drive strength and signal timing. Instead, it assumes |
| 59 | * that those parameters were already configured correctly from the ROMSTRAP. |
| 60 | */ |
| 61 | void vx900_cpu_bus_interface_setup(void) |
| 62 | { |
| 63 | vx900_cpu_bus_preram_setup(); |
| 64 | |
| 65 | dump_pci_device(HOST_BUS); |
| 66 | } |