Bari Ari | 612163e3 | 2009-05-27 13:12:42 +0000 | [diff] [blame] | 1 | /* |
| 2 | * This file is part of the coreboot project. |
| 3 | * |
| 4 | * Copyright (C) 2009 One Laptop per Child, Association, Inc. |
| 5 | * |
| 6 | * This program is free software; you can redistribute it and/or modify |
| 7 | * it under the terms of the GNU General Public License as published by |
| 8 | * the Free Software Foundation; version 2 of the License. |
| 9 | * |
| 10 | * This program is distributed in the hope that it will be useful, |
| 11 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 12 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 13 | * GNU General Public License for more details. |
Bari Ari | 612163e3 | 2009-05-27 13:12:42 +0000 | [diff] [blame] | 14 | */ |
| 15 | |
| 16 | /* |
| 17 | part of this file is from cx700 port, part of is from cn700 port, |
| 18 | */ |
| 19 | |
| 20 | #include <console/console.h> |
| 21 | #include <arch/io.h> |
| 22 | #include <stdint.h> |
| 23 | #include <device/device.h> |
| 24 | #include <device/pci.h> |
| 25 | #include <device/pci_ids.h> |
| 26 | #include <stdlib.h> |
| 27 | #include <string.h> |
Bari Ari | 612163e3 | 2009-05-27 13:12:42 +0000 | [diff] [blame] | 28 | #include <cpu/cpu.h> |
Bari Ari | 612163e3 | 2009-05-27 13:12:42 +0000 | [diff] [blame] | 29 | #include "vx800.h" |
| 30 | |
Myles Watson | bd4f2f8 | 2009-07-02 21:19:33 +0000 | [diff] [blame] | 31 | /* !!FIXME!! This was meant to be a CONFIG option */ |
| 32 | #define VIACONFIG_TOP_SM_SIZE_MB 32 // Set frame buffer 32M for default |
| 33 | /* !!FIXME!! I declared this to fix the build. */ |
| 34 | u8 acpi_sleep_type = 0; |
| 35 | |
Bari Ari | 612163e3 | 2009-05-27 13:12:42 +0000 | [diff] [blame] | 36 | static void memctrl_init(device_t dev) |
| 37 | { |
| 38 | /* |
Uwe Hermann | 8341f44 | 2009-05-27 13:46:37 +0000 | [diff] [blame] | 39 | set VGA in uma_ram_setting.c, not in this function. |
Bari Ari | 612163e3 | 2009-05-27 13:12:42 +0000 | [diff] [blame] | 40 | */ |
| 41 | #if 0 |
| 42 | pci_write_config8(dev, 0x85, 0x20); |
| 43 | pci_write_config8(dev, 0x86, 0x2d); |
| 44 | |
| 45 | /* Set up VGA timers */ |
| 46 | pci_write_config8(dev, 0xa2, 0x44); |
| 47 | |
| 48 | /* Enable VGA with a 32mb framebuffer */ |
| 49 | pci_write_config16(dev, 0xa0, 0xd000); |
| 50 | |
| 51 | pci_write_config16(dev, 0xa4, 0x0010); |
| 52 | |
| 53 | //b0: 60 aa aa 5a 0f 00 00 00 08 |
| 54 | pci_write_config16(dev, 0xb0, 0xaa00); |
| 55 | pci_write_config8(dev, 0xb8, 0x08); |
| 56 | #endif |
| 57 | } |
| 58 | |
| 59 | static const struct device_operations memctrl_operations = { |
Edward O'Callaghan | d204073 | 2014-10-31 08:26:21 +1100 | [diff] [blame] | 60 | .read_resources = DEVICE_NOOP, |
Bari Ari | 612163e3 | 2009-05-27 13:12:42 +0000 | [diff] [blame] | 61 | .init = memctrl_init, |
| 62 | }; |
| 63 | |
| 64 | static const struct pci_driver memctrl_driver __pci_driver = { |
| 65 | .ops = &memctrl_operations, |
| 66 | .vendor = PCI_VENDOR_ID_VIA, |
| 67 | .device = PCI_DEVICE_ID_VIA_VX855_MEMCTRL, |
| 68 | }; |
| 69 | |
Bari Ari | 612163e3 | 2009-05-27 13:12:42 +0000 | [diff] [blame] | 70 | static void pci_domain_set_resources(device_t dev) |
| 71 | { |
Stefan Reinauer | 14e2277 | 2010-04-27 06:56:47 +0000 | [diff] [blame] | 72 | /* |
Bari Ari | 612163e3 | 2009-05-27 13:12:42 +0000 | [diff] [blame] | 73 | * the order is important to find the correct ram size. |
| 74 | */ |
| 75 | u8 ramregs[] = { 0x43, 0x42, 0x41, 0x40 }; |
| 76 | device_t mc_dev; |
| 77 | u32 pci_tolm; |
| 78 | u8 reg; |
| 79 | |
Stefan Reinauer | c02b4fc | 2010-03-22 11:42:32 +0000 | [diff] [blame] | 80 | printk(BIOS_SPEW, "Entering vx800 pci_domain_set_resources.\n"); |
Bari Ari | 612163e3 | 2009-05-27 13:12:42 +0000 | [diff] [blame] | 81 | |
Myles Watson | 894a347 | 2010-06-09 22:41:35 +0000 | [diff] [blame] | 82 | pci_tolm = find_pci_tolm(dev->link_list); |
Bari Ari | 612163e3 | 2009-05-27 13:12:42 +0000 | [diff] [blame] | 83 | mc_dev = dev_find_device(PCI_VENDOR_ID_VIA, |
| 84 | PCI_DEVICE_ID_VIA_VX855_MEMCTRL, 0); |
| 85 | |
| 86 | if (mc_dev) { |
| 87 | unsigned long tomk, tolmk; |
| 88 | unsigned char rambits; |
| 89 | u8 i, idx; |
| 90 | |
| 91 | /* |
| 92 | * once the register value is not zero, the ramsize is |
| 93 | * this register's value multiply 64 * 1024 * 1024 |
| 94 | */ |
| 95 | for (rambits = 0, i = 0; i < ARRAY_SIZE(ramregs); i++) { |
Bari Ari | 612163e3 | 2009-05-27 13:12:42 +0000 | [diff] [blame] | 96 | rambits = pci_read_config8(mc_dev, ramregs[i]); |
| 97 | if (rambits != 0) |
| 98 | break; |
| 99 | } |
| 100 | /* |
| 101 | Get memory size and frame buffer from northbridge's registers. |
| 102 | if register with invalid value we set frame buffer size to 32M for default, but it won't happen. |
| 103 | */ |
| 104 | reg = pci_read_config8(mc_dev, 0xa1); |
| 105 | reg &= 0x70; |
| 106 | reg = reg >> 4; |
| 107 | /* TOP 1M SM Memory */ |
| 108 | if (reg == 0x0) |
| 109 | tomk = (((rambits << 6) - 32 - VIACONFIG_TOP_SM_SIZE_MB) * 1024); // Set frame buffer 32M for default |
| 110 | else |
| 111 | tomk = |
| 112 | (((rambits << 6) - (4 << reg) - |
| 113 | VIACONFIG_TOP_SM_SIZE_MB) * 1024); |
| 114 | |
Myles Watson | 08e0fb8 | 2010-03-22 16:33:25 +0000 | [diff] [blame] | 115 | printk(BIOS_SPEW, "tomk is 0x%lx\n", tomk); |
Bari Ari | 612163e3 | 2009-05-27 13:12:42 +0000 | [diff] [blame] | 116 | /* Compute the Top Of Low Memory, in Kb */ |
| 117 | tolmk = pci_tolm >> 10; |
| 118 | if (tolmk >= tomk) { |
| 119 | /* The PCI hole does does not overlap the memory. */ |
| 120 | tolmk = tomk; |
| 121 | } |
| 122 | /* Report the memory regions */ |
| 123 | idx = 10; |
| 124 | /* TODO: Hole needed? */ |
| 125 | ram_resource(dev, idx++, 0, 640); /* first 640k */ |
| 126 | /* Leave a hole for vga, 0xa0000 - 0xc0000 */ |
| 127 | ram_resource(dev, idx++, 768, (tolmk - 768)); |
| 128 | } |
Myles Watson | 894a347 | 2010-06-09 22:41:35 +0000 | [diff] [blame] | 129 | assign_resources(dev->link_list); |
Bari Ari | 612163e3 | 2009-05-27 13:12:42 +0000 | [diff] [blame] | 130 | } |
| 131 | |
Stefan Reinauer | 56a684a | 2010-04-07 15:40:26 +0000 | [diff] [blame] | 132 | static struct device_operations pci_domain_ops = { |
Bari Ari | 612163e3 | 2009-05-27 13:12:42 +0000 | [diff] [blame] | 133 | .read_resources = pci_domain_read_resources, |
| 134 | .set_resources = pci_domain_set_resources, |
Vladimir Serbinenko | 6c71a68 | 2014-09-02 00:15:02 +0200 | [diff] [blame] | 135 | #if IS_ENABLED(CONFIG_HAVE_ACPI_TABLES) |
| 136 | .write_acpi_tables = acpi_write_hpet, |
| 137 | #endif |
Myles Watson | 7eac445 | 2010-06-17 16:16:56 +0000 | [diff] [blame] | 138 | .enable_resources = NULL, |
| 139 | .init = NULL, |
Bari Ari | 612163e3 | 2009-05-27 13:12:42 +0000 | [diff] [blame] | 140 | .scan_bus = pci_domain_scan_bus, |
Kyösti Mälkki | 33e5df3 | 2013-07-03 10:51:34 +0300 | [diff] [blame] | 141 | .ops_pci_bus = pci_bus_default_ops, |
Bari Ari | 612163e3 | 2009-05-27 13:12:42 +0000 | [diff] [blame] | 142 | }; |
| 143 | |
| 144 | static void cpu_bus_init(device_t dev) |
| 145 | { |
Myles Watson | 894a347 | 2010-06-09 22:41:35 +0000 | [diff] [blame] | 146 | initialize_cpus(dev->link_list); |
Bari Ari | 612163e3 | 2009-05-27 13:12:42 +0000 | [diff] [blame] | 147 | } |
| 148 | |
Stefan Reinauer | 56a684a | 2010-04-07 15:40:26 +0000 | [diff] [blame] | 149 | static struct device_operations cpu_bus_ops = { |
Edward O'Callaghan | d204073 | 2014-10-31 08:26:21 +1100 | [diff] [blame] | 150 | .read_resources = DEVICE_NOOP, |
| 151 | .set_resources = DEVICE_NOOP, |
| 152 | .enable_resources = DEVICE_NOOP, |
Bari Ari | 612163e3 | 2009-05-27 13:12:42 +0000 | [diff] [blame] | 153 | .init = cpu_bus_init, |
| 154 | .scan_bus = 0, |
| 155 | }; |
| 156 | |
| 157 | static void enable_dev(struct device *dev) |
| 158 | { |
Stefan Reinauer | c02b4fc | 2010-03-22 11:42:32 +0000 | [diff] [blame] | 159 | printk(BIOS_SPEW, "In VX800 enable_dev for device %s.\n", dev_path(dev)); |
Bari Ari | 612163e3 | 2009-05-27 13:12:42 +0000 | [diff] [blame] | 160 | |
| 161 | /* Set the operations if it is a special bus type */ |
Stefan Reinauer | 4aff445 | 2013-02-12 14:17:15 -0800 | [diff] [blame] | 162 | if (dev->path.type == DEVICE_PATH_DOMAIN) { |
Bari Ari | 612163e3 | 2009-05-27 13:12:42 +0000 | [diff] [blame] | 163 | dev->ops = &pci_domain_ops; |
Stefan Reinauer | 0aa37c4 | 2013-02-12 15:20:54 -0800 | [diff] [blame] | 164 | } else if (dev->path.type == DEVICE_PATH_CPU_CLUSTER) { |
Bari Ari | 612163e3 | 2009-05-27 13:12:42 +0000 | [diff] [blame] | 165 | dev->ops = &cpu_bus_ops; |
| 166 | } |
| 167 | } |
| 168 | |
| 169 | struct chip_operations northbridge_via_vx800_ops = { |
| 170 | CHIP_NAME("VIA VX800 Chipset") |
| 171 | .enable_dev = enable_dev, |
| 172 | }; |