Corey Osgood | bd3f93e | 2008-02-21 00:56:14 +0000 | [diff] [blame] | 1 | /* |
| 2 | * This file is part of the coreboot project. |
| 3 | * |
| 4 | * Copyright (C) 2007 Corey Osgood <corey.osgood@gmail.com> |
| 5 | * |
| 6 | * This program is free software; you can redistribute it and/or modify |
| 7 | * it under the terms of the GNU General Public License as published by |
| 8 | * the Free Software Foundation; either version 2 of the License, or |
| 9 | * (at your option) any later version. |
| 10 | * |
| 11 | * This program is distributed in the hope that it will be useful, |
| 12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 14 | * GNU General Public License for more details. |
Corey Osgood | bd3f93e | 2008-02-21 00:56:14 +0000 | [diff] [blame] | 15 | */ |
| 16 | |
| 17 | #include <console/console.h> |
| 18 | #include <arch/io.h> |
| 19 | #include <stdint.h> |
| 20 | #include <device/device.h> |
| 21 | #include <device/pci.h> |
| 22 | #include <device/pci_ids.h> |
Corey Osgood | bd3f93e | 2008-02-21 00:56:14 +0000 | [diff] [blame] | 23 | #include "northbridge.h" |
| 24 | #include "cn700.h" |
| 25 | |
| 26 | /* This is the main AGP device, and only one used when configured for AGP 2.0 */ |
| 27 | static void agp_init(device_t dev) |
| 28 | { |
| 29 | u32 reg32; |
Uwe Hermann | ea7b518 | 2008-10-09 17:08:32 +0000 | [diff] [blame] | 30 | |
| 31 | /* Some of this may not be necessary (should be handled by the OS). */ |
Stefan Reinauer | c02b4fc | 2010-03-22 11:42:32 +0000 | [diff] [blame] | 32 | printk(BIOS_DEBUG, "Enabling AGP.\n"); |
Uwe Hermann | ea7b518 | 2008-10-09 17:08:32 +0000 | [diff] [blame] | 33 | |
| 34 | /* Allow R/W access to AGP registers. */ |
Corey Osgood | bd3f93e | 2008-02-21 00:56:14 +0000 | [diff] [blame] | 35 | pci_write_config8(dev, 0x4d, 0x15); |
Uwe Hermann | ea7b518 | 2008-10-09 17:08:32 +0000 | [diff] [blame] | 36 | |
| 37 | /* Setup PCI latency timer. */ |
Corey Osgood | bd3f93e | 2008-02-21 00:56:14 +0000 | [diff] [blame] | 38 | pci_write_config8(dev, 0xd, 0x8); |
Uwe Hermann | ea7b518 | 2008-10-09 17:08:32 +0000 | [diff] [blame] | 39 | |
| 40 | /* |
| 41 | * Set to AGP 3.0 Mode, which should theoretically render the rest of |
| 42 | * the registers set here pointless. |
| 43 | */ |
Corey Osgood | bd3f93e | 2008-02-21 00:56:14 +0000 | [diff] [blame] | 44 | pci_write_config8(dev, 0x84, 0xb); |
Uwe Hermann | ea7b518 | 2008-10-09 17:08:32 +0000 | [diff] [blame] | 45 | |
Corey Osgood | bd3f93e | 2008-02-21 00:56:14 +0000 | [diff] [blame] | 46 | /* AGP Request Queue Size */ |
| 47 | pci_write_config8(dev, 0x4a, 0x1f); |
Uwe Hermann | ea7b518 | 2008-10-09 17:08:32 +0000 | [diff] [blame] | 48 | |
| 49 | /* |
| 50 | * AGP Hardware Support (default 0xc4) |
Corey Osgood | bd3f93e | 2008-02-21 00:56:14 +0000 | [diff] [blame] | 51 | * 7: AGP SBA Enable (1 to Enable) |
| 52 | * 6: AGP Enable |
| 53 | * 5: Reserved |
| 54 | * 4: Fast Write Enable |
| 55 | * 3: AGP8X Mode Enable |
| 56 | * 2: AGP4X Mode Enable |
| 57 | * 1: AGP2X Mode Enable |
Uwe Hermann | ea7b518 | 2008-10-09 17:08:32 +0000 | [diff] [blame] | 58 | * 0: AGP1X Mode Enable |
| 59 | */ |
Corey Osgood | bd3f93e | 2008-02-21 00:56:14 +0000 | [diff] [blame] | 60 | pci_write_config8(dev, 0x4b, 0xc4); |
Uwe Hermann | ea7b518 | 2008-10-09 17:08:32 +0000 | [diff] [blame] | 61 | |
Corey Osgood | bd3f93e | 2008-02-21 00:56:14 +0000 | [diff] [blame] | 62 | /* Enable AGP Backdoor */ |
| 63 | pci_write_config8(dev, 0xb5, 0x03); |
Uwe Hermann | ea7b518 | 2008-10-09 17:08:32 +0000 | [diff] [blame] | 64 | |
| 65 | /* Set aperture to 32 MB. */ |
| 66 | /* TODO: Use config option, explain how it works. */ |
Corey Osgood | bd3f93e | 2008-02-21 00:56:14 +0000 | [diff] [blame] | 67 | pci_write_config32(dev, 0x94, 0x00010f38); |
Uwe Hermann | ea7b518 | 2008-10-09 17:08:32 +0000 | [diff] [blame] | 68 | /* Set GART Table Base Address (31:12). */ |
Corey Osgood | bd3f93e | 2008-02-21 00:56:14 +0000 | [diff] [blame] | 69 | pci_write_config32(dev, 0x98, (0x1558 << 12)); |
Uwe Hermann | ea7b518 | 2008-10-09 17:08:32 +0000 | [diff] [blame] | 70 | /* Set AGP Aperture Base. */ |
Corey Osgood | bd3f93e | 2008-02-21 00:56:14 +0000 | [diff] [blame] | 71 | pci_write_config32(dev, 0x10, 0xf8000008); |
| 72 | |
Uwe Hermann | ea7b518 | 2008-10-09 17:08:32 +0000 | [diff] [blame] | 73 | /* Enable CPU/PMSTR GART Access. */ |
Corey Osgood | bd3f93e | 2008-02-21 00:56:14 +0000 | [diff] [blame] | 74 | reg32 = pci_read_config8(dev, 0xbf); |
| 75 | reg32 |= 0x80; |
| 76 | pci_write_config8(dev, 0xbf, reg32); |
Uwe Hermann | ea7b518 | 2008-10-09 17:08:32 +0000 | [diff] [blame] | 77 | |
Corey Osgood | bd3f93e | 2008-02-21 00:56:14 +0000 | [diff] [blame] | 78 | /* Enable AGP Aperture. */ |
| 79 | reg32 = pci_read_config32(dev, 0x94); |
| 80 | reg32 |= (3 << 7); |
| 81 | pci_write_config32(dev, 0x90, reg32); |
| 82 | |
| 83 | /* AGP Control */ |
| 84 | pci_write_config8(dev, 0xbc, 0x21); |
| 85 | pci_write_config8(dev, 0xbd, 0xd2); |
Uwe Hermann | ea7b518 | 2008-10-09 17:08:32 +0000 | [diff] [blame] | 86 | |
| 87 | /* |
| 88 | * AGP Pad, driving strength, and delay control. All this should be |
| 89 | * constant, seeing as the VGA controller is onboard. |
| 90 | */ |
Corey Osgood | bd3f93e | 2008-02-21 00:56:14 +0000 | [diff] [blame] | 91 | pci_write_config8(dev, 0x40, 0xc7); |
| 92 | pci_write_config8(dev, 0x41, 0xdb); |
| 93 | pci_write_config8(dev, 0x42, 0x10); |
| 94 | pci_write_config8(dev, 0x43, 0xdb); |
| 95 | pci_write_config8(dev, 0x44, 0x24); |
Uwe Hermann | ea7b518 | 2008-10-09 17:08:32 +0000 | [diff] [blame] | 96 | |
Corey Osgood | bd3f93e | 2008-02-21 00:56:14 +0000 | [diff] [blame] | 97 | /* AGPC CKG Control */ |
| 98 | pci_write_config8(dev, 0xc0, 0x02); |
| 99 | pci_write_config8(dev, 0xc1, 0x02); |
| 100 | } |
| 101 | |
| 102 | static const struct device_operations agp_operations = { |
Edward O'Callaghan | d204073 | 2014-10-31 08:26:21 +1100 | [diff] [blame] | 103 | .read_resources = DEVICE_NOOP, |
Corey Osgood | bd3f93e | 2008-02-21 00:56:14 +0000 | [diff] [blame] | 104 | .set_resources = pci_dev_set_resources, |
| 105 | .enable_resources = pci_dev_enable_resources, |
| 106 | .init = agp_init, |
| 107 | .ops_pci = 0, |
| 108 | }; |
| 109 | |
| 110 | static const struct pci_driver agp_driver __pci_driver = { |
Uwe Hermann | ea7b518 | 2008-10-09 17:08:32 +0000 | [diff] [blame] | 111 | .ops = &agp_operations, |
Corey Osgood | bd3f93e | 2008-02-21 00:56:14 +0000 | [diff] [blame] | 112 | .vendor = PCI_VENDOR_ID_VIA, |
| 113 | .device = PCI_DEVICE_ID_VIA_CN700_AGP, |
| 114 | }; |
| 115 | |
Uwe Hermann | ea7b518 | 2008-10-09 17:08:32 +0000 | [diff] [blame] | 116 | /* |
| 117 | * This is the AGP 3.0 "bridge" @Bus 0 Device 1 Func 0. When using AGP 3.0, the |
| 118 | * config in this device takes presidence. We configure both just to be safe. |
| 119 | */ |
Corey Osgood | bd3f93e | 2008-02-21 00:56:14 +0000 | [diff] [blame] | 120 | static void agp_bridge_init(device_t dev) |
| 121 | { |
Stefan Reinauer | c02b4fc | 2010-03-22 11:42:32 +0000 | [diff] [blame] | 122 | printk(BIOS_DEBUG, "Setting up AGP bridge device\n"); |
Uwe Hermann | ea7b518 | 2008-10-09 17:08:32 +0000 | [diff] [blame] | 123 | |
Corey Osgood | bd3f93e | 2008-02-21 00:56:14 +0000 | [diff] [blame] | 124 | pci_write_config16(dev, 0x4, 0x0007); |
| 125 | |
| 126 | /* Secondary Bus Number */ |
| 127 | pci_write_config8(dev, 0x19, 0x01); |
| 128 | /* Subordinate Bus Number */ |
| 129 | pci_write_config8(dev, 0x1a, 0x01); |
Uwe Hermann | ea7b518 | 2008-10-09 17:08:32 +0000 | [diff] [blame] | 130 | /* I/O Base */ |
Corey Osgood | bd3f93e | 2008-02-21 00:56:14 +0000 | [diff] [blame] | 131 | pci_write_config8(dev, 0x1c, 0xd0); |
Uwe Hermann | ea7b518 | 2008-10-09 17:08:32 +0000 | [diff] [blame] | 132 | /* I/O Limit */ |
Corey Osgood | bd3f93e | 2008-02-21 00:56:14 +0000 | [diff] [blame] | 133 | pci_write_config8(dev, 0x1d, 0xd0); |
Uwe Hermann | ea7b518 | 2008-10-09 17:08:32 +0000 | [diff] [blame] | 134 | |
Corey Osgood | bd3f93e | 2008-02-21 00:56:14 +0000 | [diff] [blame] | 135 | /* Memory Base */ |
| 136 | pci_write_config16(dev, 0x20, 0xfb00); |
| 137 | /* Memory Limit */ |
| 138 | pci_write_config16(dev, 0x22, 0xfcf0); |
| 139 | /* Prefetchable Memory Base */ |
| 140 | pci_write_config16(dev, 0x24, 0xf400); |
| 141 | /* Prefetchable Memory Limit */ |
| 142 | pci_write_config16(dev, 0x26, 0xf7f0); |
| 143 | /* Enable VGA Compatible Memory/IO Range */ |
| 144 | pci_write_config8(dev, 0x3e, 0x08); |
| 145 | |
| 146 | /* Second PCI Bus Control (see datasheet) */ |
| 147 | pci_write_config8(dev, 0x40, 0x83); |
| 148 | pci_write_config8(dev, 0x41, 0x43); |
| 149 | pci_write_config8(dev, 0x42, 0xe2); |
| 150 | pci_write_config8(dev, 0x43, 0x44); |
| 151 | pci_write_config8(dev, 0x44, 0x34); |
| 152 | pci_write_config8(dev, 0x45, 0x72); |
| 153 | } |
| 154 | |
| 155 | static const struct device_operations agp_bridge_operations = { |
Edward O'Callaghan | d204073 | 2014-10-31 08:26:21 +1100 | [diff] [blame] | 156 | .read_resources = DEVICE_NOOP, |
Corey Osgood | bd3f93e | 2008-02-21 00:56:14 +0000 | [diff] [blame] | 157 | .set_resources = pci_dev_set_resources, |
| 158 | .enable_resources = pci_bus_enable_resources, |
| 159 | .init = agp_bridge_init, |
| 160 | .scan_bus = pci_scan_bridge, |
| 161 | .ops_pci = 0, |
| 162 | }; |
| 163 | |
| 164 | static const struct pci_driver agp_bridge_driver __pci_driver = { |
Uwe Hermann | ea7b518 | 2008-10-09 17:08:32 +0000 | [diff] [blame] | 165 | .ops = &agp_bridge_operations, |
Corey Osgood | bd3f93e | 2008-02-21 00:56:14 +0000 | [diff] [blame] | 166 | .vendor = PCI_VENDOR_ID_VIA, |
| 167 | .device = PCI_DEVICE_ID_VIA_CN700_BRIDGE, |
| 168 | }; |