Patrick Georgi | be61a17 | 2010-12-18 07:48:43 +0000 | [diff] [blame] | 1 | /* |
| 2 | * This file is part of the coreboot project. |
| 3 | * |
| 4 | * Copyright (C) 2009-2010 iWave Systems |
| 5 | * |
| 6 | * This program is free software; you can redistribute it and/or modify |
| 7 | * it under the terms of the GNU General Public License as published by |
| 8 | * the Free Software Foundation; version 2 of the License. |
| 9 | * |
| 10 | * This program is distributed in the hope that it will be useful, |
| 11 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 12 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 13 | * GNU General Public License for more details. |
Patrick Georgi | be61a17 | 2010-12-18 07:48:43 +0000 | [diff] [blame] | 14 | */ |
| 15 | |
| 16 | #ifndef RAMINIT_H |
| 17 | #define RAMINIT_H |
| 18 | |
| 19 | /** |
| 20 | * Bit Equates |
| 21 | **/ |
| 22 | #define BIT(x) (1<<x) |
| 23 | |
Elyes HAOUAS | 23fa3c2 | 2014-07-22 22:53:06 +0200 | [diff] [blame] | 24 | #define EBP_TRP_MASK (BIT(1) | BIT(0)) |
| 25 | #define TRP_LOW 3h |
| 26 | #define TRP_HIGH 5h |
| 27 | #define EBP_TRP_OFFSET 0 /* Start of TRP field in EBP*/ |
| 28 | #define EBP_TRCD_MASK (BIT(3) | BIT(2)) |
| 29 | #define TRCD_LOW 3h |
| 30 | #define TRCD_HIGH 5h |
| 31 | #define EBP_TRCD_OFFSET 2 /* Start of TRCD field in EBP*/ |
| 32 | #define EBP_TCL_MASK (BIT(5) | BIT(4)) |
| 33 | #define TCL_LOW 3 /* Minimum supported CL*/ |
| 34 | #define TCL_HIGH 5 /* Maximum supported CL*/ |
| 35 | #define EBP_TCL_OFFSET 4 /* EBP bit( )for CL mask*/ |
| 36 | #define EBP_DDR2_CL_5_0 BIT(5) /* CL 5.0 = 10b*/ |
| 37 | #define EBP_DDR2_CL_4_0 BIT(4) /* CL 4.0 = 01b*/ |
| 38 | #define EBP_DDR2_CL_3_0 00h /* CL 3.0 = 00b*/ |
| 39 | #define EBP_FREQ_MASK (BIT(10)| BIT(9)) |
| 40 | #define EBP_FREQ_OFFSET 9 /* EBP bit( )for frequency mask*/ |
| 41 | #define EBP_FREQ_400 0 /* 400MHz EBP[10:9] = 00b*/ |
| 42 | #define EBP_FREQ_533 BIT(9) /* 533MHz EBP[10:9] = 01b*/ |
| 43 | #define EBP_REFRESH_MASK (BIT(12)| BIT(11)) |
| 44 | #define EBP_REFRESH_OFFSET 11 /* Bit offset of refresh field*/ |
| 45 | #define EBP_REF_DIS 00h /* Mask for refresh disabled*/ |
| 46 | #define EBP_REF_128CLK BIT(11) /* Mask for 128 clks referesh rate*/ |
| 47 | #define EBP_REF_3_9 BIT(12) /* Mask for 3.9us refresh rate*/ |
| 48 | #define EBP_REF_7_8 (BIT(12)| BIT(11))/* Mask for 7.8us refresh rate*/ |
| 49 | #define EBP_WIDTH_MASK BIT(15) |
| 50 | #define EBP_WIDTH_OFFSET 15 /* Bit offset of EBP width field*/ |
| 51 | #define EBP_SOCKET_X16 BIT(15) /* Bit mask of x8/x16 bit*/ |
| 52 | #define EBP_DENSITY_MASK (BIT(17)| BIT(16)) |
| 53 | #define EBP_DENSITY_OFFSET 16 |
| 54 | #define EBP_DENSITY_512 BIT(16) /* 512Mbit density*/ |
| 55 | #define EBP_DENSITY_1024 BIT(17) /* 1024Mbit density*/ |
| 56 | #define EBP_DENSITY_2048 (BIT(17)| BIT(16))/* 2048Mbit density*/ |
| 57 | #define EBP_RANKS_MASK BIT(18) |
| 58 | #define EBP_RANKS_OFFSET 18 |
| 59 | #define EBP_RANKS BIT(18) /* Bit offset of # of ranks bit*/ |
| 60 | #define EBP_PACKAGE_TYPE BIT(19) /* Package type (stacked or not)*/ |
| 61 | #define EBP_2X_MASK BIT(20) |
| 62 | #define EBP_2X_OFFSET 20 /* Bit offset of ebp 2x refresh field*/ |
| 63 | #define EBP_2X_AUTO_REFRESH BIT(20) /* Bit mask of 2x refresh field*/ |
| 64 | #define EBP_DRAM_PARM_MASK BIT(21) |
| 65 | #define EBP_DRAM_PARM_OFFSET 21 |
| 66 | #define EBP_DRAM_PARM_SPD 0 /* Use SPD to get DRAM parameters*/ |
| 67 | #define EBP_DRAM_PARM_CMC BIT(21) /* DRAM parameters in CMC binary*/ |
| 68 | #define EBP_BOOT_PATH BIT(31) |
Patrick Georgi | be61a17 | 2010-12-18 07:48:43 +0000 | [diff] [blame] | 69 | |
| 70 | |
| 71 | |
| 72 | |
| 73 | #define HB_REG_MCR 0xD0 /* Message Control Register */ |
| 74 | #define HB_REG_MCR_OP_OFFSET 24 /* Offset of the opcode field in MCR */ |
| 75 | #define HB_REG_MCR_PORT_OFFSET 16 /* Offset of the port field in MCR */ |
| 76 | #define HB_REG_MCR_REG_OFFSET 8 /* Offset of the register field in MCR */ |
| 77 | #define HB_REG_MDR 0xD4 /* Message Data Register */ |
| 78 | |
| 79 | /* SCH Message OpCodes and Attributes*/ |
| 80 | #define SCH_OPCODE_WAKEFULLON 0x2 /* SCH message bus "Wake Full On" opcode*/ |
| 81 | #define SCH_OPCODE_DRAMINIT 0xA0 /* SCH message bus "DRAM Init" opcode */ |
| 82 | #define SCH_DRAMINIT_CMD_MRS 0x4000 /* MRS command */ |
| 83 | #define SCH_DRAMINIT_CMD_EMRS1 0x8 /* EMRS 1 command */ |
| 84 | #define SCH_DRAMINIT_CMD_EMRS2 0x10 /* EMRS 2 command */ |
| 85 | #define SCH_DRAMINIT_CMD_EMRS3 0x18 /* EMRS 3 command */ |
| 86 | #define SCH_DRAMINIT_CMD_CBR 0x1 /* CBR command */ |
| 87 | #define SCH_DRAMINIT_CMD_AREF 0x10001 /* Refresh command, MA10=0->All */ |
| 88 | #define SCH_DRAMINIT_CMD_PALL 0x10002 /* Precharge command, MA10=1->All */ |
| 89 | #define SCH_DRAMINIT_CMD_BACT 0x3 /* Bank activate command */ |
| 90 | #define SCH_DRAMINIT_CMD_NOP 0x7 /* NOP command */ |
| 91 | #define SCH_DRAMINIT_RANK_OFFSET 21 /* Offset of the rank selection bit */ |
| 92 | #define SCH_DRAMINIT_RANK_MASK BIT(21) |
| 93 | #define SCH_DRAMINIT_ADDR_OFFSET 6 /* Offset of the address field in MDR */ |
| 94 | #define SCH_DRAMINIT_INTLV BIT(3) /* Interleave burst type */ |
| 95 | #define SCH_DRAMINIT_BL4 2 /* Burst Length = 4 */ |
| 96 | #define SCH_DRAMINIT_CL_OFFSET 4 /* CAS Latency bit offset */ |
| 97 | #define SCH_DRAMINIT_OCD_DEFAULT 0xE000 /* OCD Default command */ |
| 98 | #define SCH_DRAMINIT_DQS_DIS BIT(16) /* DQS Disable command */ |
| 99 | #define SCH_OPCODE_READ 0xD0 /* SCH message bus "read" opcode */ |
| 100 | #define SCH_OPCODE_WRITE 0xE0 /* SCH message bus "write" opcode */ |
| 101 | |
| 102 | /* SCH Message Ports and Registers*/ |
| 103 | |
Elyes HAOUAS | 23fa3c2 | 2014-07-22 22:53:06 +0200 | [diff] [blame] | 104 | #define SCH_MSG_DUNIT_PORT 0x1 /* DRAM unit port */ |
| 105 | #define SCH_MSG_DUNIT_REG_DRP 0x0 /* DRAM Rank Population and Interface */ |
| 106 | #define DRP_FIELDS 0xFF /* Pertinent fields in DRP */ |
| 107 | #define DRP_RANK0_OFFSET 3 /* Rank 0 enable offset */ |
| 108 | #define DRP_RANK1_OFFSET 7 /* Rank 1 enable offset */ |
| 109 | #define DRP_DENSITY0_OFFSET 1 /* Density offset - Rank 0 */ |
| 110 | #define DRP_DENSITY1_OFFSET 5 /* Density offset - Rank 1 */ |
| 111 | #define DRP_WIDTH0_OFFSET 0 /* Width offset - Rank 0 */ |
| 112 | #define DRP_WIDTH1_OFFSET 4 /* Width offset - Rank 1 */ |
| 113 | #define DRP_CKE_DIS (BIT(14)| BIT(13)) /* CKE disable bits for both ranks */ |
| 114 | #define DRP_CKE_DIS0 BIT(13) /* CKE disable bit - Rank 0 */ |
| 115 | #define DRP_CKE_DIS1 BIT(14) /* CKE disable bit - Rank 1 */ |
| 116 | #define DRP_SCK_DIS (BIT(11)| BIT(10)) /* SCK/SCKB disable bits */ |
| 117 | #define DRP_SCK_DIS1 BIT(11) /* SCK[1]/SCKB[1] disable */ |
| 118 | #define DRP_SCK_DIS0 BIT(10) /* SCK[0]/SCKB[0] disable */ |
| 119 | #define SCH_MSG_DUNIT_REG_DTR 0x01 /* DRAM Timing Register */ |
| 120 | #define DTR_FIELDS 0x3F /* Pertinent fields in DTR */ |
| 121 | #define DTR_TCL_OFFSET 4 /* CAS latency offset */ |
| 122 | #define DTR_TRCD_OFFSET 2 /* RAS CAS Delay Offset */ |
| 123 | #define DTR_TRP_OFFSET 0 /* RAS Precharge Delay Offset */ |
| 124 | #define SCH_MSG_DUNIT_REG_DCO 0x2 /* DRAM Control Register */ |
| 125 | #define DCO_FIELDS 0xF /* Pertinent fields in DCO */ |
| 126 | #define DCO_REFRESH_OFFSET 2 /* Refresh Rate Field Offset */ |
| 127 | #define DCO_FREQ_OFFSET 0 /* DRAM Frequency Field Offset */ |
| 128 | #define DCO_IC BIT(7) /* Initialization complete bit */ |
| 129 | #define SCH_MSG_PUNIT_PORT 04h /* Punit Port */ |
| 130 | #define SCH_MSG_PUNIT_REG_PCR 71h /* Punit Control Register */ |
| 131 | #define SCH_MSG_TEST_PORT 05h /* Test port */ |
| 132 | #define SCH_MSG_TEST_REG_MSR 03h /* Mode and Status Register */ |
Patrick Georgi | be61a17 | 2010-12-18 07:48:43 +0000 | [diff] [blame] | 133 | |
| 134 | |
| 135 | /* Jedec initialization mapping into the MDR address field for DRAM init messages*/ |
| 136 | |
| 137 | |
| 138 | #define SCH_JEDEC_DLLRESET BIT(8) /* DLL Reset bit( ) */ |
| 139 | #define SCH_JEDEC_INTLV BIT(3) /* Interleave/NOT(Sequential) bit( ) */ |
| 140 | #define SCH_JEDEC_CL_OFFSET 4 /* Offset of the CAS latency field */ |
| 141 | #define SCH_JEDEC_OCD_DEFAULT (BIT(7)| BIT(8)| BIT(9)) /* OCD default value */ |
| 142 | #define SCH_JEDEC_DQS_DIS BIT(10) /* DQS disable bit */ |
| 143 | #define SCH_JEDEC_BL4 BIT(1) /* Burst length 4 value */ |
| 144 | /*static values used during JEDEC iniatialization. These values are not |
| 145 | dependent on memory or chipset configuration.*/ |
| 146 | #define JEDEC_STATIC_PARAM ((SCH_JEDEC_INTLV << SCH_DRAMINIT_ADDR_OFFSET) + (SCH_JEDEC_BL4 << SCH_DRAMINIT_ADDR_OFFSET)) |
| 147 | |
| 148 | #define DIMM_SOCKETS 2 |
| 149 | |
| 150 | #define DIMM_SPD_BASE 0x50 |
| 151 | #define DIMM_TCO_BASE 0x30 |
| 152 | |
| 153 | /* Burst length is always 8 */ |
| 154 | #define BURSTLENGTH 8 |
| 155 | #define RAM_PARAM_SOURCE_SOFTSTRAP 1 |
| 156 | #define RAM_PARAM_SOURCE_SPD 0 |
| 157 | struct sys_info { |
| 158 | |
| 159 | u16 memory_frequency; /* 400 or 533*/ |
| 160 | u16 fsb_frequency; /* 400 or 533*/ |
| 161 | |
| 162 | u8 trp; /*3,4,5 DRAM clocks */ |
| 163 | u8 trcd; /*3,4,5 DRAM clocks */ |
| 164 | u8 cl; /*CAS Latency 3,4,5*/ |
| 165 | |
| 166 | u8 refresh; /*Refresh rate disabled,128 DRAM clocks,3.9us,7.8us */ |
| 167 | |
| 168 | u8 data_width; /*x8/x16 data width */ |
| 169 | u8 device_density; /*SDRAM Device Density 512/1024/2048Mbit */ |
| 170 | u8 ranks; /*Single/Double */ |
| 171 | u8 ram_param_source; /*DRAM Parameter Source SPD/SoftStraps(R) Block (down memory) */ |
| 172 | u8 boot_path; |
| 173 | |
| 174 | } __attribute__ ((packed)); |
| 175 | |
| 176 | void sdram_initialize(int boot_mode); |
| 177 | |
| 178 | #endif /* RAMINIT_H */ |