Damien Zammit | f7060f1 | 2015-11-14 00:59:21 +1100 | [diff] [blame] | 1 | /* |
| 2 | * This file is part of the coreboot project. |
| 3 | * |
| 4 | * Copyright (C) 2015 Damien Zammit <damien@zamaudio.com> |
| 5 | * |
| 6 | * This program is free software; you can redistribute it and/or |
| 7 | * modify it under the terms of the GNU General Public License as |
| 8 | * published by the Free Software Foundation; either version 2 of |
| 9 | * the License, or (at your option) any later version. |
| 10 | * |
| 11 | * This program is distributed in the hope that it will be useful, |
| 12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 14 | * GNU General Public License for more details. |
| 15 | */ |
| 16 | |
| 17 | #include <stdint.h> |
| 18 | #include <stdlib.h> |
| 19 | #include <console/console.h> |
| 20 | #include <arch/io.h> |
| 21 | #include <device/pci_def.h> |
| 22 | #include <cbmem.h> |
| 23 | #include <halt.h> |
| 24 | #include <string.h> |
| 25 | #include <northbridge/intel/pineview/pineview.h> |
| 26 | |
| 27 | #define LPC PCI_DEV(0, 0x1f, 0) |
| 28 | #define D0F0 PCI_DEV(0, 0, 0) |
| 29 | |
| 30 | static void pineview_setup_bars(void) |
| 31 | { |
| 32 | u8 reg8; |
| 33 | u16 reg16; |
| 34 | u32 reg32; |
| 35 | |
| 36 | /* Setting up Southbridge. In the northbridge code. */ |
| 37 | printk(BIOS_DEBUG, "Setting up static southbridge registers..."); |
| 38 | pci_write_config32(LPC, RCBA, (uintptr_t)DEFAULT_RCBA | 1); |
| 39 | pci_write_config32(LPC, PMBASE, DEFAULT_PMBASE | 1); |
| 40 | pci_write_config8(LPC, 0x44 /* ACPI_CNTL */ , 0x80); /* Enable ACPI */ |
| 41 | pci_write_config32(LPC, GPIOBASE, DEFAULT_GPIOBASE | 1); |
| 42 | pci_write_config8(LPC, 0x4c /* GC */ , 0x10); /* Enable GPIOs */ |
| 43 | pci_write_config32(LPC, 0x88, 0x007c0291); |
| 44 | |
| 45 | pci_write_config32(PCI_DEV(0, 0x1e, 0), 0x1b, 0x20); |
| 46 | printk(BIOS_DEBUG, " done.\n"); |
| 47 | |
| 48 | printk(BIOS_DEBUG, "Disabling Watchdog reboot..."); |
| 49 | RCBA32(GCS) = RCBA32(GCS) | (1 << 5); /* No reset */ |
| 50 | outw((1 << 11), DEFAULT_PMBASE | 0x60 | 0x08); /* halt timer */ |
| 51 | printk(BIOS_DEBUG, " done.\n"); |
| 52 | |
| 53 | /* Enable upper 128bytes of CMOS */ |
| 54 | RCBA32(0x3400) = (1 << 2); |
| 55 | |
| 56 | printk(BIOS_DEBUG, "Setting up static northbridge registers..."); |
| 57 | pci_write_config8(D0F0, 0x8, 0x69); |
| 58 | |
| 59 | /* Set up all hardcoded northbridge BARs */ |
| 60 | pci_write_config32(D0F0, EPBAR, DEFAULT_EPBAR | 1); |
| 61 | pci_write_config32(D0F0, MCHBAR, (uintptr_t)DEFAULT_MCHBAR | 1); |
| 62 | pci_write_config32(D0F0, DMIBAR, (uintptr_t)DEFAULT_DMIBAR | 1); |
| 63 | pci_write_config32(D0F0, PMIOBAR, (uintptr_t)0x400 | 1); |
| 64 | |
| 65 | |
| 66 | reg32 = MCHBAR32(0x30); |
| 67 | MCHBAR32(0x30) = 0x21800; |
| 68 | DMIBAR32(0x2c) = 0x86000040; |
| 69 | pci_write_config8(D0F0, DEVEN, 0x09); |
| 70 | pci_write_config32(PCI_DEV(0, 0x1e, 0), 0x18, 0x00020200); |
| 71 | pci_write_config32(PCI_DEV(0, 0x1e, 0), 0x18, 0x00000000); |
| 72 | reg8 = pci_read_config8(D0F0, 0xe5); // 0x10 |
| 73 | reg16 = pci_read_config16(PCI_DEV(0, 0x02, 0), 0x0); // 0x8086 |
| 74 | |
| 75 | reg16 = pci_read_config16(D0F0, GGC); |
| 76 | pci_write_config16(D0F0, GGC, 0x130); |
| 77 | reg16 = pci_read_config16(D0F0, GGC); |
| 78 | pci_write_config16(D0F0, GGC, 0x130); |
| 79 | MCHBAR8(0xb08) = 0x20; |
| 80 | reg8 = pci_read_config8(D0F0, 0xe6); // 0x11 |
| 81 | reg16 = MCHBAR16(0xc8c); |
| 82 | MCHBAR16(0xc8c) = reg16 | 0x0200; |
| 83 | reg8 = MCHBAR8(0xc8c); |
| 84 | MCHBAR8(0xc8c) = reg8; |
| 85 | MCHBAR8(0xc8c) = 0x12; |
| 86 | pci_write_config8(PCI_DEV(0, 0x02, 0), 0x62, 0x02); |
| 87 | pci_write_config16(PCI_DEV(0, 0x02, 0), 0xe8, 0x8000); |
| 88 | MCHBAR32(0x3004) = 0x48000000; |
| 89 | MCHBAR32(0x3008) = 0xfffffe00; |
| 90 | MCHBAR32(0xb08) = 0x06028220; |
| 91 | MCHBAR32(0xff4) = 0xc6db8b5f; |
| 92 | MCHBAR16(0xff8) = 0x024f; |
| 93 | |
| 94 | // PLL Voltage controlled oscillator |
| 95 | //MCHBAR8(0xc38) = 0x04; |
| 96 | |
| 97 | pci_write_config16(PCI_DEV(0, 0x02, 0), 0xcc, 0x014d); |
| 98 | reg32 = MCHBAR32(0x40); |
| 99 | MCHBAR32(0x40) = 0x0; |
| 100 | reg32 = MCHBAR32(0x40); |
| 101 | MCHBAR32(0x40) = 0x8; |
| 102 | |
| 103 | pci_write_config8(LPC, 0x8, 0x1d); |
| 104 | pci_write_config8(LPC, 0x8, 0x0); |
| 105 | RCBA32(0x3410) = 0x00020465; |
| 106 | RCBA32(0x88) = 0x0011d000; |
| 107 | RCBA32(0x1fc) = 0x60f; |
| 108 | RCBA32(0x1f4) = 0x86000040; |
| 109 | RCBA32(0x214) = 0x10030509; |
| 110 | RCBA32(0x218) = 0x00020504; |
| 111 | RCBA32(0x220) = 0xc5; |
| 112 | RCBA32(0x3430) = 0x1; |
| 113 | RCBA32(0x2027) = 0x38f6a70d; |
| 114 | RCBA16(0x3e08) = 0x0080; |
| 115 | RCBA16(0x3e48) = 0x0080; |
| 116 | RCBA32(0x3e0e) = 0x00000080; |
| 117 | RCBA32(0x3e4e) = 0x00000080; |
| 118 | RCBA32(0x2034) = 0xb24577cc; |
| 119 | RCBA32(0x1c) = 0x03128010; |
| 120 | RCBA32(0x2010) = 0x400; |
| 121 | RCBA32(0x3400) = 0x4; |
| 122 | RCBA32(0x2080) = 0x18006007; |
| 123 | RCBA32(0x20a0) = 0x18006007; |
| 124 | RCBA32(0x20c0) = 0x18006007; |
| 125 | RCBA32(0x20e0) = 0x18006007; |
| 126 | |
| 127 | pci_write_config32(PCI_DEV(0, 0x1d, 0), 0xca, 0x1); |
| 128 | pci_write_config32(PCI_DEV(0, 0x1d, 1), 0xca, 0x1); |
| 129 | pci_write_config32(PCI_DEV(0, 0x1d, 2), 0xca, 0x1); |
| 130 | pci_write_config32(PCI_DEV(0, 0x1d, 3), 0xca, 0x1); |
| 131 | |
| 132 | RCBA32(0x3100) = 0x42210; |
| 133 | RCBA32(0x3108) = 0x10004321; |
| 134 | RCBA32(0x310c) = 0x00214321; |
| 135 | RCBA32(0x3110) = 0x1; |
| 136 | RCBA32(0x3140) = 0x01460132; |
| 137 | RCBA32(0x3142) = 0x02370146; |
| 138 | RCBA32(0x3144) = 0x32010237; |
| 139 | RCBA32(0x3146) = 0x01463201; |
| 140 | RCBA32(0x3148) = 0x146; |
| 141 | |
| 142 | /* Set C0000-FFFFF to access RAM on both reads and writes */ |
| 143 | pci_write_config8(D0F0, PAM0, 0x30); |
| 144 | pci_write_config8(D0F0, PAM1, 0x33); |
| 145 | pci_write_config8(D0F0, PAM2, 0x33); |
| 146 | pci_write_config8(D0F0, PAM3, 0x33); |
| 147 | pci_write_config8(D0F0, PAM4, 0x33); |
| 148 | pci_write_config8(D0F0, PAM5, 0x33); |
| 149 | pci_write_config8(D0F0, PAM6, 0x33); |
| 150 | |
| 151 | pci_write_config32(D0F0, SKPAD, SKPAD_NORMAL_BOOT_MAGIC); |
| 152 | printk(BIOS_DEBUG, " done.\n"); |
| 153 | } |
| 154 | |
| 155 | void pineview_early_initialization(void) |
| 156 | { |
| 157 | /* Print some chipset specific information */ |
| 158 | printk(BIOS_DEBUG, "Intel Pineview northbridge\n"); |
| 159 | |
| 160 | /* Setup all BARs required for early PCIe and raminit */ |
| 161 | pineview_setup_bars(); |
| 162 | |
| 163 | /* Change port80 to LPC */ |
| 164 | RCBA32(GCS) &= (~0x04); |
| 165 | RCBA32(0x2010) |= (1 << 10); |
| 166 | } |