| Joseph Smith | 6a1dc86 | 2008-03-09 13:24:46 +0000 | [diff] [blame] | 1 | /* |
| 2 | * This file is part of the coreboot project. |
| 3 | * |
| 4 | * Copyright (C) 2008 Joseph Smith <joe@smittys.pointclark.net> |
| 5 | * |
| 6 | * This program is free software; you can redistribute it and/or modify |
| 7 | * it under the terms of the GNU General Public License as published by |
| 8 | * the Free Software Foundation; either version 2 of the License, or |
| 9 | * (at your option) any later version. |
| 10 | * |
| 11 | * This program is distributed in the hope that it will be useful, |
| 12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 14 | * GNU General Public License for more details. |
| Joseph Smith | 6a1dc86 | 2008-03-09 13:24:46 +0000 | [diff] [blame] | 15 | */ |
| 16 | |
| 17 | #define RRBAR 0x48 /* Register Range Base Address (0x00000000) */ |
| 18 | #define GCC0 0x50 /* GMCH Control #0 (0xa072) */ |
| 19 | #define GCC1 0x52 /* GMCH Control #1 (0x0000) */ |
| 20 | #define FDHC 0x58 /* Fixed DRAM Hole Control (0x00) */ |
| 21 | #define PAM0 0x59 /* Programable Attribute Map #0 (0x00) */ |
| 22 | #define PAM1 0x5a /* Programable Attribute Map #1 (0x00) */ |
| 23 | #define PAM2 0x5b /* Programable Attribute Map #2 (0x00) */ |
| 24 | #define PAM3 0x5c /* Programable Attribute Map #3 (0x00) */ |
| 25 | #define PAM4 0x5d /* Programable Attribute Map #4 (0x00) */ |
| 26 | #define PAM5 0x5e /* Programable Attribute Map #5 (0x00) */ |
| 27 | #define PAM6 0x5f /* Programable Attribute Map #6 (0x00) */ |
| 28 | #define DRB 0x60 /* DRAM Row Boundary #0 (0x00) */ |
| 29 | #define DRB1 0x61 /* DRAM Row Boundary #1 (0x00) */ |
| 30 | #define DRB2 0x62 /* DRAM Row Boundary #2 (0x00) */ |
| 31 | #define DRB3 0x63 /* DRAM Row Boundary #3 (0x00) */ |
| 32 | #define DRA 0x70 /* DRAM Row Attribute #0 (0xff) */ |
| 33 | #define DRA1 0x71 /* DRAM Row Attribute #1 (0xff) */ |
| 34 | #define DRT 0x78 /* DRAM Timing (0x00000010) */ |
| 35 | #define DRC 0x7c /* DRAM Controller Mode #0 (0x00000000) */ |
| 36 | #define DRC1 0x7d /* DRAM Controller Mode #1 (0x00000000) */ |
| 37 | #define DRC2 0x7e /* DRAM Controller Mode #2 (0x00000000) */ |
| 38 | #define DRC3 0x7f /* DRAM Controller Mode #3 (0x00000000) */ |
| 39 | #define DTC 0x8c /* DRAM Throttling Control (0x00000000) */ |
| 40 | #define SMRAM 0x90 /* System Management RAM Control (0x02) */ |
| 41 | #define ESMRAMC 0x91 /* Extended System Management RAM Control Reg. (0x38) */ |
| 42 | #define ERRSTS 0x92 /* Error Status (0x0000) */ |
| 43 | #define ERRCMD 0x94 /* Error Command (0x0000) */ |
| 44 | #define BUFF_SC 0xec /* System Memory Buffer Strength Control (0x00000000) */ |
| 45 | #define APBASE 0x10 /* Aperture Base Configuration (0x00000008) */ |
| 46 | #define APSIZE 0xb4 /* Apterture Size (0x00) */ |
| 47 | #define ATTBASE 0xb8 /* Aperture Translation Table Base (0x00000000) */ |