Ed Swierk | a9faea8 | 2008-03-16 23:36:00 +0000 | [diff] [blame] | 1 | /* |
| 2 | * This file is part of the coreboot project. |
| 3 | * |
| 4 | * Copyright (C) 2008 Arastra, Inc. |
| 5 | * |
| 6 | * This program is free software; you can redistribute it and/or modify |
Uwe Hermann | c70e9fc | 2010-02-15 23:10:19 +0000 | [diff] [blame] | 7 | * it under the terms of the GNU General Public License as published by |
| 8 | * the Free Software Foundation; version 2 of the License. |
Ed Swierk | a9faea8 | 2008-03-16 23:36:00 +0000 | [diff] [blame] | 9 | * |
| 10 | * This program is distributed in the hope that it will be useful, |
| 11 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 12 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 13 | * GNU General Public License for more details. |
Ed Swierk | a9faea8 | 2008-03-16 23:36:00 +0000 | [diff] [blame] | 14 | */ |
| 15 | |
| 16 | /* This code is based on src/northbridge/intel/e7520/raminit.h */ |
| 17 | |
| 18 | #ifndef NORTHBRIDGE_INTEL_I3100_RAMINIT_H |
| 19 | #define NORTHBRIDGE_INTEL_I3100_RAMINIT_H |
| 20 | |
| 21 | #define DIMM_SOCKETS 4 |
| 22 | struct mem_controller { |
| 23 | u32 node_id; |
| 24 | device_t f0, f1, f2, f3; |
| 25 | u16 channel0[DIMM_SOCKETS]; |
| 26 | u16 channel1[DIMM_SOCKETS]; |
| 27 | }; |
| 28 | |
Stefan Reinauer | d653211 | 2010-04-16 00:31:44 +0000 | [diff] [blame] | 29 | void sdram_initialize(int controllers, const struct mem_controller *ctrl); |
| 30 | |
Ed Swierk | a9faea8 | 2008-03-16 23:36:00 +0000 | [diff] [blame] | 31 | #endif |