Aaron Durbin | 6d04f0f | 2012-10-31 22:57:16 -0500 | [diff] [blame] | 1 | #include <arch/io.h> |
Aaron Durbin | 6d04f0f | 2012-10-31 22:57:16 -0500 | [diff] [blame] | 2 | |
| 3 | /* Just re-define this instead of including haswell.h. It blows up romcc. */ |
| 4 | #define PCIEXBAR 0x60 |
| 5 | |
| 6 | static void bootblock_northbridge_init(void) |
| 7 | { |
| 8 | uint32_t reg; |
| 9 | |
| 10 | /* |
| 11 | * The "io" variant of the config access is explicitly used to |
| 12 | * setup the PCIEXBAR because CONFIG_MMCONF_SUPPORT_DEFAULT is set to |
| 13 | * to true. That way all subsequent non-explicit config accesses use |
| 14 | * MCFG. This code also assumes that bootblock_northbridge_init() is |
| 15 | * the first thing called in the non-asm boot block code. The final |
| 16 | * assumption is that no assembly code is using the |
| 17 | * CONFIG_MMCONF_SUPPORT_DEFAULT option to do PCI config acceses. |
| 18 | * |
| 19 | * The PCIEXBAR is assumed to live in the memory mapped IO space under |
| 20 | * 4GiB. |
| 21 | */ |
| 22 | reg = 0; |
| 23 | pci_io_write_config32(PCI_DEV(0,0,0), PCIEXBAR + 4, reg); |
| 24 | reg = CONFIG_MMCONF_BASE_ADDRESS | 4 | 1; /* 64MiB - 0-63 buses. */ |
| 25 | pci_io_write_config32(PCI_DEV(0,0,0), PCIEXBAR, reg); |
| 26 | } |